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Commit 7b87c164 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'renesas-dts-for-v6.5-tag2' of... 

Merge tag 'renesas-dts-for-v6.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt

Renesas DTS updates for v6.5 (take two)

  - Add IOMMU support for PCIe devices on R-Car Gen3 and RZ/G2 SoCs,
  - Add HSCIF1 serial port support on Renesas ULCB boards equipped with
    the Shimafuji Kingfisher extension,
  - Miscellaneous fixes and improvements.

* tag 'renesas-dts-for-v6.5-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
  arm64: dts: renesas: ulcb-kf: Add HSCIF1 node
  arm64: dts: renesas: ulcb-kf: Remove flow control for SCIF1
  ARM: dts: iwg20d-q7-common: Fix backlight pwm specifier
  arm64: dts: renesas: Add IOMMU related properties into PCIe host nodes

Link: https://lore.kernel.org/r/cover.1686304614.git.geert+renesas@glider.beSigned-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 1b84450e c776a212
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Showing with 84 additions and 36 deletions
arch/arm/boot/dts/iwg20d-q7-common.dtsi
View file @ 7b87c164
......@@ -49,7 +49,7 @@ audio_clock: audio_clock {
lcd_backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 5000000 0>;
pwms = <&pwm3 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <7>;
enable-gpios = <&gpio5 14 GPIO_ACTIVE_HIGH>;
......
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View file @ 7b87c164
......@@ -2359,8 +2359,8 @@ pciec0: pcie@fe000000 {
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
/* Map all possible DDR/IOMMU as inbound ranges */
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
......@@ -2371,6 +2371,8 @@ pciec0: pcie@fe000000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 319>;
iommu-map = <0 &ipmmu_hc 0 1>;
iommu-map-mask = <0>;
status = "disabled";
};
......@@ -2386,8 +2388,8 @@ pciec1: pcie@ee800000 {
<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
/* Map all possible DDR/IOMMU as inbound ranges */
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
......@@ -2398,6 +2400,8 @@ pciec1: pcie@ee800000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 318>;
iommu-map = <0 &ipmmu_hc 1 1>;
iommu-map-mask = <0>;
status = "disabled";
};
......
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
View file @ 7b87c164
......@@ -2238,8 +2238,8 @@ pciec0: pcie@fe000000 {
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
/* Map all possible DDR/IOMMU as inbound ranges */
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
......@@ -2250,6 +2250,8 @@ pciec0: pcie@fe000000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 319>;
iommu-map = <0 &ipmmu_hc 0 1>;
iommu-map-mask = <0>;
status = "disabled";
};
......@@ -2265,8 +2267,8 @@ pciec1: pcie@ee800000 {
<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
/* Map all possible DDR/IOMMU as inbound ranges */
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
......@@ -2277,6 +2279,8 @@ pciec1: pcie@ee800000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 318>;
iommu-map = <0 &ipmmu_hc 1 1>;
iommu-map-mask = <0>;
status = "disabled";
};
......
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
View file @ 7b87c164
......@@ -1704,8 +1704,8 @@ pciec0: pcie@fe000000 {
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
/* Map all possible DDR/IOMMU as inbound ranges */
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1716,6 +1716,8 @@ pciec0: pcie@fe000000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 319>;
iommu-map = <0 &ipmmu_hc 0 1>;
iommu-map-mask = <0>;
status = "disabled";
};
......
arch/arm64/boot/dts/renesas/r8a774e1.dtsi
View file @ 7b87c164
......@@ -2471,8 +2471,8 @@ pciec0: pcie@fe000000 {
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
/* Map all possible DDR/IOMMU as inbound ranges */
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
......@@ -2483,6 +2483,8 @@ pciec0: pcie@fe000000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 319>;
iommu-map = <0 &ipmmu_hc 0 1>;
iommu-map-mask = <0>;
status = "disabled";
};
......@@ -2498,8 +2500,8 @@ pciec1: pcie@ee800000 {
<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
/* Map all possible DDR/IOMMU as inbound ranges */
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
......@@ -2510,6 +2512,8 @@ pciec1: pcie@ee800000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 318>;
iommu-map = <0 &ipmmu_hc 1 1>;
iommu-map-mask = <0>;
status = "disabled";
};
......
arch/arm64/boot/dts/renesas/r8a77951.dtsi
View file @ 7b87c164
......@@ -2778,8 +2778,8 @@ pciec0: pcie@fe000000 {
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
/* Map all possible DDR/IOMMU as inbound ranges */
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
......@@ -2790,6 +2790,8 @@ pciec0: pcie@fe000000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 319>;
iommu-map = <0 &ipmmu_hc 0 1>;
iommu-map-mask = <0>;
status = "disabled";
};
......@@ -2805,8 +2807,8 @@ pciec1: pcie@ee800000 {
<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
/* Map all possible DDR/IOMMU as inbound ranges */
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
......@@ -2817,6 +2819,8 @@ pciec1: pcie@ee800000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 318>;
iommu-map = <0 &ipmmu_hc 1 1>;
iommu-map-mask = <0>;
status = "disabled";
};
......
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View file @ 7b87c164
......@@ -2565,8 +2565,8 @@ pciec0: pcie@fe000000 {
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
/* Map all possible DDR/IOMMU as inbound ranges */
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
......@@ -2577,6 +2577,8 @@ pciec0: pcie@fe000000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 319>;
iommu-map = <0 &ipmmu_hc 0 1>;
iommu-map-mask = <0>;
status = "disabled";
};
......@@ -2592,8 +2594,8 @@ pciec1: pcie@ee800000 {
<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
/* Map all possible DDR/IOMMU as inbound ranges */
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
......@@ -2604,6 +2606,8 @@ pciec1: pcie@ee800000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
resets = <&cpg 318>;
iommu-map = <0 &ipmmu_hc 1 1>;
iommu-map-mask = <0>;
status = "disabled";
};
......
arch/arm64/boot/dts/renesas/r8a77961.dtsi
View file @ 7b87c164
......@@ -2445,8 +2445,8 @@ pciec0: pcie@fe000000 {
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
/* Map all possible DDR/IOMMU as inbound ranges */
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
......@@ -2457,6 +2457,8 @@ pciec0: pcie@fe000000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 319>;
iommu-map = <0 &ipmmu_hc 0 1>;
iommu-map-mask = <0>;
status = "disabled";
};
......@@ -2472,8 +2474,8 @@ pciec1: pcie@ee800000 {
<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
/* Map all possible DDR/IOMMU as inbound ranges */
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
......@@ -2484,6 +2486,8 @@ pciec1: pcie@ee800000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
resets = <&cpg 318>;
iommu-map = <0 &ipmmu_hc 1 1>;
iommu-map-mask = <0>;
status = "disabled";
};
......
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View file @ 7b87c164
......@@ -2423,8 +2423,8 @@ pciec0: pcie@fe000000 {
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
/* Map all possible DDR/IOMMU as inbound ranges */
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
......@@ -2435,6 +2435,8 @@ pciec0: pcie@fe000000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 319>;
iommu-map = <0 &ipmmu_hc 0 1>;
iommu-map-mask = <0>;
status = "disabled";
};
......@@ -2450,8 +2452,8 @@ pciec1: pcie@ee800000 {
<0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>,
<0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>,
<0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
/* Map all possible DDR/IOMMU as inbound ranges */
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
......@@ -2462,6 +2464,8 @@ pciec1: pcie@ee800000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
resets = <&cpg 318>;
iommu-map = <0 &ipmmu_hc 1 1>;
iommu-map-mask = <0>;
status = "disabled";
};
......
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View file @ 7b87c164
......@@ -1386,7 +1386,8 @@ pciec: pcie@fe000000 {
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>;
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
/* Map all possible DDR/IOMMU as inbound ranges */
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1399,6 +1400,8 @@ pciec: pcie@fe000000 {
resets = <&cpg 319>;
phys = <&pcie_phy>;
phy-names = "pcie";
iommu-map = <0 &ipmmu_vi0 5 1>;
iommu-map-mask = <0>;
status = "disabled";
};
......
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View file @ 7b87c164
......@@ -1870,8 +1870,8 @@ pciec0: pcie@fe000000 {
<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
/* Map all possible DDR as inbound ranges */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
/* Map all possible DDR/IOMMU as inbound ranges */
dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
......@@ -1882,6 +1882,8 @@ pciec0: pcie@fe000000 {
clock-names = "pcie", "pcie_bus";
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 319>;
iommu-map = <0 &ipmmu_hc 0 1>;
iommu-map-mask = <0>;
status = "disabled";
};
......
arch/arm64/boot/dts/renesas/ulcb-kf.dtsi
View file @ 7b87c164
......@@ -10,6 +10,7 @@ / {
aliases {
serial1 = &hscif0;
serial2 = &scif1;
serial3 = &hscif1;
mmc2 = &sdhi3;
};
......@@ -114,6 +115,14 @@ &hscif0 {
status = "okay";
};
&hscif1 {
pinctrl-0 = <&hscif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
&hsusb {
dr_mode = "otg";
status = "okay";
......@@ -366,8 +375,13 @@ hscif0_pins: hscif0 {
function = "hscif0";
};
hscif1_pins: hscif1 {
groups = "hscif1_data_a", "hscif1_ctrl_a";
function = "hscif1";
};
scif1_pins: scif1 {
groups = "scif1_data_b", "scif1_ctrl";
groups = "scif1_data_b";
function = "scif1";
};
......@@ -397,7 +411,6 @@ &sound_clk_pins
&scif1 {
pinctrl-0 = <&scif1_pins>;
pinctrl-names = "default";
uart-has-rtscts;
status = "okay";
};
......
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