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Commit 7c865b09 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
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arm64: dts: qcom: msm8994: Modernize the DTS style 

Following changes have been made:

- remove name, compatible and msm-id
- wrap clocks in clocks{}
- order nodes by name and by address
- clock_gcc -> gcc
- msmgpio -> tlmm
- qcom,smem -> smem
- remove unit-address from smem
- retire msm8994-pins.dtsi
- add some of the missing pins
- make comments C-style
Signed-off-by: default avatarKonrad Dybcio <konradybcio@gmail.com>
Link: https://lore.kernel.org/r/20200623224813.297077-2-konradybcio@gmail.comSigned-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 23a89037
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Showing with 225 additions and 95 deletions
arch/arm64/boot/dts/qcom/msm8994-pins.dtsi deleted 100644 → 0
View file @ 23a89037
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
*/
&msmgpio {
blsp1_uart2_default: blsp1_uart2_default {
pinmux {
function = "blsp_uart2";
pins = "gpio4", "gpio5";
};
pinconf {
pins = "gpio4", "gpio5";
drive-strength = <16>;
bias-disable;
};
};
blsp1_uart2_sleep: blsp1_uart2_sleep {
pinmux {
function = "gpio";
pins = "gpio4", "gpio5";
};
pinconf {
pins = "gpio4", "gpio5";
drive-strength = <2>;
bias-pull-down;
};
};
};
arch/arm64/boot/dts/qcom/msm8994.dtsi
View file @ 7c865b09
...@@ -6,12 +6,6 @@ ...@@ -6,12 +6,6 @@
#include <dt-bindings/clock/qcom,gcc-msm8994.h> #include <dt-bindings/clock/qcom,gcc-msm8994.h>
/ { / {
model = "Qualcomm Technologies, Inc. MSM 8994";
compatible = "qcom,msm8994";
// msm-id and pmic-id are required by bootloader for
// proper selection of dt blob
qcom,msm-id = <207 0x20000>;
qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
interrupt-parent = <&intc>; interrupt-parent = <&intc>;
#address-cells = <2>; #address-cells = <2>;
...@@ -19,6 +13,20 @@ / { ...@@ -19,6 +13,20 @@ / {
chosen { }; chosen { };
clocks {
xo_board: xo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
};
sleep_clk: sleep_clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
};
};
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -42,12 +50,27 @@ L2_0: l2-cache { ...@@ -42,12 +50,27 @@ L2_0: l2-cache {
}; };
}; };
timer { memory {
compatible = "arm,armv8-timer"; device_type = "memory";
interrupts = <1 2 0xff08>, /* We expect the bootloader to fill in the reg */
<1 3 0xff08>, reg = <0 0 0 0>;
<1 4 0xff08>, };
<1 1 0xff08>;
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
smem_mem: smem_region@6a00000 {
reg = <0x0 0x6a00000 0x0 0x200000>;
no-map;
};
};
smem {
compatible = "qcom,smem";
memory-region = <&smem_mem>;
hwlocks = <&tcsr_mutex 3>;
}; };
soc: soc { soc: soc {
...@@ -62,7 +85,7 @@ intc: interrupt-controller@f9000000 { ...@@ -62,7 +85,7 @@ intc: interrupt-controller@f9000000 {
interrupt-controller; interrupt-controller;
#interrupt-cells = <3>; #interrupt-cells = <3>;
reg = <0xf9000000 0x1000>, reg = <0xf9000000 0x1000>,
<0xf9002000 0x1000>; <0xf9002000 0x1000>;
}; };
timer@f9020000 { timer@f9020000 {
...@@ -123,72 +146,209 @@ frame@f9028000 { ...@@ -123,72 +146,209 @@ frame@f9028000 {
}; };
}; };
blsp1_uart2: serial@f991e000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0xf991e000 0x1000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clock-names = "core", "iface";
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
};
gcc: clock-controller@fc400000 {
compatible = "qcom,gcc-msm8994";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0xfc400000 0x2000>;
};
restart@fc4ab000 { restart@fc4ab000 {
compatible = "qcom,pshold"; compatible = "qcom,pshold";
reg = <0xfc4ab000 0x4>; reg = <0xfc4ab000 0x4>;
}; };
msmgpio: pinctrl@fd510000 { tcsr_mutex_regs: syscon@fd484000 {
compatible = "syscon";
reg = <0xfd484000 0x2000>;
};
tlmm: pinctrl@fd510000 {
compatible = "qcom,msm8994-pinctrl"; compatible = "qcom,msm8994-pinctrl";
reg = <0xfd510000 0x4000>; reg = <0xfd510000 0x4000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller; gpio-controller;
gpio-ranges = <&msmgpio 0 0 146>; gpio-ranges = <&tlmm 0 0 146>;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
};
blsp1_uart2: serial@f991e000 { blsp1_uart2_default: blsp1-uart2-default {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; function = "blsp_uart2";
reg = <0xf991e000 0x1000>; pins = "gpio4", "gpio5";
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; drive-strength = <16>;
status = "disabled"; bias-disable;
clock-names = "core", "iface"; };
clocks = <&clock_gcc GCC_BLSP1_UART2_APPS_CLK>,
<&clock_gcc GCC_BLSP1_AHB_CLK>;
};
tcsr_mutex_regs: syscon@fd484000 { blsp1_uart2_sleep: blsp1-uart2-sleep {
compatible = "syscon"; function = "gpio";
reg = <0xfd484000 0x2000>; pins = "gpio4", "gpio5";
}; drive-strength = <2>;
bias-pull-down;
};
clock_gcc: clock-controller@fc400000 { blsp2_uart2_default: blsp2-uart2-default {
compatible = "qcom,gcc-msm8994"; function = "blsp_uart8";
#clock-cells = <1>; pins = "gpio45", "gpio46";
#reset-cells = <1>; drive-strength = <2>;
#power-domain-cells = <1>; bias-disable;
reg = <0xfc400000 0x2000>; };
};
};
memory { blsp2_uart2_sleep: blsp2-uart2-sleep {
device_type = "memory"; function = "gpio";
// We expect the bootloader to fill in the reg pins = "gpio45", "gpio46";
reg = <0 0 0 0>; drive-strength = <2>;
}; bias-pull-down;
};
xo_board: xo_board { i2c1_default: i2c1-default {
compatible = "fixed-clock"; function = "blsp_i2c1";
#clock-cells = <0>; pins = "gpio2", "gpio3";
clock-frequency = <19200000>; drive-strength = <2>;
}; bias-disable;
};
sleep_clk: sleep_clk { i2c1_sleep: i2c1-sleep {
compatible = "fixed-clock"; function = "gpio";
#clock-cells = <0>; pins = "gpio2", "gpio3";
clock-frequency = <32768>; drive-strength = <2>;
}; bias-disable;
};
reserved-memory { i2c2_default: i2c2-default {
#address-cells = <2>; function = "blsp_i2c2";
#size-cells = <2>; pins = "gpio6", "gpio7";
ranges; drive-strength = <2>;
bias-disable;
};
smem_mem: smem_region@6a00000 { i2c2_sleep: i2c2-sleep {
reg = <0x0 0x6a00000 0x0 0x200000>; function = "gpio";
no-map; pins = "gpio6", "gpio7";
drive-strength = <2>;
bias-disable;
};
i2c4_default: i2c4-default {
function = "blsp_i2c4";
pins = "gpio19", "gpio20";
drive-strength = <2>;
bias-disable;
};
i2c4_sleep: i2c4-sleep {
function = "gpio";
pins = "gpio19", "gpio20";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
i2c5_default: i2c5-default {
function = "blsp_i2c5";
pins = "gpio23", "gpio24";
drive-strength = <2>;
bias-disable;
};
i2c5_sleep: i2c5-sleep {
function = "gpio";
pins = "gpio23", "gpio24";
drive-strength = <2>;
bias-disable;
};
i2c6_default: i2c6-default {
function = "blsp_i2c6";
pins = "gpio28", "gpio27";
drive-strength = <2>;
bias-disable;
};
i2c6_sleep: i2c6-sleep {
function = "gpio";
pins = "gpio28", "gpio27";
drive-strength = <2>;
bias-disable;
};
blsp1_spi0_default: blsp1-spi0-default {
default {
function = "blsp_spi1";
pins = "gpio0", "gpio1", "gpio3";
drive-strength = <10>;
bias-pull-down;
};
cs {
function = "gpio";
pins = "gpio8";
drive-strength = <2>;
bias-disable;
};
};
blsp1_spi0_sleep: blsp1-spi0-sleep {
pins = "gpio0", "gpio1", "gpio3";
drive-strength = <2>;
bias-disable;
};
sdc1_clk_on: clk-on {
pins = "sdc1_clk";
bias-disable;
drive-strength = <16>;
};
sdc1_clk_off: clk-off {
pins = "sdc1_clk";
bias-disable;
drive-strength = <2>;
};
sdc1_cmd_on: cmd-on {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <8>;
};
sdc1_cmd_off: cmd-off {
pins = "sdc1_cmd";
bias-pull-up;
drive-strength = <2>;
};
sdc1_data_on: data-on {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <8>;
};
sdc1_data_off: data-off {
pins = "sdc1_data";
bias-pull-up;
drive-strength = <2>;
};
sdc1_rclk_on: rclk-on {
pins = "sdc1_rclk";
bias-pull-down;
};
sdc1_rclk_off: rclk-off {
pins = "sdc1_rclk";
bias-pull-down;
};
}; };
}; };
...@@ -198,12 +358,12 @@ tcsr_mutex: hwlock { ...@@ -198,12 +358,12 @@ tcsr_mutex: hwlock {
#hwlock-cells = <1>; #hwlock-cells = <1>;
}; };
qcom,smem@6a00000 { timer {
compatible = "qcom,smem"; compatible = "arm,armv8-timer";
memory-region = <&smem_mem>; interrupts = <GIC_PPI 2 0xff08>,
hwlocks = <&tcsr_mutex 3>; <GIC_PPI 3 0xff08>,
<GIC_PPI 4 0xff08>,
<GIC_PPI 1 0xff08>;
}; };
}; };
#include "msm8994-pins.dtsi"
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