Commit 7cc16380 authored by Arvind Bhushan's avatar Arvind Bhushan Committed by David S. Miller

csiostor: Cleanup chip specific operations.

This patch removes chip specific operations from the common hardware
paths, as well as the Makefile change to accomodate the new files.
Signed-off-by: default avatarArvind Bhushan <arvindb@chelsio.com>
Signed-off-by: default avatarNaresh Kumar Inna <naresh@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d69630e8
...@@ -8,4 +8,5 @@ ccflags-y += -I$(srctree)/drivers/net/ethernet/chelsio/cxgb4 ...@@ -8,4 +8,5 @@ ccflags-y += -I$(srctree)/drivers/net/ethernet/chelsio/cxgb4
obj-$(CONFIG_SCSI_CHELSIO_FCOE) += csiostor.o obj-$(CONFIG_SCSI_CHELSIO_FCOE) += csiostor.o
csiostor-objs := csio_attr.o csio_init.o csio_lnode.o csio_scsi.o \ csiostor-objs := csio_attr.o csio_init.o csio_lnode.o csio_scsi.o \
csio_hw.o csio_isr.o csio_mb.o csio_rnode.o csio_wr.o csio_hw.o csio_hw_t4.o csio_hw_t5.o csio_isr.o \
csio_mb.o csio_rnode.o csio_wr.o
This diff is collapsed.
...@@ -48,6 +48,7 @@ ...@@ -48,6 +48,7 @@
#include <scsi/scsi_device.h> #include <scsi/scsi_device.h>
#include <scsi/scsi_transport_fc.h> #include <scsi/scsi_transport_fc.h>
#include "csio_hw_chip.h"
#include "csio_wr.h" #include "csio_wr.h"
#include "csio_mb.h" #include "csio_mb.h"
#include "csio_scsi.h" #include "csio_scsi.h"
...@@ -60,13 +61,6 @@ ...@@ -60,13 +61,6 @@
*/ */
#define FW_HOSTERROR 255 #define FW_HOSTERROR 255
#define CSIO_FW_FNAME "cxgb4/t4fw.bin"
#define CSIO_CF_FNAME "cxgb4/t4-config.txt"
#define FW_VERSION_MAJOR 1
#define FW_VERSION_MINOR 2
#define FW_VERSION_MICRO 8
#define CSIO_HW_NAME "Chelsio FCoE Adapter" #define CSIO_HW_NAME "Chelsio FCoE Adapter"
#define CSIO_MAX_PFN 8 #define CSIO_MAX_PFN 8
#define CSIO_MAX_PPORTS 4 #define CSIO_MAX_PPORTS 4
...@@ -123,8 +117,6 @@ extern int csio_msi; ...@@ -123,8 +117,6 @@ extern int csio_msi;
#define CSIO_VENDOR_ID 0x1425 #define CSIO_VENDOR_ID 0x1425
#define CSIO_ASIC_DEVID_PROTO_MASK 0xFF00 #define CSIO_ASIC_DEVID_PROTO_MASK 0xFF00
#define CSIO_ASIC_DEVID_TYPE_MASK 0x00FF #define CSIO_ASIC_DEVID_TYPE_MASK 0x00FF
#define CSIO_FPGA 0xA000
#define CSIO_T4_FCOE_ASIC 0x4600
#define CSIO_GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \ #define CSIO_GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \
EDC1 | LE | TP | MA | PM_TX | PM_RX | \ EDC1 | LE | TP | MA | PM_TX | PM_RX | \
...@@ -207,17 +199,6 @@ enum { ...@@ -207,17 +199,6 @@ enum {
SF_SIZE = SF_SEC_SIZE * 16, /* serial flash size */ SF_SIZE = SF_SEC_SIZE * 16, /* serial flash size */
}; };
enum { MEM_EDC0, MEM_EDC1, MEM_MC };
enum {
MEMWIN0_APERTURE = 2048,
MEMWIN0_BASE = 0x1b800,
MEMWIN1_APERTURE = 32768,
MEMWIN1_BASE = 0x28000,
MEMWIN2_APERTURE = 65536,
MEMWIN2_BASE = 0x30000,
};
/* serial flash and firmware constants */ /* serial flash and firmware constants */
enum { enum {
SF_ATTEMPTS = 10, /* max retries for SF operations */ SF_ATTEMPTS = 10, /* max retries for SF operations */
...@@ -239,9 +220,6 @@ enum { ...@@ -239,9 +220,6 @@ enum {
FLASH_CFG_MAX_SIZE = 0x10000 , /* max size of the flash config file*/ FLASH_CFG_MAX_SIZE = 0x10000 , /* max size of the flash config file*/
FLASH_CFG_OFFSET = 0x1f0000, FLASH_CFG_OFFSET = 0x1f0000,
FLASH_CFG_START_SEC = FLASH_CFG_OFFSET / SF_SEC_SIZE, FLASH_CFG_START_SEC = FLASH_CFG_OFFSET / SF_SEC_SIZE,
FPGA_FLASH_CFG_OFFSET = 0xf0000 , /* if FPGA mode, then cfg file is
* at 1MB - 64KB */
FPGA_FLASH_CFG_START_SEC = FPGA_FLASH_CFG_OFFSET / SF_SEC_SIZE,
}; };
/* /*
...@@ -259,6 +237,8 @@ enum { ...@@ -259,6 +237,8 @@ enum {
FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC), FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS), FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
/* Location of Firmware Configuration File in FLASH. */
FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
}; };
#undef FLASH_START #undef FLASH_START
...@@ -310,7 +290,7 @@ struct csio_adap_desc { ...@@ -310,7 +290,7 @@ struct csio_adap_desc {
struct pci_params { struct pci_params {
uint16_t vendor_id; uint16_t vendor_id;
uint16_t device_id; uint16_t device_id;
uint32_t vpd_cap_addr; int vpd_cap_addr;
uint16_t speed; uint16_t speed;
uint8_t width; uint8_t width;
}; };
...@@ -513,6 +493,7 @@ struct csio_hw { ...@@ -513,6 +493,7 @@ struct csio_hw {
uint32_t fwrev; uint32_t fwrev;
uint32_t tp_vers; uint32_t tp_vers;
char chip_ver; char chip_ver;
uint16_t chip_id; /* Tells T4/T5 chip */
uint32_t cfg_finiver; uint32_t cfg_finiver;
uint32_t cfg_finicsum; uint32_t cfg_finicsum;
uint32_t cfg_cfcsum; uint32_t cfg_cfcsum;
...@@ -556,6 +537,9 @@ struct csio_hw { ...@@ -556,6 +537,9 @@ struct csio_hw {
*/ */
struct csio_fcoe_res_info fres_info; /* Fcoe resource info */ struct csio_fcoe_res_info fres_info; /* Fcoe resource info */
struct csio_hw_chip_ops *chip_ops; /* T4/T5 Chip specific
* Operations
*/
/* MSIX vectors */ /* MSIX vectors */
struct csio_msix_entries msix_entries[CSIO_MAX_MSIX_VECS]; struct csio_msix_entries msix_entries[CSIO_MAX_MSIX_VECS];
...@@ -636,9 +620,16 @@ csio_us_to_core_ticks(struct csio_hw *hw, uint32_t us) ...@@ -636,9 +620,16 @@ csio_us_to_core_ticks(struct csio_hw *hw, uint32_t us)
#define csio_dbg(__hw, __fmt, ...) #define csio_dbg(__hw, __fmt, ...)
#endif #endif
int csio_hw_wait_op_done_val(struct csio_hw *, int, uint32_t, int,
int, int, uint32_t *);
void csio_hw_tp_wr_bits_indirect(struct csio_hw *, unsigned int,
unsigned int, unsigned int);
int csio_mgmt_req_lookup(struct csio_mgmtm *, struct csio_ioreq *); int csio_mgmt_req_lookup(struct csio_mgmtm *, struct csio_ioreq *);
void csio_hw_intr_disable(struct csio_hw *); void csio_hw_intr_disable(struct csio_hw *);
int csio_hw_slow_intr_handler(struct csio_hw *hw); int csio_hw_slow_intr_handler(struct csio_hw *);
int csio_handle_intr_status(struct csio_hw *, unsigned int,
const struct intr_info *);
int csio_hw_start(struct csio_hw *); int csio_hw_start(struct csio_hw *);
int csio_hw_stop(struct csio_hw *); int csio_hw_stop(struct csio_hw *);
int csio_hw_reset(struct csio_hw *); int csio_hw_reset(struct csio_hw *);
...@@ -647,19 +638,17 @@ int csio_is_hw_removing(struct csio_hw *); ...@@ -647,19 +638,17 @@ int csio_is_hw_removing(struct csio_hw *);
int csio_fwevtq_handler(struct csio_hw *); int csio_fwevtq_handler(struct csio_hw *);
void csio_evtq_worker(struct work_struct *); void csio_evtq_worker(struct work_struct *);
int csio_enqueue_evt(struct csio_hw *hw, enum csio_evt type, int csio_enqueue_evt(struct csio_hw *, enum csio_evt, void *, uint16_t);
void *evt_msg, uint16_t len);
void csio_evtq_flush(struct csio_hw *hw); void csio_evtq_flush(struct csio_hw *hw);
int csio_request_irqs(struct csio_hw *); int csio_request_irqs(struct csio_hw *);
void csio_intr_enable(struct csio_hw *); void csio_intr_enable(struct csio_hw *);
void csio_intr_disable(struct csio_hw *, bool); void csio_intr_disable(struct csio_hw *, bool);
void csio_hw_fatal_err(struct csio_hw *);
struct csio_lnode *csio_lnode_alloc(struct csio_hw *); struct csio_lnode *csio_lnode_alloc(struct csio_hw *);
int csio_config_queues(struct csio_hw *); int csio_config_queues(struct csio_hw *);
int csio_hw_mc_read(struct csio_hw *, uint32_t, __be32 *, uint64_t *);
int csio_hw_edc_read(struct csio_hw *, int, uint32_t, __be32 *, uint64_t *);
int csio_hw_init(struct csio_hw *); int csio_hw_init(struct csio_hw *);
void csio_hw_exit(struct csio_hw *); void csio_hw_exit(struct csio_hw *);
#endif /* ifndef __CSIO_HW_H__ */ #endif /* ifndef __CSIO_HW_H__ */
...@@ -81,9 +81,11 @@ csio_mem_read(struct file *file, char __user *buf, size_t count, loff_t *ppos) ...@@ -81,9 +81,11 @@ csio_mem_read(struct file *file, char __user *buf, size_t count, loff_t *ppos)
__be32 data[16]; __be32 data[16];
if (mem == MEM_MC) if (mem == MEM_MC)
ret = csio_hw_mc_read(hw, pos, data, NULL); ret = hw->chip_ops->chip_mc_read(hw, 0, pos,
data, NULL);
else else
ret = csio_hw_edc_read(hw, mem, pos, data, NULL); ret = hw->chip_ops->chip_edc_read(hw, mem, pos,
data, NULL);
if (ret) if (ret)
return ret; return ret;
...@@ -108,7 +110,7 @@ static const struct file_operations csio_mem_debugfs_fops = { ...@@ -108,7 +110,7 @@ static const struct file_operations csio_mem_debugfs_fops = {
.llseek = default_llseek, .llseek = default_llseek,
}; };
static void csio_add_debugfs_mem(struct csio_hw *hw, const char *name, void csio_add_debugfs_mem(struct csio_hw *hw, const char *name,
unsigned int idx, unsigned int size_mb) unsigned int idx, unsigned int size_mb)
{ {
struct dentry *de; struct dentry *de;
...@@ -131,9 +133,8 @@ static int csio_setup_debugfs(struct csio_hw *hw) ...@@ -131,9 +133,8 @@ static int csio_setup_debugfs(struct csio_hw *hw)
csio_add_debugfs_mem(hw, "edc0", MEM_EDC0, 5); csio_add_debugfs_mem(hw, "edc0", MEM_EDC0, 5);
if (i & EDRAM1_ENABLE) if (i & EDRAM1_ENABLE)
csio_add_debugfs_mem(hw, "edc1", MEM_EDC1, 5); csio_add_debugfs_mem(hw, "edc1", MEM_EDC1, 5);
if (i & EXT_MEM_ENABLE)
csio_add_debugfs_mem(hw, "mc", MEM_MC, hw->chip_ops->chip_dfs_create_ext_mem(hw);
EXT_MEM_SIZE_GET(csio_rd_reg32(hw, MA_EXT_MEMORY_BAR)));
return 0; return 0;
} }
...@@ -1169,7 +1170,7 @@ static struct pci_error_handlers csio_err_handler = { ...@@ -1169,7 +1170,7 @@ static struct pci_error_handlers csio_err_handler = {
}; };
static DEFINE_PCI_DEVICE_TABLE(csio_pci_tbl) = { static DEFINE_PCI_DEVICE_TABLE(csio_pci_tbl) = {
CSIO_DEVICE(CSIO_DEVID_T440DBG_FCOE, 0), /* T440DBG FCOE */ CSIO_DEVICE(CSIO_DEVID_T440DBG_FCOE, 0), /* T4 DEBUG FCOE */
CSIO_DEVICE(CSIO_DEVID_T420CR_FCOE, 0), /* T420CR FCOE */ CSIO_DEVICE(CSIO_DEVID_T420CR_FCOE, 0), /* T420CR FCOE */
CSIO_DEVICE(CSIO_DEVID_T422CR_FCOE, 0), /* T422CR FCOE */ CSIO_DEVICE(CSIO_DEVID_T422CR_FCOE, 0), /* T422CR FCOE */
CSIO_DEVICE(CSIO_DEVID_T440CR_FCOE, 0), /* T440CR FCOE */ CSIO_DEVICE(CSIO_DEVID_T440CR_FCOE, 0), /* T440CR FCOE */
...@@ -1184,8 +1185,34 @@ static DEFINE_PCI_DEVICE_TABLE(csio_pci_tbl) = { ...@@ -1184,8 +1185,34 @@ static DEFINE_PCI_DEVICE_TABLE(csio_pci_tbl) = {
CSIO_DEVICE(CSIO_DEVID_B404_FCOE, 0), /* B404 FCOE */ CSIO_DEVICE(CSIO_DEVID_B404_FCOE, 0), /* B404 FCOE */
CSIO_DEVICE(CSIO_DEVID_T480CR_FCOE, 0), /* T480 CR FCOE */ CSIO_DEVICE(CSIO_DEVID_T480CR_FCOE, 0), /* T480 CR FCOE */
CSIO_DEVICE(CSIO_DEVID_T440LPCR_FCOE, 0), /* T440 LP-CR FCOE */ CSIO_DEVICE(CSIO_DEVID_T440LPCR_FCOE, 0), /* T440 LP-CR FCOE */
CSIO_DEVICE(CSIO_DEVID_PE10K, 0), /* PE10K FCOE */ CSIO_DEVICE(CSIO_DEVID_AMSTERDAM_T4_FCOE, 0), /* AMSTERDAM T4 FCOE */
CSIO_DEVICE(CSIO_DEVID_PE10K_PF1, 0), /* PE10K FCOE on PF1 */ CSIO_DEVICE(CSIO_DEVID_HUAWEI_T480_FCOE, 0), /* HUAWEI T480 FCOE */
CSIO_DEVICE(CSIO_DEVID_HUAWEI_T440_FCOE, 0), /* HUAWEI T440 FCOE */
CSIO_DEVICE(CSIO_DEVID_HUAWEI_STG310_FCOE, 0), /* HUAWEI STG FCOE */
CSIO_DEVICE(CSIO_DEVID_ACROMAG_XMC_XAUI, 0), /* ACROMAG XAUI FCOE */
CSIO_DEVICE(CSIO_DEVID_QUANTA_MEZZ_SFP_FCOE, 0),/* QUANTA MEZZ FCOE */
CSIO_DEVICE(CSIO_DEVID_HUAWEI_10GT_FCOE, 0), /* HUAWEI 10GT FCOE */
CSIO_DEVICE(CSIO_DEVID_HUAWEI_T440_TOE_FCOE, 0),/* HUAWEI T4 TOE FCOE */
CSIO_DEVICE(CSIO_DEVID_T580DBG_FCOE, 0), /* T5 DEBUG FCOE */
CSIO_DEVICE(CSIO_DEVID_T520CR_FCOE, 0), /* T520CR FCOE */
CSIO_DEVICE(CSIO_DEVID_T522CR_FCOE, 0), /* T522CR FCOE */
CSIO_DEVICE(CSIO_DEVID_T540CR_FCOE, 0), /* T540CR FCOE */
CSIO_DEVICE(CSIO_DEVID_T520BCH_FCOE, 0), /* T520BCH FCOE */
CSIO_DEVICE(CSIO_DEVID_T540BCH_FCOE, 0), /* T540BCH FCOE */
CSIO_DEVICE(CSIO_DEVID_T540CH_FCOE, 0), /* T540CH FCOE */
CSIO_DEVICE(CSIO_DEVID_T520SO_FCOE, 0), /* T520SO FCOE */
CSIO_DEVICE(CSIO_DEVID_T520CX_FCOE, 0), /* T520CX FCOE */
CSIO_DEVICE(CSIO_DEVID_T520BT_FCOE, 0), /* T520BT FCOE */
CSIO_DEVICE(CSIO_DEVID_T504BT_FCOE, 0), /* T504BT FCOE */
CSIO_DEVICE(CSIO_DEVID_B520_FCOE, 0), /* B520 FCOE */
CSIO_DEVICE(CSIO_DEVID_B504_FCOE, 0), /* B504 FCOE */
CSIO_DEVICE(CSIO_DEVID_T580CR2_FCOE, 0), /* T580 CR FCOE */
CSIO_DEVICE(CSIO_DEVID_T540LPCR_FCOE, 0), /* T540 LP-CR FCOE */
CSIO_DEVICE(CSIO_DEVID_AMSTERDAM_T5_FCOE, 0), /* AMSTERDAM T5 FCOE */
CSIO_DEVICE(CSIO_DEVID_T580LPCR_FCOE, 0), /* T580 LP-CR FCOE */
CSIO_DEVICE(CSIO_DEVID_T520LLCR_FCOE, 0), /* T520 LL-CR FCOE */
CSIO_DEVICE(CSIO_DEVID_T560CR_FCOE, 0), /* T560 CR FCOE */
CSIO_DEVICE(CSIO_DEVID_T580CR_FCOE, 0), /* T580 CR FCOE */
{ 0, 0, 0, 0, 0, 0, 0 } { 0, 0, 0, 0, 0, 0, 0 }
}; };
...@@ -1259,4 +1286,5 @@ MODULE_DESCRIPTION(CSIO_DRV_DESC); ...@@ -1259,4 +1286,5 @@ MODULE_DESCRIPTION(CSIO_DRV_DESC);
MODULE_LICENSE(CSIO_DRV_LICENSE); MODULE_LICENSE(CSIO_DRV_LICENSE);
MODULE_DEVICE_TABLE(pci, csio_pci_tbl); MODULE_DEVICE_TABLE(pci, csio_pci_tbl);
MODULE_VERSION(CSIO_DRV_VERSION); MODULE_VERSION(CSIO_DRV_VERSION);
MODULE_FIRMWARE(CSIO_FW_FNAME); MODULE_FIRMWARE(FW_FNAME_T4);
MODULE_FIRMWARE(FW_FNAME_T5);
...@@ -52,31 +52,6 @@ ...@@ -52,31 +52,6 @@
#define CSIO_DRV_DESC "Chelsio FCoE driver" #define CSIO_DRV_DESC "Chelsio FCoE driver"
#define CSIO_DRV_VERSION "1.0.0" #define CSIO_DRV_VERSION "1.0.0"
#define CSIO_DEVICE(devid, idx) \
{ PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
#define CSIO_IS_T4_FPGA(_dev) (((_dev) == CSIO_DEVID_PE10K) ||\
((_dev) == CSIO_DEVID_PE10K_PF1))
/* FCoE device IDs */
#define CSIO_DEVID_PE10K 0xA000
#define CSIO_DEVID_PE10K_PF1 0xA001
#define CSIO_DEVID_T440DBG_FCOE 0x4600
#define CSIO_DEVID_T420CR_FCOE 0x4601
#define CSIO_DEVID_T422CR_FCOE 0x4602
#define CSIO_DEVID_T440CR_FCOE 0x4603
#define CSIO_DEVID_T420BCH_FCOE 0x4604
#define CSIO_DEVID_T440BCH_FCOE 0x4605
#define CSIO_DEVID_T440CH_FCOE 0x4606
#define CSIO_DEVID_T420SO_FCOE 0x4607
#define CSIO_DEVID_T420CX_FCOE 0x4608
#define CSIO_DEVID_T420BT_FCOE 0x4609
#define CSIO_DEVID_T404BT_FCOE 0x460A
#define CSIO_DEVID_B420_FCOE 0x460B
#define CSIO_DEVID_B404_FCOE 0x460C
#define CSIO_DEVID_T480CR_FCOE 0x460D
#define CSIO_DEVID_T440LPCR_FCOE 0x460E
extern struct fc_function_template csio_fc_transport_funcs; extern struct fc_function_template csio_fc_transport_funcs;
extern struct fc_function_template csio_fc_transport_vport_funcs; extern struct fc_function_template csio_fc_transport_vport_funcs;
...@@ -100,6 +75,10 @@ struct csio_lnode *csio_shost_init(struct csio_hw *, struct device *, bool, ...@@ -100,6 +75,10 @@ struct csio_lnode *csio_shost_init(struct csio_hw *, struct device *, bool,
void csio_shost_exit(struct csio_lnode *); void csio_shost_exit(struct csio_lnode *);
void csio_lnodes_exit(struct csio_hw *, bool); void csio_lnodes_exit(struct csio_hw *, bool);
/* DebugFS helper routines */
void csio_add_debugfs_mem(struct csio_hw *, const char *,
unsigned int, unsigned int);
static inline struct Scsi_Host * static inline struct Scsi_Host *
csio_ln_to_shost(struct csio_lnode *ln) csio_ln_to_shost(struct csio_lnode *ln)
{ {
......
...@@ -85,8 +85,8 @@ csio_wr_ring_fldb(struct csio_hw *hw, struct csio_q *flq) ...@@ -85,8 +85,8 @@ csio_wr_ring_fldb(struct csio_hw *hw, struct csio_q *flq)
*/ */
if (flq->inc_idx >= 8) { if (flq->inc_idx >= 8) {
csio_wr_reg32(hw, DBPRIO(1) | QID(flq->un.fl.flid) | csio_wr_reg32(hw, DBPRIO(1) | QID(flq->un.fl.flid) |
PIDX(flq->inc_idx / 8), CSIO_HW_PIDX(hw, flq->inc_idx / 8),
MYPF_REG(SGE_PF_KDOORBELL)); MYPF_REG(SGE_PF_KDOORBELL));
flq->inc_idx &= 7; flq->inc_idx &= 7;
} }
} }
...@@ -989,7 +989,8 @@ csio_wr_issue(struct csio_hw *hw, int qidx, bool prio) ...@@ -989,7 +989,8 @@ csio_wr_issue(struct csio_hw *hw, int qidx, bool prio)
wmb(); wmb();
/* Ring SGE Doorbell writing q->pidx into it */ /* Ring SGE Doorbell writing q->pidx into it */
csio_wr_reg32(hw, DBPRIO(prio) | QID(q->un.eq.physeqid) | csio_wr_reg32(hw, DBPRIO(prio) | QID(q->un.eq.physeqid) |
PIDX(q->inc_idx), MYPF_REG(SGE_PF_KDOORBELL)); CSIO_HW_PIDX(hw, q->inc_idx),
MYPF_REG(SGE_PF_KDOORBELL));
q->inc_idx = 0; q->inc_idx = 0;
return 0; return 0;
...@@ -1352,6 +1353,9 @@ csio_wr_fixup_host_params(struct csio_hw *hw) ...@@ -1352,6 +1353,9 @@ csio_wr_fixup_host_params(struct csio_hw *hw)
/* default value of rx_dma_offset of the NIC driver */ /* default value of rx_dma_offset of the NIC driver */
csio_set_reg_field(hw, SGE_CONTROL, PKTSHIFT_MASK, csio_set_reg_field(hw, SGE_CONTROL, PKTSHIFT_MASK,
PKTSHIFT(CSIO_SGE_RX_DMA_OFFSET)); PKTSHIFT(CSIO_SGE_RX_DMA_OFFSET));
csio_hw_tp_wr_bits_indirect(hw, TP_INGRESS_CONFIG,
CSUM_HAS_PSEUDO_HDR, 0);
} }
static void static void
...@@ -1467,10 +1471,11 @@ csio_wr_set_sge(struct csio_hw *hw) ...@@ -1467,10 +1471,11 @@ csio_wr_set_sge(struct csio_hw *hw)
* and generate an interrupt when this occurs so we can recover. * and generate an interrupt when this occurs so we can recover.
*/ */
csio_set_reg_field(hw, SGE_DBFIFO_STATUS, csio_set_reg_field(hw, SGE_DBFIFO_STATUS,
HP_INT_THRESH(HP_INT_THRESH_MASK) | HP_INT_THRESH(HP_INT_THRESH_MASK) |
LP_INT_THRESH(LP_INT_THRESH_MASK), CSIO_HW_LP_INT_THRESH(hw, CSIO_HW_M_LP_INT_THRESH(hw)),
HP_INT_THRESH(CSIO_SGE_DBFIFO_INT_THRESH) | HP_INT_THRESH(CSIO_SGE_DBFIFO_INT_THRESH) |
LP_INT_THRESH(CSIO_SGE_DBFIFO_INT_THRESH)); CSIO_HW_LP_INT_THRESH(hw, CSIO_SGE_DBFIFO_INT_THRESH));
csio_set_reg_field(hw, SGE_DOORBELL_CONTROL, ENABLE_DROP, csio_set_reg_field(hw, SGE_DOORBELL_CONTROL, ENABLE_DROP,
ENABLE_DROP); ENABLE_DROP);
......
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