Commit 7d207831 authored by Conor Dooley's avatar Conor Dooley Committed by Palmer Dabbelt

dt-bindings: arm: move cpu-capacity to a shared loation

RISC-V uses the same generic topology code as arm64 & while there
currently exists no binding for cpu-capacity on RISC-V, the code paths
can be hit if the property is present.

Move the documentation of cpu-capacity to a shared location, ahead of
defining a binding for capacity-dmips-mhz on RISC-V. Update some
references to this document in the process.
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Reviewed-by: default avatarLey Foon Tan <leyfoon.tan@starfivetech.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarYanteng Si <siyanteng@loongson.cn>
Link: https://lore.kernel.org/r/20230104180513.1379453-2-conor@kernel.orgSigned-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent c1d61058
...@@ -257,7 +257,7 @@ properties: ...@@ -257,7 +257,7 @@ properties:
capacity-dmips-mhz: capacity-dmips-mhz:
description: description:
u32 value representing CPU capacity (see ./cpu-capacity.txt) in u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
DMIPS/MHz, relative to highest capacity-dmips-mhz DMIPS/MHz, relative to highest capacity-dmips-mhz
in the system. in the system.
......
========================================== ==========================================
ARM CPUs capacity bindings CPU capacity bindings
========================================== ==========================================
========================================== ==========================================
1 - Introduction 1 - Introduction
========================================== ==========================================
ARM systems may be configured to have cpus with different power/performance Some systems may be configured to have cpus with different power/performance
characteristics within the same chip. In this case, additional information has characteristics within the same chip. In this case, additional information has
to be made available to the kernel for it to be aware of such differences and to be made available to the kernel for it to be aware of such differences and
take decisions accordingly. take decisions accordingly.
......
...@@ -260,7 +260,7 @@ for that purpose. ...@@ -260,7 +260,7 @@ for that purpose.
The arm and arm64 architectures directly map this to the arch_topology driver The arm and arm64 architectures directly map this to the arch_topology driver
CPU scaling data, which is derived from the capacity-dmips-mhz CPU binding; see CPU scaling data, which is derived from the capacity-dmips-mhz CPU binding; see
Documentation/devicetree/bindings/arm/cpu-capacity.txt. Documentation/devicetree/bindings/cpu/cpu-capacity.txt.
3.2 Frequency invariance 3.2 Frequency invariance
------------------------ ------------------------
......
...@@ -233,7 +233,7 @@ CFS调度类基于实体负载跟踪机制(Per-Entity Load Tracking, PELT) ...@@ -233,7 +233,7 @@ CFS调度类基于实体负载跟踪机制(Per-Entity Load Tracking, PELT)
arm和arm64架构直接把这个信息映射到arch_topology驱动的CPU scaling数据中(译注:参考 arm和arm64架构直接把这个信息映射到arch_topology驱动的CPU scaling数据中(译注:参考
arch_topology.h的percpu变量cpu_scale),它是从capacity-dmips-mhz CPU binding中衍生计算 arch_topology.h的percpu变量cpu_scale),它是从capacity-dmips-mhz CPU binding中衍生计算
出来的。参见Documentation/devicetree/bindings/arm/cpu-capacity.txt。 出来的。参见Documentation/devicetree/bindings/cpu/cpu-capacity.txt。
3.2 频率不变性 3.2 频率不变性
-------------- --------------
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment