Commit 7d6d45f8 authored by Kumar Gala's avatar Kumar Gala

clocksource: qcom: split building of legacy vs multiplatform support

The majority of the clocksource code for the Qualcomm platform is shared
between newer (multiplatform) and older platforms.  However there is a bit
of code that isn't, so only build it for the appropriate config.
Acked-by: default avatarOlof Johansson <olof@lixom.net>
Signed-off-by: default avatarKumar Gala <galak@codeaurora.org>
parent 8fc1b0f8
...@@ -106,15 +106,6 @@ static notrace cycle_t msm_read_timer_count(struct clocksource *cs) ...@@ -106,15 +106,6 @@ static notrace cycle_t msm_read_timer_count(struct clocksource *cs)
return readl_relaxed(source_base + TIMER_COUNT_VAL); return readl_relaxed(source_base + TIMER_COUNT_VAL);
} }
static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
{
/*
* Shift timer count down by a constant due to unreliable lower bits
* on some targets.
*/
return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
}
static struct clocksource msm_clocksource = { static struct clocksource msm_clocksource = {
.name = "dg_timer", .name = "dg_timer",
.rating = 300, .rating = 300,
...@@ -228,7 +219,7 @@ static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq, ...@@ -228,7 +219,7 @@ static void __init msm_timer_init(u32 dgt_hz, int sched_bits, int irq,
sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz); sched_clock_register(msm_sched_clock_read, sched_bits, dgt_hz);
} }
#ifdef CONFIG_OF #ifdef CONFIG_ARCH_QCOM
static void __init msm_dt_timer_init(struct device_node *np) static void __init msm_dt_timer_init(struct device_node *np)
{ {
u32 freq; u32 freq;
...@@ -281,7 +272,7 @@ static void __init msm_dt_timer_init(struct device_node *np) ...@@ -281,7 +272,7 @@ static void __init msm_dt_timer_init(struct device_node *np)
} }
CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init); CLOCKSOURCE_OF_DECLARE(kpss_timer, "qcom,kpss-timer", msm_dt_timer_init);
CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init); CLOCKSOURCE_OF_DECLARE(scss_timer, "qcom,scss-timer", msm_dt_timer_init);
#endif #else
static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source, static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
u32 sts) u32 sts)
...@@ -301,6 +292,15 @@ static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source, ...@@ -301,6 +292,15 @@ static int __init msm_timer_map(phys_addr_t addr, u32 event, u32 source,
return 0; return 0;
} }
static notrace cycle_t msm_read_timer_count_shift(struct clocksource *cs)
{
/*
* Shift timer count down by a constant due to unreliable lower bits
* on some targets.
*/
return msm_read_timer_count(cs) >> MSM_DGT_SHIFT;
}
void __init msm7x01_timer_init(void) void __init msm7x01_timer_init(void)
{ {
struct clocksource *cs = &msm_clocksource; struct clocksource *cs = &msm_clocksource;
...@@ -327,3 +327,4 @@ void __init qsd8x50_timer_init(void) ...@@ -327,3 +327,4 @@ void __init qsd8x50_timer_init(void)
return; return;
msm_timer_init(19200000 / 4, 32, 7, false); msm_timer_init(19200000 / 4, 32, 7, false);
} }
#endif
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