Commit 7e148070 authored by Nishanth Menon's avatar Nishanth Menon Committed by Tero Kristo

ARM: dts: OMAP5/DRA7: use omap5-mpu-dpll-clock capable of dealing with higher frequencies

OMAP5432, DRA75x and DRA72x have MPU DPLLs that need Duty Cycle
Correction(DCC) to operate safely at frequencies >= 1.4GHz.

Switch to "ti,omap5-mpu-dpll-clock" compatible property which provides
this support.
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Signed-off-by: default avatarTero Kristo <t-kristo@ti.com>
parent b4be0189
...@@ -277,7 +277,7 @@ mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { ...@@ -277,7 +277,7 @@ mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
dpll_mpu_ck: dpll_mpu_ck { dpll_mpu_ck: dpll_mpu_ck {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,omap4-dpll-clock"; compatible = "ti,omap5-mpu-dpll-clock";
clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>; clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
}; };
......
...@@ -362,7 +362,7 @@ mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div { ...@@ -362,7 +362,7 @@ mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
dpll_mpu_ck: dpll_mpu_ck { dpll_mpu_ck: dpll_mpu_ck {
#clock-cells = <0>; #clock-cells = <0>;
compatible = "ti,omap4-dpll-clock"; compatible = "ti,omap5-mpu-dpll-clock";
clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>; clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>; reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
}; };
......
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