Commit 7e6c2ffe authored by André Draszik's avatar André Draszik Committed by Vinod Koul

phy: exynos5-usbdrd: convert some FIELD_PREP_CONST() to FIELD_PREP()

Use of FIELD_PREP_CONST() was a thinko - it's meant to be used for
(constant) initialisers, not constant values.

Use FIELD_PREP() where possible. It has better error checking and is
therefore the preferred macro to use in those cases.
Signed-off-by: default avatarAndré Draszik <andre.draszik@linaro.org>
Reviewed-by: default avatarSam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240710-phy-field-prep-v1-1-2fa3f7dc4fc7@linaro.orgSigned-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 4bf8b462
...@@ -607,7 +607,7 @@ exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready(struct exynos5_usbdrd_phy *phy_drd) ...@@ -607,7 +607,7 @@ exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready(struct exynos5_usbdrd_phy *phy_drd)
reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL); reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL);
reg &= ~SECPMACTL_PMA_REF_FREQ_SEL; reg &= ~SECPMACTL_PMA_REF_FREQ_SEL;
reg |= FIELD_PREP_CONST(SECPMACTL_PMA_REF_FREQ_SEL, 1); reg |= FIELD_PREP(SECPMACTL_PMA_REF_FREQ_SEL, 1);
/* SFR reset */ /* SFR reset */
reg |= (SECPMACTL_PMA_LOW_PWR | SECPMACTL_PMA_APB_SW_RST); reg |= (SECPMACTL_PMA_LOW_PWR | SECPMACTL_PMA_APB_SW_RST);
reg &= ~(SECPMACTL_PMA_ROPLL_REF_CLK_SEL | reg &= ~(SECPMACTL_PMA_ROPLL_REF_CLK_SEL |
...@@ -1123,19 +1123,19 @@ static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) ...@@ -1123,19 +1123,19 @@ static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd)
reg &= ~SSPPLLCTL_FSEL; reg &= ~SSPPLLCTL_FSEL;
switch (phy_drd->extrefclk) { switch (phy_drd->extrefclk) {
case EXYNOS5_FSEL_50MHZ: case EXYNOS5_FSEL_50MHZ:
reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 7); reg |= FIELD_PREP(SSPPLLCTL_FSEL, 7);
break; break;
case EXYNOS5_FSEL_26MHZ: case EXYNOS5_FSEL_26MHZ:
reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 6); reg |= FIELD_PREP(SSPPLLCTL_FSEL, 6);
break; break;
case EXYNOS5_FSEL_24MHZ: case EXYNOS5_FSEL_24MHZ:
reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 2); reg |= FIELD_PREP(SSPPLLCTL_FSEL, 2);
break; break;
case EXYNOS5_FSEL_20MHZ: case EXYNOS5_FSEL_20MHZ:
reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 1); reg |= FIELD_PREP(SSPPLLCTL_FSEL, 1);
break; break;
case EXYNOS5_FSEL_19MHZ2: case EXYNOS5_FSEL_19MHZ2:
reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 0); reg |= FIELD_PREP(SSPPLLCTL_FSEL, 0);
break; break;
default: default:
dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n", dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n",
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment