Commit 7f18a70d authored by Ping-Ke Shih's avatar Ping-Ke Shih Committed by Kalle Valo

wifi: rtw89: 8852b: rfk: add TSSI

TSSI is transmitter signal strength indication, which is a close-loop
hardware circuit to feedback actual transmitting power as a reference for
next transmission.

When we setup channel to connect an AP, it does full calibration. When
switching bands or channels, it needs to reset hardware status to prevent
use wrong feedback of previous transmission.

To do TX power compensation reflecting current temperature, it loads tables
of compensation values into registers according to channel and band group.
Signed-off-by: default avatarPing-Ke Shih <pkshih@realtek.com>
Signed-off-by: default avatarKalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20221012083234.20224-6-pkshih@realtek.com
parent f2abe804
...@@ -3164,6 +3164,14 @@ struct rtw89_cfo_tracking_info { ...@@ -3164,6 +3164,14 @@ struct rtw89_cfo_tracking_info {
u8 lock_cnt; u8 lock_cnt;
}; };
enum rtw89_tssi_alimk_band {
TSSI_ALIMK_2G = 0,
TSSI_ALIMK_5GL,
TSSI_ALIMK_5GM,
TSSI_ALIMK_5GH,
TSSI_ALIMK_MAX
};
/* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */ /* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
#define TSSI_TRIM_CH_GROUP_NUM 8 #define TSSI_TRIM_CH_GROUP_NUM 8
#define TSSI_TRIM_CH_GROUP_NUM_6G 16 #define TSSI_TRIM_CH_GROUP_NUM_6G 16
...@@ -3174,6 +3182,8 @@ struct rtw89_cfo_tracking_info { ...@@ -3174,6 +3182,8 @@ struct rtw89_cfo_tracking_info {
#define TSSI_MCS_6G_CH_GROUP_NUM 32 #define TSSI_MCS_6G_CH_GROUP_NUM 32
#define TSSI_MCS_CH_GROUP_NUM \ #define TSSI_MCS_CH_GROUP_NUM \
(TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM) (TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
#define TSSI_MAX_CH_NUM 67
#define TSSI_ALIMK_VALUE_NUM 8
struct rtw89_tssi_info { struct rtw89_tssi_info {
u8 thermal[RF_PATH_MAX]; u8 thermal[RF_PATH_MAX];
...@@ -3186,6 +3196,11 @@ struct rtw89_tssi_info { ...@@ -3186,6 +3196,11 @@ struct rtw89_tssi_info {
bool tssi_tracking_check[RF_PATH_MAX]; bool tssi_tracking_check[RF_PATH_MAX];
u8 default_txagc_offset[RF_PATH_MAX]; u8 default_txagc_offset[RF_PATH_MAX];
u32 base_thermal[RF_PATH_MAX]; u32 base_thermal[RF_PATH_MAX];
bool check_backup_aligmk[RF_PATH_MAX][TSSI_MAX_CH_NUM];
u32 alignment_backup_by_ch[RF_PATH_MAX][TSSI_MAX_CH_NUM][TSSI_ALIMK_VALUE_NUM];
u32 alignment_value[RF_PATH_MAX][TSSI_ALIMK_MAX][TSSI_ALIMK_VALUE_NUM];
bool alignment_done[RF_PATH_MAX][TSSI_ALIMK_MAX];
u32 tssi_alimk_time;
}; };
struct rtw89_power_trim_info { struct rtw89_power_trim_info {
......
...@@ -3389,6 +3389,8 @@ ...@@ -3389,6 +3389,8 @@
#define RR_TXGA_TRK_EN BIT(7) #define RR_TXGA_TRK_EN BIT(7)
#define RR_TXGA_LOK_EXT GENMASK(4, 0) #define RR_TXGA_LOK_EXT GENMASK(4, 0)
#define RR_TXGA_LOK_EN BIT(0) #define RR_TXGA_LOK_EN BIT(0)
#define RR_TXGA_V1 0x10055
#define RR_TXGA_V1_TRK_EN BIT(7)
#define RR_GAINTX 0x56 #define RR_GAINTX 0x56
#define RR_GAINTX_ALL GENMASK(15, 0) #define RR_GAINTX_ALL GENMASK(15, 0)
#define RR_GAINTX_PAD GENMASK(9, 5) #define RR_GAINTX_PAD GENMASK(9, 5)
...@@ -3730,6 +3732,9 @@ ...@@ -3730,6 +3732,9 @@
#define B_TXAGC_TP GENMASK(2, 0) #define B_TXAGC_TP GENMASK(2, 0)
#define R_TSSI_THER 0x1C10 #define R_TSSI_THER 0x1C10
#define B_TSSI_THER GENMASK(29, 24) #define B_TSSI_THER GENMASK(29, 24)
#define R_TSSI_CWRPT 0x1C18
#define B_TSSI_CWRPT_RDY BIT(16)
#define B_TSSI_CWRPT GENMASK(8, 0)
#define R_TXAGC_BTP 0x1CA0 #define R_TXAGC_BTP 0x1CA0
#define B_TXAGC_BTP GENMASK(31, 24) #define B_TXAGC_BTP GENMASK(31, 24)
#define R_TXAGC_BB 0x1C60 #define R_TXAGC_BB 0x1C60
...@@ -4092,6 +4097,20 @@ ...@@ -4092,6 +4097,20 @@
#define B_CFO_COMP_VALID_BIT BIT(29) #define B_CFO_COMP_VALID_BIT BIT(29)
#define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24) #define B_CFO_COMP_WEIGHT_MSK GENMASK(27, 24)
#define B_CFO_COMP_VAL_MSK GENMASK(11, 0) #define B_CFO_COMP_VAL_MSK GENMASK(11, 0)
#define R_TSSI_PA_K1 0x5600
#define R_TSSI_PA_K2 0x5604
#define R_P0_TSSI_ALIM1 0x5630
#define B_P0_TSSI_ALIM1 GENMASK(29, 0)
#define B_P0_TSSI_ALIM11 GENMASK(29, 20)
#define B_P0_TSSI_ALIM12 GENMASK(19, 10)
#define B_P0_TSSI_ALIM13 GENMASK(9, 0)
#define R_P0_TSSI_ALIM3 0x5634
#define B_P0_TSSI_ALIM31 GENMASK(9, 0)
#define R_TSSI_PA_K5 0x5638
#define R_P0_TSSI_ALIM2 0x563c
#define B_P0_TSSI_ALIM2 GENMASK(29, 0)
#define R_P0_TSSI_ALIM4 0x5640
#define R_TSSI_PA_K8 0x5644
#define R_UPD_CLK 0x5670 #define R_UPD_CLK 0x5670
#define B_DAC_VAL BIT(31) #define B_DAC_VAL BIT(31)
#define B_ACK_VAL GENMASK(30, 29) #define B_ACK_VAL GENMASK(30, 29)
...@@ -4106,6 +4125,8 @@ ...@@ -4106,6 +4125,8 @@
#define B_DPD_TSSI_CW GENMASK(26, 18) #define B_DPD_TSSI_CW GENMASK(26, 18)
#define B_DPD_PWR_CW GENMASK(17, 9) #define B_DPD_PWR_CW GENMASK(17, 9)
#define B_DPD_REF GENMASK(8, 0) #define B_DPD_REF GENMASK(8, 0)
#define R_P0_TSSIC 0x5814
#define B_P0_TSSIC_BYPASS BIT(11)
#define R_DPD_OFT_ADDR 0x5804 #define R_DPD_OFT_ADDR 0x5804
#define B_DPD_OFT_ADDR GENMASK(31, 27) #define B_DPD_OFT_ADDR GENMASK(31, 27)
#define R_TXPWRB_H 0x580c #define R_TXPWRB_H 0x580c
...@@ -4114,11 +4135,15 @@ ...@@ -4114,11 +4135,15 @@
#define B_P0_TMETER GENMASK(15, 10) #define B_P0_TMETER GENMASK(15, 10)
#define B_P0_TMETER_DIS BIT(16) #define B_P0_TMETER_DIS BIT(16)
#define B_P0_TMETER_TRK BIT(24) #define B_P0_TMETER_TRK BIT(24)
#define R_P1_TSSIC 0x7814
#define B_P1_TSSIC_BYPASS BIT(11)
#define R_P0_TSSI_TRK 0x5818 #define R_P0_TSSI_TRK 0x5818
#define B_P0_TSSI_TRK_EN BIT(30) #define B_P0_TSSI_TRK_EN BIT(30)
#define B_P0_TSSI_RFC GENMASK(28, 27)
#define B_P0_TSSI_OFT_EN BIT(28) #define B_P0_TSSI_OFT_EN BIT(28)
#define B_P0_TSSI_OFT GENMASK(7, 0) #define B_P0_TSSI_OFT GENMASK(7, 0)
#define R_P0_TSSI_AVG 0x5820 #define R_P0_TSSI_AVG 0x5820
#define B_P0_TSSI_EN BIT(31)
#define B_P0_TSSI_AVG GENMASK(15, 12) #define B_P0_TSSI_AVG GENMASK(15, 12)
#define R_P0_RFCTM 0x5864 #define R_P0_RFCTM 0x5864
#define B_P0_RFCTM_EN BIT(29) #define B_P0_RFCTM_EN BIT(29)
...@@ -4141,7 +4166,9 @@ ...@@ -4141,7 +4166,9 @@
#define B_P0_TXPW_RSTB_MANON BIT(30) #define B_P0_TXPW_RSTB_MANON BIT(30)
#define B_P0_TXPW_RSTB_TSSI BIT(31) #define B_P0_TXPW_RSTB_TSSI BIT(31)
#define R_P0_TSSI_MV_AVG 0x58E4 #define R_P0_TSSI_MV_AVG 0x58E4
#define B_P0_TSSI_MV_MIX GENMASK(19, 11)
#define B_P0_TSSI_MV_AVG GENMASK(13, 11) #define B_P0_TSSI_MV_AVG GENMASK(13, 11)
#define B_P0_TSSI_MV_CLR BIT(14)
#define R_TXGAIN_SCALE 0x58F0 #define R_TXGAIN_SCALE 0x58F0
#define B_TXGAIN_SCALE_EN BIT(19) #define B_TXGAIN_SCALE_EN BIT(19)
#define B_TXGAIN_SCALE_OFT GENMASK(31, 24) #define B_TXGAIN_SCALE_OFT GENMASK(31, 24)
...@@ -4166,25 +4193,41 @@ ...@@ -4166,25 +4193,41 @@
#define B_S0_DACKQ8_K GENMASK(15, 8) #define B_S0_DACKQ8_K GENMASK(15, 8)
#define R_RPL_BIAS_COMP1 0x6DF0 #define R_RPL_BIAS_COMP1 0x6DF0
#define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0) #define B_RPL_BIAS_COMP1_MASK GENMASK(7, 0)
#define R_P1_TSSI_ALIM1 0x7630
#define B_P1_TSSI_ALIM1 GENMASK(29, 0)
#define B_P1_TSSI_ALIM11 GENMASK(29, 20)
#define B_P1_TSSI_ALIM12 GENMASK(19, 10)
#define B_P1_TSSI_ALIM13 GENMASK(9, 0)
#define R_P1_TSSI_ALIM3 0x7634
#define B_P1_TSSI_ALIM31 GENMASK(9, 0)
#define R_P1_TSSI_ALIM2 0x763c
#define B_P1_TSSI_ALIM2 GENMASK(29, 0)
#define R_P1_TSSIC 0x7814
#define B_P1_TSSIC_BYPASS BIT(11)
#define R_P1_TMETER 0x7810 #define R_P1_TMETER 0x7810
#define B_P1_TMETER GENMASK(15, 10) #define B_P1_TMETER GENMASK(15, 10)
#define B_P1_TMETER_DIS BIT(16) #define B_P1_TMETER_DIS BIT(16)
#define B_P1_TMETER_TRK BIT(24) #define B_P1_TMETER_TRK BIT(24)
#define R_P1_TSSI_TRK 0x7818 #define R_P1_TSSI_TRK 0x7818
#define B_P1_TSSI_TRK_EN BIT(30) #define B_P1_TSSI_TRK_EN BIT(30)
#define B_P1_TSSI_RFC GENMASK(28, 27)
#define B_P1_TSSI_OFT_EN BIT(28) #define B_P1_TSSI_OFT_EN BIT(28)
#define B_P1_TSSI_OFT GENMASK(7, 0) #define B_P1_TSSI_OFT GENMASK(7, 0)
#define R_P1_TSSI_AVG 0x7820 #define R_P1_TSSI_AVG 0x7820
#define B_P1_TSSI_EN BIT(31)
#define B_P1_TSSI_AVG GENMASK(15, 12) #define B_P1_TSSI_AVG GENMASK(15, 12)
#define R_P1_RFCTM 0x7864 #define R_P1_RFCTM 0x7864
#define R_P1_RFCTM_RDY BIT(26) #define R_P1_RFCTM_RDY BIT(26)
#define B_P1_RFCTM_VAL GENMASK(25, 20) #define B_P1_RFCTM_VAL GENMASK(25, 20)
#define B_P1_RFCTM_DEL GENMASK(19, 11)
#define R_P1_PATH_RST 0x78AC #define R_P1_PATH_RST 0x78AC
#define R_P1_TXPW_RSTB 0x78DC #define R_P1_TXPW_RSTB 0x78DC
#define B_P1_TXPW_RSTB_MANON BIT(30) #define B_P1_TXPW_RSTB_MANON BIT(30)
#define B_P1_TXPW_RSTB_TSSI BIT(31) #define B_P1_TXPW_RSTB_TSSI BIT(31)
#define R_P1_TSSI_MV_AVG 0x78E4 #define R_P1_TSSI_MV_AVG 0x78E4
#define B_P1_TSSI_MV_MIX GENMASK(19, 11)
#define B_P1_TSSI_MV_AVG GENMASK(13, 11) #define B_P1_TSSI_MV_AVG GENMASK(13, 11)
#define B_P1_TSSI_MV_CLR BIT(14)
#define R_TSSI_THOF 0x7C00 #define R_TSSI_THOF 0x7C00
#define R_S1_DACKI 0x7E00 #define R_S1_DACKI 0x7E00
#define B_S1_DACKI_AR GENMASK(31, 28) #define B_S1_DACKI_AR GENMASK(31, 28)
......
...@@ -11,6 +11,10 @@ void rtw8852b_rck(struct rtw89_dev *rtwdev); ...@@ -11,6 +11,10 @@ void rtw8852b_rck(struct rtw89_dev *rtwdev);
void rtw8852b_dack(struct rtw89_dev *rtwdev); void rtw8852b_dack(struct rtw89_dev *rtwdev);
void rtw8852b_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); void rtw8852b_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
void rtw8852b_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); void rtw8852b_rx_dck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx);
void rtw8852b_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, bool hwtx_en);
void rtw8852b_tssi_scan(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy);
void rtw8852b_wifi_scan_notify(struct rtw89_dev *rtwdev, bool scan_start,
enum rtw89_phy_idx phy_idx);
void rtw8852b_set_channel_rf(struct rtw89_dev *rtwdev, void rtw8852b_set_channel_rf(struct rtw89_dev *rtwdev,
const struct rtw89_chan *chan, const struct rtw89_chan *chan,
enum rtw89_phy_idx phy_idx); enum rtw89_phy_idx phy_idx);
......
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