Skip to content

L
linux
Commit 7fc698a0 authored by Tony Cheng's avatar Tony Cheng Committed by Alex Deucher
Browse files
Options

drm/amd/display: limit HBR3 support to Polaris and up 

- also fix YCbCr420 supported on Polaris and up
Signed-off-by: default avatarTony Cheng <tony.cheng@amd.com>
Reviewed-by: default avatarHersen Wu <hersenxs.wu@amd.com>
Reviewed-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 4dfb0bad
Hide whitespace changes
Inline Side-by-side
Showing with 46 additions and 34 deletions
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
View file @ 7fc698a0
...@@ -927,10 +927,14 @@ bool dce110_link_encoder_validate_dp_output( ...@@ -927,10 +927,14 @@ bool dce110_link_encoder_validate_dp_output(
bool dce110_link_encoder_construct( bool dce110_link_encoder_construct(
struct dce110_link_encoder *enc110, struct dce110_link_encoder *enc110,
const struct encoder_init_data *init_data, const struct encoder_init_data *init_data,
const struct encoder_feature_support *enc_features,
const struct dce110_link_enc_registers *link_regs, const struct dce110_link_enc_registers *link_regs,
const struct dce110_link_enc_aux_registers *aux_regs, const struct dce110_link_enc_aux_registers *aux_regs,
const struct dce110_link_enc_hpd_registers *hpd_regs) const struct dce110_link_enc_hpd_registers *hpd_regs)
{ {
struct bp_encoder_cap_info bp_cap_info = {0};
const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
enc110->base.funcs = &dce110_lnk_enc_funcs; enc110->base.funcs = &dce110_lnk_enc_funcs;
enc110->base.ctx = init_data->ctx; enc110->base.ctx = init_data->ctx;
enc110->base.id = init_data->encoder; enc110->base.id = init_data->encoder;
...@@ -941,12 +945,10 @@ bool dce110_link_encoder_construct( ...@@ -941,12 +945,10 @@ bool dce110_link_encoder_construct(
enc110->base.preferred_engine = ENGINE_ID_UNKNOWN; enc110->base.preferred_engine = ENGINE_ID_UNKNOWN;
enc110->base.features.flags.raw = 0; enc110->base.features = *enc_features;
enc110->base.transmitter = init_data->transmitter; enc110->base.transmitter = init_data->transmitter;
enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_121212;
if (enc110->base.ctx->dc->debug.disable_hdmi_deep_color) if (enc110->base.ctx->dc->debug.disable_hdmi_deep_color)
enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_888; enc110->base.features.max_hdmi_deep_color = COLOR_DEPTH_888;
...@@ -1013,10 +1015,6 @@ bool dce110_link_encoder_construct( ...@@ -1013,10 +1015,6 @@ bool dce110_link_encoder_construct(
init_data->channel); init_data->channel);
/* Override features with DCE-specific values */ /* Override features with DCE-specific values */
{
struct bp_encoder_cap_info bp_cap_info = {0};
const struct dc_vbios_funcs *bp_funcs = enc110->base.ctx->dc_bios->funcs;
if (BP_RESULT_OK == bp_funcs->get_encoder_cap_info( if (BP_RESULT_OK == bp_funcs->get_encoder_cap_info(
enc110->base.ctx->dc_bios, enc110->base.id, enc110->base.ctx->dc_bios, enc110->base.id,
&bp_cap_info)) &bp_cap_info))
...@@ -1024,26 +1022,7 @@ bool dce110_link_encoder_construct( ...@@ -1024,26 +1022,7 @@ bool dce110_link_encoder_construct(
bp_cap_info.DP_HBR2_CAP; bp_cap_info.DP_HBR2_CAP;
enc110->base.features.flags.bits.IS_HBR3_CAPABLE = enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
bp_cap_info.DP_HBR3_EN; bp_cap_info.DP_HBR3_EN;
}
/* TODO: check PPLIB maxPhyClockInKHz <= 540000, if yes,
* IS_HBR3_CAPABLE = 0.
*/
/* test pattern 3 support */
enc110->base.features.flags.bits.IS_TPS3_CAPABLE = true;
/* test pattern 4 support */
enc110->base.features.flags.bits.IS_TPS4_CAPABLE = true;
/*
dal_adapter_service_is_feature_supported(as,
FEATURE_SUPPORT_DP_Y_ONLY);
*/
enc110->base.features.flags.bits.IS_YCBCR_CAPABLE = true;
/*
dal_adapter_service_is_feature_supported(as,
FEATURE_SUPPORT_DP_YUV);
*/
return true; return true;
} }
......
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
View file @ 7fc698a0
...@@ -236,6 +236,7 @@ struct dce110_abm_backlight_registers { ...@@ -236,6 +236,7 @@ struct dce110_abm_backlight_registers {
bool dce110_link_encoder_construct( bool dce110_link_encoder_construct(
struct dce110_link_encoder *enc110, struct dce110_link_encoder *enc110,
const struct encoder_init_data *init_data, const struct encoder_init_data *init_data,
const struct encoder_feature_support *enc_features,
const struct dce110_link_enc_registers *link_regs, const struct dce110_link_enc_registers *link_regs,
const struct dce110_link_enc_aux_registers *aux_regs, const struct dce110_link_enc_aux_registers *aux_regs,
const struct dce110_link_enc_hpd_registers *hpd_regs); const struct dce110_link_enc_hpd_registers *hpd_regs);
......
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
View file @ 7fc698a0
...@@ -581,6 +581,14 @@ static struct input_pixel_processor *dce100_ipp_create( ...@@ -581,6 +581,14 @@ static struct input_pixel_processor *dce100_ipp_create(
return NULL; return NULL;
} }
static const struct encoder_feature_support link_enc_feature = {
.max_hdmi_deep_color = COLOR_DEPTH_121212,
.max_hdmi_pixel_clock = 300000,
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
.flags.bits.IS_YCBCR_CAPABLE = true
};
struct link_encoder *dce100_link_encoder_create( struct link_encoder *dce100_link_encoder_create(
const struct encoder_init_data *enc_init_data) const struct encoder_init_data *enc_init_data)
{ {
...@@ -593,12 +601,11 @@ struct link_encoder *dce100_link_encoder_create( ...@@ -593,12 +601,11 @@ struct link_encoder *dce100_link_encoder_create(
if (dce110_link_encoder_construct( if (dce110_link_encoder_construct(
enc110, enc110,
enc_init_data, enc_init_data,
&link_enc_feature,
&link_enc_regs[enc_init_data->transmitter], &link_enc_regs[enc_init_data->transmitter],
&link_enc_aux_regs[enc_init_data->channel - 1], &link_enc_aux_regs[enc_init_data->channel - 1],
&link_enc_hpd_regs[enc_init_data->hpd_source])) { &link_enc_hpd_regs[enc_init_data->hpd_source])) {
enc110->base.features.ycbcr420_supported = false;
enc110->base.features.max_hdmi_pixel_clock = 300000;
return &enc110->base; return &enc110->base;
} }
......
drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c
View file @ 7fc698a0
...@@ -570,6 +570,14 @@ static struct input_pixel_processor *dce110_ipp_create( ...@@ -570,6 +570,14 @@ static struct input_pixel_processor *dce110_ipp_create(
return NULL; return NULL;
} }
static const struct encoder_feature_support link_enc_feature = {
.max_hdmi_deep_color = COLOR_DEPTH_121212,
.max_hdmi_pixel_clock = 594000,
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
.flags.bits.IS_YCBCR_CAPABLE = true
};
struct link_encoder *dce110_link_encoder_create( struct link_encoder *dce110_link_encoder_create(
const struct encoder_init_data *enc_init_data) const struct encoder_init_data *enc_init_data)
{ {
...@@ -582,12 +590,11 @@ struct link_encoder *dce110_link_encoder_create( ...@@ -582,12 +590,11 @@ struct link_encoder *dce110_link_encoder_create(
if (dce110_link_encoder_construct( if (dce110_link_encoder_construct(
enc110, enc110,
enc_init_data, enc_init_data,
&link_enc_feature,
&link_enc_regs[enc_init_data->transmitter], &link_enc_regs[enc_init_data->transmitter],
&link_enc_aux_regs[enc_init_data->channel - 1], &link_enc_aux_regs[enc_init_data->channel - 1],
&link_enc_hpd_regs[enc_init_data->hpd_source])) { &link_enc_hpd_regs[enc_init_data->hpd_source])) {
enc110->base.features.ycbcr420_supported = false;
enc110->base.features.max_hdmi_pixel_clock = 594000;
return &enc110->base; return &enc110->base;
} }
......
drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c
View file @ 7fc698a0
...@@ -564,6 +564,18 @@ static struct transform *dce112_transform_create( ...@@ -564,6 +564,18 @@ static struct transform *dce112_transform_create(
dm_free(transform); dm_free(transform);
return NULL; return NULL;
} }
static const struct encoder_feature_support link_enc_feature = {
.max_hdmi_deep_color = COLOR_DEPTH_121212,
.max_hdmi_pixel_clock = 600000,
.ycbcr420_supported = true,
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_HBR3_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
.flags.bits.IS_TPS4_CAPABLE = true,
.flags.bits.IS_YCBCR_CAPABLE = true
};
struct link_encoder *dce112_link_encoder_create( struct link_encoder *dce112_link_encoder_create(
const struct encoder_init_data *enc_init_data) const struct encoder_init_data *enc_init_data)
{ {
...@@ -576,12 +588,11 @@ struct link_encoder *dce112_link_encoder_create( ...@@ -576,12 +588,11 @@ struct link_encoder *dce112_link_encoder_create(
if (dce110_link_encoder_construct( if (dce110_link_encoder_construct(
enc110, enc110,
enc_init_data, enc_init_data,
&link_enc_feature,
&link_enc_regs[enc_init_data->transmitter], &link_enc_regs[enc_init_data->transmitter],
&link_enc_aux_regs[enc_init_data->channel - 1], &link_enc_aux_regs[enc_init_data->channel - 1],
&link_enc_hpd_regs[enc_init_data->hpd_source])) { &link_enc_hpd_regs[enc_init_data->hpd_source])) {
enc110->base.features.ycbcr420_supported = false;
enc110->base.features.max_hdmi_pixel_clock = 600000;
return &enc110->base; return &enc110->base;
} }
......
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
View file @ 7fc698a0
...@@ -611,6 +611,14 @@ static struct input_pixel_processor *dce80_ipp_create( ...@@ -611,6 +611,14 @@ static struct input_pixel_processor *dce80_ipp_create(
return NULL; return NULL;
} }
static const struct encoder_feature_support link_enc_feature = {
.max_hdmi_deep_color = COLOR_DEPTH_121212,
.max_hdmi_pixel_clock = 297000,
.flags.bits.IS_HBR2_CAPABLE = true,
.flags.bits.IS_TPS3_CAPABLE = true,
.flags.bits.IS_YCBCR_CAPABLE = true
};
struct link_encoder *dce80_link_encoder_create( struct link_encoder *dce80_link_encoder_create(
const struct encoder_init_data *enc_init_data) const struct encoder_init_data *enc_init_data)
{ {
...@@ -623,12 +631,11 @@ struct link_encoder *dce80_link_encoder_create( ...@@ -623,12 +631,11 @@ struct link_encoder *dce80_link_encoder_create(
if (dce110_link_encoder_construct( if (dce110_link_encoder_construct(
enc110, enc110,
enc_init_data, enc_init_data,
&link_enc_feature,
&link_enc_regs[enc_init_data->transmitter], &link_enc_regs[enc_init_data->transmitter],
&link_enc_aux_regs[enc_init_data->channel - 1], &link_enc_aux_regs[enc_init_data->channel - 1],
&link_enc_hpd_regs[enc_init_data->hpd_source])) { &link_enc_hpd_regs[enc_init_data->hpd_source])) {
enc110->base.features.ycbcr420_supported = false;
enc110->base.features.max_hdmi_pixel_clock = 297000;
return &enc110->base; return &enc110->base;
} }
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7