Commit 8026f2d8 authored by Frank Li's avatar Frank Li Committed by Krzysztof Wilczyński

PCI: imx6: Call common PHY API to set mode, speed, and submode

Invoke the common PHY API to configure mode, speed, and submode. While
these functions are optional in the PHY interface, they are necessary for
certain PHY drivers. Lack of support for these functions in a PHY driver
does not cause harm.

Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-10-b68ee5ef2b4d@nxp.comSigned-off-by: default avatarFrank Li <Frank.Li@nxp.com>
Signed-off-by: default avatarKrzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
parent 4f1e478f
...@@ -28,6 +28,7 @@ ...@@ -28,6 +28,7 @@
#include <linux/types.h> #include <linux/types.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/reset.h> #include <linux/reset.h>
#include <linux/phy/pcie.h>
#include <linux/phy/phy.h> #include <linux/phy/phy.h>
#include <linux/pm_domain.h> #include <linux/pm_domain.h>
#include <linux/pm_runtime.h> #include <linux/pm_runtime.h>
...@@ -226,6 +227,10 @@ static void imx_pcie_configure_type(struct imx_pcie *imx_pcie) ...@@ -226,6 +227,10 @@ static void imx_pcie_configure_type(struct imx_pcie *imx_pcie)
id = imx_pcie->controller_id; id = imx_pcie->controller_id;
/* If mode_mask is 0, then generic PHY driver is used to set the mode */
if (!drvdata->mode_mask[0])
return;
/* If mode_mask[id] is zero, means each controller have its individual gpr */ /* If mode_mask[id] is zero, means each controller have its individual gpr */
if (!drvdata->mode_mask[id]) if (!drvdata->mode_mask[id])
id = 0; id = 0;
...@@ -801,7 +806,11 @@ static void imx_pcie_ltssm_enable(struct device *dev) ...@@ -801,7 +806,11 @@ static void imx_pcie_ltssm_enable(struct device *dev)
{ {
struct imx_pcie *imx_pcie = dev_get_drvdata(dev); struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
u8 offset = dw_pcie_find_capability(imx_pcie->pci, PCI_CAP_ID_EXP);
u32 tmp;
tmp = dw_pcie_readl_dbi(imx_pcie->pci, offset + PCI_EXP_LNKCAP);
phy_set_speed(imx_pcie->phy, FIELD_GET(PCI_EXP_LNKCAP_SLS, tmp));
if (drvdata->ltssm_mask) if (drvdata->ltssm_mask)
regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask,
drvdata->ltssm_mask); drvdata->ltssm_mask);
...@@ -814,6 +823,7 @@ static void imx_pcie_ltssm_disable(struct device *dev) ...@@ -814,6 +823,7 @@ static void imx_pcie_ltssm_disable(struct device *dev)
struct imx_pcie *imx_pcie = dev_get_drvdata(dev); struct imx_pcie *imx_pcie = dev_get_drvdata(dev);
const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata;
phy_set_speed(imx_pcie->phy, 0);
if (drvdata->ltssm_mask) if (drvdata->ltssm_mask)
regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off,
drvdata->ltssm_mask, 0); drvdata->ltssm_mask, 0);
...@@ -949,6 +959,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) ...@@ -949,6 +959,12 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp)
goto err_clk_disable; goto err_clk_disable;
} }
ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
if (ret) {
dev_err(dev, "unable to set PCIe PHY mode\n");
goto err_phy_exit;
}
ret = phy_power_on(imx_pcie->phy); ret = phy_power_on(imx_pcie->phy);
if (ret) { if (ret) {
dev_err(dev, "waiting for PHY ready timeout!\n"); dev_err(dev, "waiting for PHY ready timeout!\n");
......
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