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Commit 80706f55 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'soc-fixes-6.5-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull ARM SoC fixes from Arnd Bergmann:
 "As usual, mostly DT fixes for the major Arm platforms from Qualcomm
  and NXP, plus a bit for Rockchips and others:

  The qualcomm fixes mainly deal with their higher-end arm64 devices
  trees, fixing issues in L3 interconnect, crypto, thermal, UFS and a
  regression for the DSI phy.

  NXP i.MX has two correctness fixes for the 64-bit chips, dealing with
  the imx93 "anatop" module and the CSI interface. On the 32-bit side,
  there are functional fixes for RTC, display and SD card intefaces.

  Rockchip fixes are for wifi support on certain boards, a eMMC
  stability and DT build warnings.

  On TI OMAP, a regulator is described in DT to avoid problems with the
  ethernet phy initialization.

  The code changes include a missing MMIO serialization on OMAP, plus a
  few minor fixes on ASpeed and AMD/Zynq chips"

* tag 'soc-fixes-6.5-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (30 commits)
  ARM: dts: am335x-bone-common: Add vcc-supply for on-board eeprom
  ARM: dts: am335x-bone-common: Add GPIO PHY reset on revision C3 board
  soc: aspeed: socinfo: Add kfree for kstrdup
  soc: aspeed: uart-routing: Use __sysfs_match_string
  ARM: dts: integrator: fix PCI bus dtc warnings
  arm64: dts: imx93: Fix anatop node size
  arm64: dts: qcom: sc7180: Fix DSI0_PHY reg-names
  ARM: dts: imx: Set default tuning step for imx6sx usdhc
  arm64: dts: imx8mm: Drop CSI1 PHY reference clock configuration
  arm64: dts: imx8mn: Drop CSI1 PHY reference clock configuration
  ARM: dts: imx: Set default tuning step for imx7d usdhc
  ARM: dts: imx6: phytec: fix RTC interrupt level
  ARM: dts: imx6sx: Remove LDB endpoint
  arm64: dts: rockchip: Fix Wifi/Bluetooth on ROCK Pi 4 boards
  ARM: zynq: Explicitly include correct DT includes
  arm64: dts: qcom: sa8775p-ride: Update L4C parameters
  arm64: dts: rockchip: minor whitespace cleanup around '='
  arm64: dts: rockchip: Disable HS400 for eMMC on ROCK 4C+
  arm64: dts: rockchip: Disable HS400 for eMMC on ROCK Pi 4
  arm64: dts: rockchip: add missing space before { on indiedroid nova
  ...
parents eabeef90 3c78dbf2
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Showing with 86 additions and 112 deletions
arch/arm/boot/dts/arm/integratorap.dts
View file @ 80706f55
......@@ -158,7 +158,7 @@ pic: pic@14000000 {
valid-mask = <0x003fffff>;
};
pci: pciv3@62000000 {
pci: pci@62000000 {
compatible = "arm,integrator-ap-pci", "v3,v360epc-pci";
device_type = "pci";
#interrupt-cells = <1>;
......
arch/arm/boot/dts/nxp/imx/imx6qdl-phytec-mira.dtsi
View file @ 80706f55
......@@ -182,7 +182,7 @@ i2c_rtc: rtc@68 {
pinctrl-0 = <&pinctrl_rtc_int>;
reg = <0x68>;
interrupt-parent = <&gpio7>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
status = "disabled";
};
};
......
arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
View file @ 80706f55
......@@ -863,7 +863,6 @@ port@0 {
reg = <0>;
ldb_from_lcdif1: endpoint {
remote-endpoint = <&lcdif1_to_ldb>;
};
};
......@@ -1010,6 +1009,8 @@ usdhc1: mmc@2190000 {
<&clks IMX6SX_CLK_USDHC1>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled";
};
......@@ -1022,6 +1023,8 @@ usdhc2: mmc@2194000 {
<&clks IMX6SX_CLK_USDHC2>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled";
};
......@@ -1034,6 +1037,8 @@ usdhc3: mmc@2198000 {
<&clks IMX6SX_CLK_USDHC3>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-start-tap = <20>;
fsl,tuning-step= <2>;
status = "disabled";
};
......@@ -1309,11 +1314,8 @@ lcdif1: lcdif@2220000 {
power-domains = <&pd_disp>;
status = "disabled";
ports {
port {
lcdif1_to_ldb: endpoint {
remote-endpoint = <&ldb_from_lcdif1>;
};
port {
lcdif1_to_ldb: endpoint {
};
};
};
......
arch/arm/boot/dts/nxp/imx/imx7s.dtsi
View file @ 80706f55
......@@ -1184,6 +1184,8 @@ usdhc1: mmc@30b40000 {
<&clks IMX7D_USDHC1_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-step = <2>;
fsl,tuning-start-tap = <20>;
status = "disabled";
};
......@@ -1196,6 +1198,8 @@ usdhc2: mmc@30b50000 {
<&clks IMX7D_USDHC2_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-step = <2>;
fsl,tuning-start-tap = <20>;
status = "disabled";
};
......@@ -1208,6 +1212,8 @@ usdhc3: mmc@30b60000 {
<&clks IMX7D_USDHC3_ROOT_CLK>;
clock-names = "ipg", "ahb", "per";
bus-width = <4>;
fsl,tuning-step = <2>;
fsl,tuning-start-tap = <20>;
status = "disabled";
};
......
arch/arm/boot/dts/ti/omap/am335x-bone-common.dtsi
View file @ 80706f55
......@@ -145,6 +145,8 @@ davinci_mdio_default: davinci-mdio-default-pins {
/* MDIO */
AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
/* Added to support GPIO controlled PHY reset */
AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE7)
>;
};
......@@ -153,6 +155,8 @@ davinci_mdio_sleep: davinci-mdio-sleep-pins {
/* MDIO reset value */
AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)
AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)
/* Added to support GPIO controlled PHY reset */
AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE7)
>;
};
......@@ -215,6 +219,7 @@ tps: tps@24 {
baseboard_eeprom: baseboard_eeprom@50 {
compatible = "atmel,24c256";
reg = <0x50>;
vcc-supply = <&ldo4_reg>;
#address-cells = <1>;
#size-cells = <1>;
......@@ -377,6 +382,10 @@ &davinci_mdio_sw {
ethphy0: ethernet-phy@0 {
reg = <0>;
/* Support GPIO reset on revision C3 boards */
reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
reset-assert-us = <300>;
reset-deassert-us = <6500>;
};
};
......
arch/arm/mach-zynq/pm.c
View file @ 80706f55
......@@ -8,8 +8,8 @@
*/
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include "common.h"
/* register offsets */
......
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View file @ 80706f55
......@@ -1221,10 +1221,9 @@ mipi_csi: mipi-csi@32e30000 {
compatible = "fsl,imx8mm-mipi-csi2";
reg = <0x32e30000 0x1000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
<&clk IMX8MM_CLK_CSI1_PHY_REF>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
<&clk IMX8MM_SYS_PLL2_1000M>;
assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>;
clock-frequency = <333000000>;
clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
<&clk IMX8MM_CLK_CSI1_ROOT>,
......
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View file @ 80706f55
......@@ -1175,10 +1175,8 @@ mipi_csi: mipi-csi@32e30000 {
compatible = "fsl,imx8mm-mipi-csi2";
reg = <0x32e30000 0x1000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>,
<&clk IMX8MN_CLK_CSI1_PHY_REF>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>,
<&clk IMX8MN_SYS_PLL2_1000M>;
assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>;
assigned-clock-rates = <333000000>;
clock-frequency = <333000000>;
clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>,
......
arch/arm64/boot/dts/freescale/imx93.dtsi
View file @ 80706f55
......@@ -340,7 +340,7 @@ mediamix: power-domain@44462400 {
anatop: anatop@44480000 {
compatible = "fsl,imx93-anatop", "syscon";
reg = <0x44480000 0x10000>;
reg = <0x44480000 0x2000>;
};
adc1: adc@44530000 {
......
arch/arm64/boot/dts/qcom/qrb5165-rb5.dts
View file @ 80706f55
......@@ -121,7 +121,7 @@ active-config0 {
};
};
pm8150l-thermal {
pm8150l-pcb-thermal {
polling-delay-passive = <0>;
polling-delay = <0>;
thermal-sensors = <&pm8150l_adc_tm 1>;
......
arch/arm64/boot/dts/qcom/sa8775p-ride.dts
View file @ 80706f55
......@@ -153,8 +153,8 @@ vreg_l3c: ldo3 {
vreg_l4c: ldo4 {
regulator-name = "vreg_l4c";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1300000>;
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
/*
* FIXME: This should have regulator-allow-set-load but
......
arch/arm64/boot/dts/qcom/sc7180.dtsi
View file @ 80706f55
......@@ -3120,8 +3120,8 @@ mdss_dsi0_phy: phy@ae94400 {
reg = <0 0x0ae94400 0 0x200>,
<0 0x0ae94600 0 0x280>,
<0 0x0ae94a00 0 0x1e0>;
reg-names = "dsi0_phy",
"dsi0_phy_lane",
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
......
arch/arm64/boot/dts/qcom/sc8180x.dtsi
View file @ 80706f55
......@@ -3561,7 +3561,7 @@ rpmhpd_opp_turbo_l1: opp10 {
};
osm_l3: interconnect@18321000 {
compatible = "qcom,sc8180x-osm-l3";
compatible = "qcom,sc8180x-osm-l3", "qcom,osm-l3";
reg = <0 0x18321000 0 0x1400>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
......
arch/arm64/boot/dts/qcom/sm8150.dtsi
View file @ 80706f55
......@@ -56,7 +56,7 @@ CPU0: cpu@0 {
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
#cooling-cells = <2>;
......@@ -85,7 +85,7 @@ CPU1: cpu@100 {
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
#cooling-cells = <2>;
......@@ -109,7 +109,7 @@ CPU2: cpu@200 {
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
#cooling-cells = <2>;
......@@ -133,7 +133,7 @@ CPU3: cpu@300 {
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
#cooling-cells = <2>;
......@@ -157,7 +157,7 @@ CPU4: cpu@400 {
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD4>;
power-domain-names = "psci";
#cooling-cells = <2>;
......@@ -181,7 +181,7 @@ CPU5: cpu@500 {
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD5>;
power-domain-names = "psci";
#cooling-cells = <2>;
......@@ -205,7 +205,7 @@ CPU6: cpu@600 {
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD6>;
power-domain-names = "psci";
#cooling-cells = <2>;
......@@ -229,7 +229,7 @@ CPU7: cpu@700 {
qcom,freq-domain = <&cpufreq_hw 2>;
operating-points-v2 = <&cpu7_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&osm_l3 MASTER_OSM_L3_APPS 0 &osm_l3 SLAVE_OSM_L3 0>;
<&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
power-domains = <&CPU_PD7>;
power-domain-names = "psci";
#cooling-cells = <2>;
......@@ -4342,7 +4342,7 @@ osm_l3: interconnect@18321000 {
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
#interconnect-cells = <2>;
#interconnect-cells = <1>;
};
cpufreq_hw: cpufreq@18323000 {
......
arch/arm64/boot/dts/qcom/sm8250.dtsi
View file @ 80706f55
......@@ -107,7 +107,7 @@ CPU0: cpu@0 {
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
......@@ -138,7 +138,7 @@ CPU1: cpu@100 {
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
......@@ -163,7 +163,7 @@ CPU2: cpu@200 {
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
......@@ -188,7 +188,7 @@ CPU3: cpu@300 {
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
......@@ -213,7 +213,7 @@ CPU4: cpu@400 {
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
......@@ -238,7 +238,7 @@ CPU5: cpu@500 {
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
......@@ -263,7 +263,7 @@ CPU6: cpu@600 {
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
......@@ -288,7 +288,7 @@ CPU7: cpu@700 {
qcom,freq-domain = <&cpufreq_hw 2>;
operating-points-v2 = <&cpu7_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 0 &mc_virt SLAVE_EBI_CH0 0>,
<&epss_l3 MASTER_OSM_L3_APPS 0 &epss_l3 SLAVE_OSM_L3 0>;
<&epss_l3 MASTER_OSM_L3_APPS &epss_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
......@@ -5679,7 +5679,7 @@ epss_l3: interconnect@18590000 {
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
#interconnect-cells = <2>;
#interconnect-cells = <1>;
};
cpufreq_hw: cpufreq@18591000 {
......
arch/arm64/boot/dts/qcom/sm8350.dtsi
View file @ 80706f55
......@@ -1744,6 +1744,8 @@ cryptobam: dma-controller@1dc4000 {
qcom,controlled-remotely;
iommus = <&apps_smmu 0x594 0x0011>,
<&apps_smmu 0x596 0x0011>;
/* FIXME: Probing BAM DMA causes some abort and system hang */
status = "fail";
};
crypto: crypto@1dfa000 {
......@@ -1755,6 +1757,8 @@ crypto: crypto@1dfa000 {
<&apps_smmu 0x596 0x0011>;
interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "memory";
/* FIXME: dependency BAM DMA is disabled */
status = "disabled";
};
ipa: ipa@1e40000 {
......
arch/arm64/boot/dts/rockchip/px30.dtsi
View file @ 80706f55
......@@ -291,14 +291,14 @@ power-domain@PX30_PD_GMAC {
};
power-domain@PX30_PD_MMC_NAND {
reg = <PX30_PD_MMC_NAND>;
clocks = <&cru HCLK_NANDC>,
<&cru HCLK_EMMC>,
<&cru HCLK_SDIO>,
<&cru HCLK_SFC>,
<&cru SCLK_EMMC>,
<&cru SCLK_NANDC>,
<&cru SCLK_SDIO>,
<&cru SCLK_SFC>;
clocks = <&cru HCLK_NANDC>,
<&cru HCLK_EMMC>,
<&cru HCLK_SDIO>,
<&cru HCLK_SFC>,
<&cru SCLK_EMMC>,
<&cru SCLK_NANDC>,
<&cru SCLK_SDIO>,
<&cru SCLK_SFC>;
pm_qos = <&qos_emmc>, <&qos_nand>,
<&qos_sdio>, <&qos_sfc>;
#power-domain-cells = <0>;
......
arch/arm64/boot/dts/rockchip/rk3308-roc-cc.dts
View file @ 80706f55
......@@ -106,7 +106,6 @@ vdd_core: vdd-core {
regulator-name = "vdd_core";
regulator-min-microvolt = <827000>;
regulator-max-microvolt = <1340000>;
regulator-init-microvolt = <1015000>;
regulator-settling-time-up-us = <250>;
regulator-always-on;
regulator-boot-on;
......
arch/arm64/boot/dts/rockchip/rk3308-rock-pi-s.dts
View file @ 80706f55
......@@ -105,7 +105,6 @@ vdd_core: vdd-core {
regulator-name = "vdd_core";
regulator-min-microvolt = <827000>;
regulator-max-microvolt = <1340000>;
regulator-init-microvolt = <1015000>;
regulator-settling-time-up-us = <250>;
regulator-always-on;
regulator-boot-on;
......
arch/arm64/boot/dts/rockchip/rk3399-eaidk-610.dts
View file @ 80706f55
......@@ -773,7 +773,7 @@ brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
......
arch/arm64/boot/dts/rockchip/rk3399-nanopi4.dtsi
View file @ 80706f55
......@@ -375,7 +375,6 @@ regulator-state-mem {
vcc_sdio: LDO_REG4 {
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <3000000>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-name = "vcc_sdio";
......
arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
View file @ 80706f55
......@@ -548,9 +548,8 @@ &saradc {
&sdhci {
max-frequency = <150000000>;
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs200-1_8v;
non-removable;
mmc-hs400-enhanced-strobe;
status = "okay";
};
......
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
View file @ 80706f55
......@@ -45,7 +45,7 @@ led-0 {
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&rk808 1>;
clock-names = "ext_clock";
clock-names = "lpo";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h>;
reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
......@@ -645,9 +645,9 @@ &saradc {
};
&sdhci {
max-frequency = <150000000>;
bus-width = <8>;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
mmc-hs200-1_8v;
non-removable;
status = "okay";
};
......
arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dts
View file @ 80706f55
......@@ -31,7 +31,7 @@ brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio0>;
interrupts = <RK_PA3 GPIO_ACTIVE_HIGH>;
interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_l>;
......
arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi
View file @ 80706f55
......@@ -356,7 +356,6 @@ vdd_logic: DCDC_REG1 {
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_logic";
......@@ -371,7 +370,6 @@ vdd_gpu: DCDC_REG2 {
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_gpu";
......@@ -533,7 +531,6 @@ vdd_cpu: regulator@40 {
regulator-boot-on;
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1390000>;
regulator-init-microvolt = <900000>;
regulator-name = "vdd_cpu";
regulator-ramp-delay = <2300>;
vin-supply = <&vcc_sys>;
......
arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
View file @ 80706f55
......@@ -239,7 +239,7 @@ &cpu3 {
&gmac1 {
assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
phy-mode = "rgmii";
clock_in_out = "input";
pinctrl-names = "default";
......@@ -416,7 +416,7 @@ brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio2>;
interrupts = <RK_PB2 GPIO_ACTIVE_HIGH>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_h>;
......
arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts
View file @ 80706f55
......@@ -218,7 +218,6 @@ vdd_logic: DCDC_REG1 {
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
......@@ -233,7 +232,6 @@ vdd_gpu: DCDC_REG2 {
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
......@@ -259,7 +257,6 @@ vdd_npu: DCDC_REG4 {
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
......
arch/arm64/boot/dts/rockchip/rk3566-pinenote.dtsi
View file @ 80706f55
......@@ -264,7 +264,6 @@ vdd_logic: DCDC_REG1 {
regulator-always-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
......@@ -278,7 +277,6 @@ vdd_gpu_npu: DCDC_REG2 {
regulator-name = "vdd_gpu_npu";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
......
arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
View file @ 80706f55
......@@ -366,7 +366,6 @@ vdd_logic: DCDC_REG1 {
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_logic";
......@@ -381,7 +380,6 @@ vdd_gpu: DCDC_REG2 {
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_gpu";
......
arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
View file @ 80706f55
......@@ -277,7 +277,6 @@ vdd_log: DCDC_REG1 {
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
......@@ -292,7 +291,6 @@ vdd_gpu: DCDC_REG2 {
regulator-boot-on;
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
......
arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
View file @ 80706f55
......@@ -137,8 +137,8 @@ &hdmi_sound {
&mdio1 {
rgmii_phy1: ethernet-phy@0 {
compatible="ethernet-phy-ieee802.3-c22";
reg= <0x0>;
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x0>;
};
};
......
arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
View file @ 80706f55
......@@ -278,7 +278,6 @@ vdd_log: DCDC_REG1 {
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
......@@ -291,7 +290,6 @@ vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-state-mem {
......
arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
View file @ 80706f55
......@@ -234,7 +234,6 @@ vdd_logic: DCDC_REG1 {
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-state-mem {
......@@ -249,7 +248,6 @@ vdd_gpu: DCDC_REG2 {
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
regulator-state-mem {
......@@ -272,7 +270,6 @@ vdd_npu: DCDC_REG4 {
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-name = "vdd_npu";
regulator-state-mem {
......
arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
View file @ 80706f55
......@@ -308,7 +308,6 @@ vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......@@ -322,7 +321,6 @@ regulator-state-mem {
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......@@ -346,7 +344,6 @@ regulator-state-mem {
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......
arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
View file @ 80706f55
......@@ -293,7 +293,6 @@ vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......@@ -307,7 +306,6 @@ regulator-state-mem {
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......@@ -331,7 +329,6 @@ regulator-state-mem {
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......
arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
View file @ 80706f55
......@@ -173,7 +173,6 @@ vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......@@ -187,7 +186,6 @@ regulator-state-mem {
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......@@ -211,7 +209,6 @@ regulator-state-mem {
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......@@ -330,7 +327,6 @@ regulator-state-mem {
vcca1v8_image: LDO_REG9 {
regulator-name = "vcca1v8_image";
regulator-init-microvolt = <950000>;
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1800000>;
......
arch/arm64/boot/dts/rockchip/rk3568-lubancat-2.dts
View file @ 80706f55
......@@ -243,7 +243,6 @@ vdd_logic: DCDC_REG1 {
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
......@@ -258,7 +257,6 @@ vdd_gpu: DCDC_REG2 {
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
......@@ -284,7 +282,6 @@ vdd_npu: DCDC_REG4 {
regulator-boot-on;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-init-microvolt = <900000>;
regulator-ramp-delay = <6001>;
regulator-initial-mode = <0x2>;
......
arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
View file @ 80706f55
......@@ -232,7 +232,6 @@ vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......@@ -246,7 +245,6 @@ regulator-state-mem {
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......@@ -270,7 +268,6 @@ regulator-state-mem {
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......
arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
View file @ 80706f55
......@@ -291,7 +291,6 @@ vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......@@ -305,7 +304,6 @@ regulator-state-mem {
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......@@ -329,7 +327,6 @@ regulator-state-mem {
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......
arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
View file @ 80706f55
......@@ -163,7 +163,6 @@ vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......@@ -177,7 +176,6 @@ regulator-state-mem {
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......@@ -201,7 +199,6 @@ regulator-state-mem {
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......
arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
View file @ 80706f55
......@@ -350,7 +350,6 @@ vdd_logic: DCDC_REG1 {
regulator-name = "vdd_logic";
regulator-always-on;
regulator-boot-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......@@ -364,7 +363,6 @@ regulator-state-mem {
vdd_gpu: DCDC_REG2 {
regulator-name = "vdd_gpu";
regulator-always-on;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......@@ -388,7 +386,6 @@ regulator-state-mem {
vdd_npu: DCDC_REG4 {
regulator-name = "vdd_npu";
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x2>;
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
......
arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
View file @ 80706f55
......@@ -337,7 +337,6 @@ vdd_vdenc_s0: vdd_vdenc_mem_s0: dcdc-reg4 {
regulator-boot-on;
regulator-min-microvolt = <550000>;
regulator-max-microvolt = <950000>;
regulator-init-microvolt = <750000>;
regulator-ramp-delay = <12500>;
regulator-name = "vdd_vdenc_s0";
......
arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts
View file @ 80706f55
......@@ -125,19 +125,19 @@ &cpu_l3 {
cpu-supply = <&vdd_cpu_lit_s0>;
};
&cpu_b0{
&cpu_b0 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
&cpu_b1{
&cpu_b1 {
cpu-supply = <&vdd_cpu_big0_s0>;
};
&cpu_b2{
&cpu_b2 {
cpu-supply = <&vdd_cpu_big1_s0>;
};
&cpu_b3{
&cpu_b3 {
cpu-supply = <&vdd_cpu_big1_s0>;
};
......
drivers/bus/ti-sysc.c
View file @ 80706f55
......@@ -2142,6 +2142,8 @@ static int sysc_reset(struct sysc *ddata)
sysc_val = sysc_read_sysconfig(ddata);
sysc_val |= sysc_mask;
sysc_write(ddata, sysc_offset, sysc_val);
/* Flush posted write */
sysc_val = sysc_read_sysconfig(ddata);
}
if (ddata->cfg.srst_udelay)
......
drivers/soc/aspeed/aspeed-socinfo.c
View file @ 80706f55
......@@ -137,6 +137,7 @@ static int __init aspeed_socinfo_init(void)
soc_dev = soc_device_register(attrs);
if (IS_ERR(soc_dev)) {
kfree(attrs->machine);
kfree(attrs->soc_id);
kfree(attrs->serial_number);
kfree(attrs);
......
drivers/soc/aspeed/aspeed-uart-routing.c
View file @ 80706f55
......@@ -524,7 +524,7 @@ static ssize_t aspeed_uart_routing_store(struct device *dev,
struct aspeed_uart_routing_selector *sel = to_routing_selector(attr);
int val;
val = match_string(sel->options, -1, buf);
val = __sysfs_match_string(sel->options, -1, buf);
if (val < 0) {
dev_err(dev, "invalid value \"%s\"\n", buf);
return -EINVAL;
......
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