Commit 80fbe30f authored by Linus Walleij's avatar Linus Walleij

ARM: ux500: switch SSP/SPI clock name to "SSPCLK"

As noted in recent discussions the name of the core clock for
the PL022 derived SPI blocks is erroneously named in the
Ux500 device trees. The kernel doesn't currently use the name,
but may do so soon so let use rename all these clocks in
accordance with the name given in the PL022 TRM (ARM DDI 0194G).
Reviewed-by: default avatarMark Brown <broonie@linaro.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 77ad9dfc
...@@ -705,7 +705,7 @@ ssp@80002000 { ...@@ -705,7 +705,7 @@ ssp@80002000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>; clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
clock-names = "ssp0clk", "apb_pclk"; clock-names = "SSPCLK", "apb_pclk";
dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */ dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
<&dma 8 0 0x0>; /* Logical - MemToDev */ <&dma 8 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx"; dma-names = "rx", "tx";
...@@ -718,7 +718,7 @@ ssp@80003000 { ...@@ -718,7 +718,7 @@ ssp@80003000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>; clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
clock-names = "ssp1clk", "apb_pclk"; clock-names = "SSPCLK", "apb_pclk";
dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */ dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
<&dma 9 0 0x0>; /* Logical - MemToDev */ <&dma 9 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx"; dma-names = "rx", "tx";
...@@ -732,7 +732,7 @@ spi@8011a000 { ...@@ -732,7 +732,7 @@ spi@8011a000 {
#size-cells = <0>; #size-cells = <0>;
/* Same clock wired to kernel and pclk */ /* Same clock wired to kernel and pclk */
clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>; clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
clock-names = "spi0clk", "apb_pclk"; clock-names = "SSPCLK", "apb_pclk";
dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */ dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
<&dma 0 0 0x0>; /* Logical - MemToDev */ <&dma 0 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx"; dma-names = "rx", "tx";
...@@ -746,7 +746,7 @@ spi@80112000 { ...@@ -746,7 +746,7 @@ spi@80112000 {
#size-cells = <0>; #size-cells = <0>;
/* Same clock wired to kernel and pclk */ /* Same clock wired to kernel and pclk */
clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>; clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
clock-names = "spi1clk", "apb_pclk"; clock-names = "SSPCLK", "apb_pclk";
dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */ dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
<&dma 35 0 0x0>; /* Logical - MemToDev */ <&dma 35 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx"; dma-names = "rx", "tx";
...@@ -760,7 +760,7 @@ spi@80111000 { ...@@ -760,7 +760,7 @@ spi@80111000 {
#size-cells = <0>; #size-cells = <0>;
/* Same clock wired to kernel and pclk */ /* Same clock wired to kernel and pclk */
clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>; clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
clock-names = "spi2clk", "apb_pclk"; clock-names = "SSPCLK", "apb_pclk";
dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */ dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
<&dma 33 0 0x0>; /* Logical - MemToDev */ <&dma 33 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx"; dma-names = "rx", "tx";
...@@ -774,7 +774,7 @@ spi@80129000 { ...@@ -774,7 +774,7 @@ spi@80129000 {
#size-cells = <0>; #size-cells = <0>;
/* Same clock wired to kernel and pclk */ /* Same clock wired to kernel and pclk */
clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>; clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
clock-names = "spi3clk", "apb_pclk"; clock-names = "SSPCLK", "apb_pclk";
dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */ dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
<&dma 40 0 0x0>; /* Logical - MemToDev */ <&dma 40 0 0x0>; /* Logical - MemToDev */
dma-names = "rx", "tx"; dma-names = "rx", "tx";
......
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