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Commit 819d1413 authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Wim Van Sebroeck
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dt-bindings: watchdog: indentation, quotes and white-space cleanup 

Minor cleanup without functional impact:
1. Indent DTS examples to preferred four-spaces (more readable for DTS),
2. Drop unneeded quotes,
3. Add/drop blank lines to make the code readable.
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: default avatarSergio Paracuellos <sergio.paracuellos@gmail.com>
Acked-by: default avatarJustin Chen <justinpopo6@gmail.com>
Acked-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Acked-by: default avatarNicolas Ferre <nicolas.ferre@microchip.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230415095112.51257-2-krzysztof.kozlowski@linaro.orgSigned-off-by: default avatarGuenter Roeck <linux@roeck-us.net>
Signed-off-by: default avatarWim Van Sebroeck <wim@linux-watchdog.org>
parent ab8da076
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Showing with 83 additions and 83 deletions
Documentation/devicetree/bindings/watchdog/amlogic,meson-gxbb-wdt.yaml
View file @ 819d1413
......@@ -2,8 +2,8 @@
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
$id: "http://devicetree.org/schemas/watchdog/amlogic,meson-gxbb-wdt.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
$id: http://devicetree.org/schemas/watchdog/amlogic,meson-gxbb-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Meson GXBB SoCs Watchdog timer
......@@ -36,7 +36,7 @@ unevaluatedProperties: false
examples:
- |
watchdog@98d0 {
compatible = "amlogic,meson-gxbb-wdt";
reg = <0x98d0 0x10>;
clocks = <&xtal>;
compatible = "amlogic,meson-gxbb-wdt";
reg = <0x98d0 0x10>;
clocks = <&xtal>;
};
Documentation/devicetree/bindings/watchdog/arm,sbsa-gwdt.yaml
View file @ 819d1413
......@@ -40,7 +40,6 @@ unevaluatedProperties: false
examples:
- |
watchdog@2a440000 {
compatible = "arm,sbsa-gwdt";
reg = <0x2a440000 0x1000>,
......
Documentation/devicetree/bindings/watchdog/arm,twd-wdt.yaml
View file @ 819d1413
......@@ -44,7 +44,7 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
watchdog@2c000620 {
compatible = "arm,arm11mp-twd-wdt";
reg = <0x2c000620 0x20>;
interrupts = <GIC_PPI 14 0xf01>;
compatible = "arm,arm11mp-twd-wdt";
reg = <0x2c000620 0x20>;
interrupts = <GIC_PPI 14 0xf01>;
};
Documentation/devicetree/bindings/watchdog/arm-smc-wdt.yaml
View file @ 819d1413
......@@ -16,6 +16,7 @@ properties:
compatible:
enum:
- arm,smc-wdt
arm,smc-id:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
......@@ -30,9 +31,9 @@ unevaluatedProperties: false
examples:
- |
watchdog {
compatible = "arm,smc-wdt";
arm,smc-id = <0x82003D06>;
timeout-sec = <15>;
compatible = "arm,smc-wdt";
arm,smc-id = <0x82003D06>;
timeout-sec = <15>;
};
...
Documentation/devicetree/bindings/watchdog/atmel,sama5d4-wdt.yaml
View file @ 819d1413
......@@ -65,13 +65,13 @@ examples:
#include <dt-bindings/interrupt-controller/irq.h>
watchdog@fc068640 {
compatible = "atmel,sama5d4-wdt";
reg = <0xfc068640 0x10>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 5>;
timeout-sec = <10>;
atmel,watchdog-type = "hardware";
atmel,dbg-halt;
atmel,idle-halt;
compatible = "atmel,sama5d4-wdt";
reg = <0xfc068640 0x10>;
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 5>;
timeout-sec = <10>;
atmel,watchdog-type = "hardware";
atmel,dbg-halt;
atmel,idle-halt;
};
...
Documentation/devicetree/bindings/watchdog/brcm,bcm7038-wdt.yaml
View file @ 819d1413
......@@ -37,7 +37,7 @@ required:
examples:
- |
watchdog@f040a7e8 {
compatible = "brcm,bcm7038-wdt";
reg = <0xf040a7e8 0x16>;
clocks = <&upg_fixed>;
compatible = "brcm,bcm7038-wdt";
reg = <0xf040a7e8 0x16>;
clocks = <&upg_fixed>;
};
Documentation/devicetree/bindings/watchdog/faraday,ftwdt010.yaml
View file @ 819d1413
......@@ -52,16 +52,16 @@ examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
watchdog@41000000 {
compatible = "faraday,ftwdt010";
reg = <0x41000000 0x1000>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
timeout-sec = <5>;
compatible = "faraday,ftwdt010";
reg = <0x41000000 0x1000>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
timeout-sec = <5>;
};
- |
watchdog: watchdog@98500000 {
compatible = "moxa,moxart-watchdog", "faraday,ftwdt010";
reg = <0x98500000 0x10>;
clocks = <&clk_apb>;
clock-names = "PCLK";
compatible = "moxa,moxart-watchdog", "faraday,ftwdt010";
reg = <0x98500000 0x10>;
clocks = <&clk_apb>;
clock-names = "PCLK";
};
...
Documentation/devicetree/bindings/watchdog/mediatek,mt7621-wdt.yaml
View file @ 819d1413
......@@ -34,7 +34,7 @@ additionalProperties: false
examples:
- |
watchdog@100 {
compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x100>;
mediatek,sysctl = <&sysc>;
compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x100>;
mediatek,sysctl = <&sysc>;
};
Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml
View file @ 819d1413
......@@ -116,26 +116,26 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
watchdog@17c10000 {
compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
reg = <0x17c10000 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
timeout-sec = <10>;
compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
reg = <0x17c10000 0x1000>;
clocks = <&sleep_clk>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
timeout-sec = <10>;
};
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
watchdog@200a000 {
compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer";
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
reg = <0x0200a000 0x100>;
clock-frequency = <25000000>;
clocks = <&sleep_clk>;
clock-names = "sleep";
cpu-offset = <0x80000>;
compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer";
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
<GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
reg = <0x0200a000 0x100>;
clock-frequency = <25000000>;
clocks = <&sleep_clk>;
clock-names = "sleep";
cpu-offset = <0x80000>;
};
Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
View file @ 819d1413
......@@ -177,11 +177,11 @@ examples:
#include <dt-bindings/power/r8a7795-sysc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
wdt0: watchdog@e6020000 {
compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
reg = <0xe6020000 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 402>;
timeout-sec = <60>;
compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
reg = <0xe6020000 0x0c>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 402>;
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
resets = <&cpg 402>;
timeout-sec = <60>;
};
Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml
View file @ 819d1413
......@@ -83,25 +83,25 @@ required:
examples:
- |
watchdog@ffd02000 {
compatible = "snps,dw-wdt";
reg = <0xffd02000 0x1000>;
interrupts = <0 171 4>;
clocks = <&per_base_clk>;
resets = <&wdt_rst>;
compatible = "snps,dw-wdt";
reg = <0xffd02000 0x1000>;
interrupts = <0 171 4>;
clocks = <&per_base_clk>;
resets = <&wdt_rst>;
};
- |
watchdog@ffd02000 {
compatible = "snps,dw-wdt";
reg = <0xffd02000 0x1000>;
interrupts = <0 171 4>;
clocks = <&per_base_clk>;
clock-names = "tclk";
snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
0x000007FF 0x0000FFFF 0x0001FFFF
0x0003FFFF 0x0007FFFF 0x000FFFFF
0x001FFFFF 0x003FFFFF 0x007FFFFF
0x00FFFFFF 0x01FFFFFF 0x03FFFFFF
0x07FFFFFF>;
compatible = "snps,dw-wdt";
reg = <0xffd02000 0x1000>;
interrupts = <0 171 4>;
clocks = <&per_base_clk>;
clock-names = "tclk";
snps,watchdog-tops = <0x000000FF 0x000001FF 0x000003FF
0x000007FF 0x0000FFFF 0x0001FFFF
0x0003FFFF 0x0007FFFF 0x000FFFFF
0x001FFFFF 0x003FFFFF 0x007FFFFF
0x00FFFFFF 0x01FFFFFF 0x03FFFFFF
0x07FFFFFF>;
};
...
Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml
View file @ 819d1413
......@@ -48,11 +48,11 @@ examples:
- |
#include <dt-bindings/clock/stm32mp1-clks.h>
watchdog@5a002000 {
compatible = "st,stm32mp1-iwdg";
reg = <0x5a002000 0x400>;
clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
clock-names = "pclk", "lsi";
timeout-sec = <32>;
compatible = "st,stm32mp1-iwdg";
reg = <0x5a002000 0x400>;
clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
clock-names = "pclk", "lsi";
timeout-sec = <32>;
};
...
Documentation/devicetree/bindings/watchdog/xlnx,xps-timebase-wdt.yaml
View file @ 819d1413
......@@ -58,11 +58,11 @@ unevaluatedProperties: false
examples:
- |
watchdog@40100000 {
compatible = "xlnx,xps-timebase-wdt-1.00.a";
reg = <0x40100000 0x1000>;
clock-frequency = <50000000>;
clocks = <&clkc 15>;
xlnx,wdt-enable-once = <0x0>;
xlnx,wdt-interval = <0x1b>;
compatible = "xlnx,xps-timebase-wdt-1.00.a";
reg = <0x40100000 0x1000>;
clock-frequency = <50000000>;
clocks = <&clkc 15>;
xlnx,wdt-enable-once = <0x0>;
xlnx,wdt-interval = <0x1b>;
};
...
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