Commit 81af2952 authored by Gil Fine's avatar Gil Fine Committed by Mika Westerberg

thunderbolt: Add support for asymmetric link

USB4 v2 spec defines a Gen 4 link that can operate as an aggregated
symmetric (80/80G) or asymmetric (120/40G). When the link is asymmetric,
the USB4 port on one side of the link operates with three TX lanes and
one RX lane, while the USB4 port on the opposite side of the link
operates with three RX lanes and one TX lane.

Add support for the asymmetric link and provide functions that can be
used to transition the link to asymmetric and back.
Signed-off-by: default avatarGil Fine <gil.fine@linux.intel.com>
Co-developed-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: default avatarMika Westerberg <mika.westerberg@linux.intel.com>
parent c4ff1443
This diff is collapsed.
...@@ -985,7 +985,7 @@ static void tb_scan_port(struct tb_port *port) ...@@ -985,7 +985,7 @@ static void tb_scan_port(struct tb_port *port)
} }
/* Enable lane bonding if supported */ /* Enable lane bonding if supported */
tb_switch_lane_bonding_enable(sw); tb_switch_set_link_width(sw, TB_LINK_WIDTH_DUAL);
/* Set the link configured */ /* Set the link configured */
tb_switch_configure_link(sw); tb_switch_configure_link(sw);
/* /*
...@@ -1103,7 +1103,8 @@ static void tb_free_unplugged_children(struct tb_switch *sw) ...@@ -1103,7 +1103,8 @@ static void tb_free_unplugged_children(struct tb_switch *sw)
tb_retimer_remove_all(port); tb_retimer_remove_all(port);
tb_remove_dp_resources(port->remote->sw); tb_remove_dp_resources(port->remote->sw);
tb_switch_unconfigure_link(port->remote->sw); tb_switch_unconfigure_link(port->remote->sw);
tb_switch_lane_bonding_disable(port->remote->sw); tb_switch_set_link_width(port->remote->sw,
TB_LINK_WIDTH_SINGLE);
tb_switch_remove(port->remote->sw); tb_switch_remove(port->remote->sw);
port->remote = NULL; port->remote = NULL;
if (port->dual_link_port) if (port->dual_link_port)
...@@ -1721,7 +1722,8 @@ static void tb_handle_hotplug(struct work_struct *work) ...@@ -1721,7 +1722,8 @@ static void tb_handle_hotplug(struct work_struct *work)
tb_remove_dp_resources(port->remote->sw); tb_remove_dp_resources(port->remote->sw);
tb_switch_tmu_disable(port->remote->sw); tb_switch_tmu_disable(port->remote->sw);
tb_switch_unconfigure_link(port->remote->sw); tb_switch_unconfigure_link(port->remote->sw);
tb_switch_lane_bonding_disable(port->remote->sw); tb_switch_set_link_width(port->remote->sw,
TB_LINK_WIDTH_SINGLE);
tb_switch_remove(port->remote->sw); tb_switch_remove(port->remote->sw);
port->remote = NULL; port->remote = NULL;
if (port->dual_link_port) if (port->dual_link_port)
...@@ -2203,7 +2205,8 @@ static void tb_restore_children(struct tb_switch *sw) ...@@ -2203,7 +2205,8 @@ static void tb_restore_children(struct tb_switch *sw)
continue; continue;
if (port->remote) { if (port->remote) {
tb_switch_lane_bonding_enable(port->remote->sw); tb_switch_set_link_width(port->remote->sw,
port->remote->sw->link_width);
tb_switch_configure_link(port->remote->sw); tb_switch_configure_link(port->remote->sw);
tb_restore_children(port->remote->sw); tb_restore_children(port->remote->sw);
......
...@@ -162,11 +162,6 @@ struct tb_switch_tmu { ...@@ -162,11 +162,6 @@ struct tb_switch_tmu {
* switches) you need to have domain lock held. * switches) you need to have domain lock held.
* *
* In USB4 terminology this structure represents a router. * In USB4 terminology this structure represents a router.
*
* Note @link_width is not the same as whether link is bonded or not.
* For Gen 4 links the link is also bonded when it is asymmetric. The
* correct way to find out whether the link is bonded or not is to look
* @bonded field of the upstream port.
*/ */
struct tb_switch { struct tb_switch {
struct device dev; struct device dev;
...@@ -967,8 +962,7 @@ static inline bool tb_switch_is_icm(const struct tb_switch *sw) ...@@ -967,8 +962,7 @@ static inline bool tb_switch_is_icm(const struct tb_switch *sw)
return !sw->config.enabled; return !sw->config.enabled;
} }
int tb_switch_lane_bonding_enable(struct tb_switch *sw); int tb_switch_set_link_width(struct tb_switch *sw, enum tb_link_width width);
void tb_switch_lane_bonding_disable(struct tb_switch *sw);
int tb_switch_configure_link(struct tb_switch *sw); int tb_switch_configure_link(struct tb_switch *sw);
void tb_switch_unconfigure_link(struct tb_switch *sw); void tb_switch_unconfigure_link(struct tb_switch *sw);
...@@ -1100,10 +1094,11 @@ static inline bool tb_port_use_credit_allocation(const struct tb_port *port) ...@@ -1100,10 +1094,11 @@ static inline bool tb_port_use_credit_allocation(const struct tb_port *port)
int tb_port_get_link_speed(struct tb_port *port); int tb_port_get_link_speed(struct tb_port *port);
int tb_port_get_link_generation(struct tb_port *port); int tb_port_get_link_generation(struct tb_port *port);
int tb_port_get_link_width(struct tb_port *port); int tb_port_get_link_width(struct tb_port *port);
bool tb_port_width_supported(struct tb_port *port, unsigned int width);
int tb_port_set_link_width(struct tb_port *port, enum tb_link_width width); int tb_port_set_link_width(struct tb_port *port, enum tb_link_width width);
int tb_port_lane_bonding_enable(struct tb_port *port); int tb_port_lane_bonding_enable(struct tb_port *port);
void tb_port_lane_bonding_disable(struct tb_port *port); void tb_port_lane_bonding_disable(struct tb_port *port);
int tb_port_wait_for_link_width(struct tb_port *port, unsigned int width_mask, int tb_port_wait_for_link_width(struct tb_port *port, unsigned int width,
int timeout_msec); int timeout_msec);
int tb_port_update_credits(struct tb_port *port); int tb_port_update_credits(struct tb_port *port);
...@@ -1297,6 +1292,11 @@ int usb4_port_router_online(struct tb_port *port); ...@@ -1297,6 +1292,11 @@ int usb4_port_router_online(struct tb_port *port);
int usb4_port_enumerate_retimers(struct tb_port *port); int usb4_port_enumerate_retimers(struct tb_port *port);
bool usb4_port_clx_supported(struct tb_port *port); bool usb4_port_clx_supported(struct tb_port *port);
int usb4_port_margining_caps(struct tb_port *port, u32 *caps); int usb4_port_margining_caps(struct tb_port *port, u32 *caps);
bool usb4_port_asym_supported(struct tb_port *port);
int usb4_port_asym_set_link_width(struct tb_port *port, enum tb_link_width width);
int usb4_port_asym_start(struct tb_port *port);
int usb4_port_hw_margin(struct tb_port *port, unsigned int lanes, int usb4_port_hw_margin(struct tb_port *port, unsigned int lanes,
unsigned int ber_level, bool timing, bool right_high, unsigned int ber_level, bool timing, bool right_high,
u32 *results); u32 *results);
......
...@@ -346,10 +346,14 @@ struct tb_regs_port_header { ...@@ -346,10 +346,14 @@ struct tb_regs_port_header {
#define LANE_ADP_CS_1 0x01 #define LANE_ADP_CS_1 0x01
#define LANE_ADP_CS_1_TARGET_SPEED_MASK GENMASK(3, 0) #define LANE_ADP_CS_1_TARGET_SPEED_MASK GENMASK(3, 0)
#define LANE_ADP_CS_1_TARGET_SPEED_GEN3 0xc #define LANE_ADP_CS_1_TARGET_SPEED_GEN3 0xc
#define LANE_ADP_CS_1_TARGET_WIDTH_MASK GENMASK(9, 4) #define LANE_ADP_CS_1_TARGET_WIDTH_MASK GENMASK(5, 4)
#define LANE_ADP_CS_1_TARGET_WIDTH_SHIFT 4 #define LANE_ADP_CS_1_TARGET_WIDTH_SHIFT 4
#define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE 0x1 #define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE 0x1
#define LANE_ADP_CS_1_TARGET_WIDTH_DUAL 0x3 #define LANE_ADP_CS_1_TARGET_WIDTH_DUAL 0x3
#define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK GENMASK(7, 6)
#define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_TX 0x1
#define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_RX 0x2
#define LANE_ADP_CS_1_TARGET_WIDTH_ASYM_DUAL 0x0
#define LANE_ADP_CS_1_CL0S_ENABLE BIT(10) #define LANE_ADP_CS_1_CL0S_ENABLE BIT(10)
#define LANE_ADP_CS_1_CL1_ENABLE BIT(11) #define LANE_ADP_CS_1_CL1_ENABLE BIT(11)
#define LANE_ADP_CS_1_CL2_ENABLE BIT(12) #define LANE_ADP_CS_1_CL2_ENABLE BIT(12)
...@@ -382,12 +386,15 @@ struct tb_regs_port_header { ...@@ -382,12 +386,15 @@ struct tb_regs_port_header {
#define PORT_CS_18_WOCS BIT(16) #define PORT_CS_18_WOCS BIT(16)
#define PORT_CS_18_WODS BIT(17) #define PORT_CS_18_WODS BIT(17)
#define PORT_CS_18_WOU4S BIT(18) #define PORT_CS_18_WOU4S BIT(18)
#define PORT_CS_18_CSA BIT(22)
#define PORT_CS_18_TIP BIT(24)
#define PORT_CS_19 0x13 #define PORT_CS_19 0x13
#define PORT_CS_19_PC BIT(3) #define PORT_CS_19_PC BIT(3)
#define PORT_CS_19_PID BIT(4) #define PORT_CS_19_PID BIT(4)
#define PORT_CS_19_WOC BIT(16) #define PORT_CS_19_WOC BIT(16)
#define PORT_CS_19_WOD BIT(17) #define PORT_CS_19_WOD BIT(17)
#define PORT_CS_19_WOU4 BIT(18) #define PORT_CS_19_WOU4 BIT(18)
#define PORT_CS_19_START_ASYM BIT(24)
/* Display Port adapter registers */ /* Display Port adapter registers */
#define ADP_DP_CS_0 0x00 #define ADP_DP_CS_0 0x00
......
...@@ -1454,6 +1454,112 @@ bool usb4_port_clx_supported(struct tb_port *port) ...@@ -1454,6 +1454,112 @@ bool usb4_port_clx_supported(struct tb_port *port)
return !!(val & PORT_CS_18_CPS); return !!(val & PORT_CS_18_CPS);
} }
/**
* usb4_port_asym_supported() - If the port supports asymmetric link
* @port: USB4 port
*
* Checks if the port and the cable supports asymmetric link and returns
* %true in that case.
*/
bool usb4_port_asym_supported(struct tb_port *port)
{
u32 val;
if (!port->cap_usb4)
return false;
if (tb_port_read(port, &val, TB_CFG_PORT, port->cap_usb4 + PORT_CS_18, 1))
return false;
return !!(val & PORT_CS_18_CSA);
}
/**
* usb4_port_asym_set_link_width() - Set link width to asymmetric or symmetric
* @port: USB4 port
* @width: Asymmetric width to configure
*
* Sets USB4 port link width to @width. Can be called for widths where
* usb4_port_asym_width_supported() returned @true.
*/
int usb4_port_asym_set_link_width(struct tb_port *port, enum tb_link_width width)
{
u32 val;
int ret;
if (!port->cap_phy)
return -EINVAL;
ret = tb_port_read(port, &val, TB_CFG_PORT,
port->cap_phy + LANE_ADP_CS_1, 1);
if (ret)
return ret;
val &= ~LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK;
switch (width) {
case TB_LINK_WIDTH_DUAL:
val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
LANE_ADP_CS_1_TARGET_WIDTH_ASYM_DUAL);
break;
case TB_LINK_WIDTH_ASYM_TX:
val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
LANE_ADP_CS_1_TARGET_WIDTH_ASYM_TX);
break;
case TB_LINK_WIDTH_ASYM_RX:
val |= FIELD_PREP(LANE_ADP_CS_1_TARGET_WIDTH_ASYM_MASK,
LANE_ADP_CS_1_TARGET_WIDTH_ASYM_RX);
break;
default:
return -EINVAL;
}
return tb_port_write(port, &val, TB_CFG_PORT,
port->cap_phy + LANE_ADP_CS_1, 1);
}
/**
* usb4_port_asym_start() - Start symmetry change and wait for completion
* @port: USB4 port
*
* Start symmetry change of the link to asymmetric or symmetric
* (according to what was previously set in tb_port_set_link_width().
* Wait for completion of the change.
*
* Returns %0 in case of success, %-ETIMEDOUT if case of timeout or
* a negative errno in case of a failure.
*/
int usb4_port_asym_start(struct tb_port *port)
{
int ret;
u32 val;
ret = tb_port_read(port, &val, TB_CFG_PORT,
port->cap_usb4 + PORT_CS_19, 1);
if (ret)
return ret;
val &= ~PORT_CS_19_START_ASYM;
val |= FIELD_PREP(PORT_CS_19_START_ASYM, 1);
ret = tb_port_write(port, &val, TB_CFG_PORT,
port->cap_usb4 + PORT_CS_19, 1);
if (ret)
return ret;
/*
* Wait for PORT_CS_19_START_ASYM to be 0. This means the USB4
* port started the symmetry transition.
*/
ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_19,
PORT_CS_19_START_ASYM, 0, 1000);
if (ret)
return ret;
/* Then wait for the transtion to be completed */
return usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_18,
PORT_CS_18_TIP, 0, 5000);
}
/** /**
* usb4_port_margining_caps() - Read USB4 port marginig capabilities * usb4_port_margining_caps() - Read USB4 port marginig capabilities
* @port: USB4 port * @port: USB4 port
......
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