Commit 81ee6693 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Greg Kroah-Hartman

mmc: sunxi: Keep default timing phase settings for new timing mode

commit 26cb2be4 upstream.

The register for the "new timing mode" also has bit fields for setting
output and sample timing phases. According to comments in Allwinner's
BSP kernel, the default values are good enough.

Keep the default values already in the hardware when setting new timing
mode, instead of overwriting the whole register.

Fixes: 9a37e53e ("mmc: sunxi: Enable the new timings for the A64 MMC
controllers")
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 2759c248
...@@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, ...@@ -793,8 +793,12 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
} }
mmc_writel(host, REG_CLKCR, rval); mmc_writel(host, REG_CLKCR, rval);
if (host->cfg->needs_new_timings) if (host->cfg->needs_new_timings) {
mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE); /* Don't touch the delay bits */
rval = mmc_readl(host, REG_SD_NTSR);
rval |= SDXC_2X_TIMING_MODE;
mmc_writel(host, REG_SD_NTSR, rval);
}
ret = sunxi_mmc_clk_set_phase(host, ios, rate); ret = sunxi_mmc_clk_set_phase(host, ios, rate);
if (ret) if (ret)
......
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