Commit 821e4e93 authored by Roland Vossen's avatar Roland Vossen Committed by Greg Kroah-Hartman

staging: brcm80211: removed unused bus code from softmac

Code cleanup. For the softmac, the 'bustype' in use is always PCI_BUS. Hence
code related to dealing with different bus types (eg: PCI_BUS, JTAG_BUS,
SI_BUS) could be removed.
Reviewed-by: default avatarPieter-Paul Giesberts <pieterpg@broadcom.com>
Signed-off-by: default avatarArend van Spriel <arend@broadcom.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@suse.de>
parent 09f882b0
......@@ -330,10 +330,8 @@
#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
#define PCI(si) (((si)->pub.bustype == PCI_BUS) && \
((si)->pub.buscoretype == PCI_CORE_ID))
#define PCIE(si) (((si)->pub.bustype == PCI_BUS) && \
((si)->pub.buscoretype == PCIE_CORE_ID))
#define PCI(si) ((si)->pub.buscoretype == PCI_CORE_ID)
#define PCIE(si) ((si)->pub.buscoretype == PCIE_CORE_ID)
#define PCI_FORCEHT(si) \
(PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))
......@@ -351,7 +349,6 @@
* public (read-only) portion of aiutils handle returned by si_attach()
*/
struct si_pub {
uint bustype; /* SI_BUS, PCI_BUS */
uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
uint buscorerev; /* buscore rev */
uint buscoreidx; /* buscore index */
......@@ -518,9 +515,8 @@ extern u32 ai_addrspacesize(struct si_pub *sih, uint asidx);
extern void ai_write_wrap_reg(struct si_pub *sih, u32 offset, u32 val);
/* === exported functions === */
extern struct si_pub *ai_attach(void *regs, uint bustype,
void *sdh, char **vars, uint *varsz);
extern struct si_pub *ai_attach(void *regs, void *sdh, char **vars,
uint *varsz);
extern void ai_detach(struct si_pub *sih);
extern bool ai_pci_war16165(struct si_pub *sih);
......
......@@ -451,14 +451,11 @@ struct dma_pub *dma_attach(char *name, struct si_pub *sih,
*/
di->ddoffsetlow = 0;
di->dataoffsetlow = 0;
/* for pci bus, add offset */
if (sih->bustype == PCI_BUS) {
/* pcie with DMA64 */
di->ddoffsetlow = 0;
di->ddoffsethigh = SI_PCIE_DMA_H32;
di->dataoffsetlow = di->ddoffsetlow;
di->dataoffsethigh = di->ddoffsethigh;
}
/* add offset for pcie with DMA64 bus */
di->ddoffsetlow = 0;
di->ddoffsethigh = SI_PCIE_DMA_H32;
di->dataoffsetlow = di->ddoffsetlow;
di->dataoffsethigh = di->ddoffsethigh;
#if defined(__mips__) && defined(IL_BIGENDIAN)
di->dataoffsetlow = di->dataoffsetlow + SI_SDRAM_SWAPPED;
#endif /* defined(__mips__) && defined(IL_BIGENDIAN) */
......
......@@ -755,7 +755,7 @@ static int brcms_set_hint(struct brcms_info *wl, char *abbrev)
*/
static struct brcms_info *brcms_attach(u16 vendor, u16 device,
unsigned long regs,
uint bustype, void *btparam, uint irq)
void *btparam, uint irq)
{
struct brcms_info *wl = NULL;
int unit, err;
......@@ -786,14 +786,6 @@ static struct brcms_info *brcms_attach(u16 vendor, u16 device,
base_addr = regs;
if (bustype == PCI_BUS || bustype == RPC_BUS) {
/* Do nothing */
} else {
bustype = PCI_BUS;
BCMMSG(wl->wiphy, "force to PCI\n");
}
wl->bcm_bustype = bustype;
wl->regsva = ioremap_nocache(base_addr, PCI_BAR0_WINSZ);
if (wl->regsva == NULL) {
wiphy_err(wl->wiphy, "wl%d: ioremap() failed\n", unit);
......@@ -813,7 +805,7 @@ static struct brcms_info *brcms_attach(u16 vendor, u16 device,
/* common load-time initialization */
wl->wlc = brcms_c_attach((void *)wl, vendor, device, unit, false,
wl->regsva, wl->bcm_bustype, btparam, &err);
wl->regsva, btparam, &err);
brcms_release_fw(wl);
if (!wl->wlc) {
wiphy_err(wl->wiphy, "%s: attach() failed with code %d\n",
......@@ -1156,7 +1148,7 @@ brcms_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
memset(hw->priv, 0, sizeof(*wl));
wl = brcms_attach(pdev->vendor, pdev->device,
pci_resource_start(pdev, 0), PCI_BUS, pdev,
pci_resource_start(pdev, 0), pdev,
pdev->irq);
if (!wl) {
......@@ -1373,8 +1365,7 @@ static void brcms_free(struct brcms_info *wl)
* registers so we cannot unmap the chip registers until
* after calling unregister_netdev() .
*/
if (wl->regsva && wl->bcm_bustype != SDIO_BUS &&
wl->bcm_bustype != JTAG_BUS)
if (wl->regsva)
iounmap((void *)wl->regsva);
wl->regsva = NULL;
......
......@@ -60,8 +60,7 @@ struct brcms_info {
spinlock_t lock; /* per-device perimeter lock */
spinlock_t isr_lock; /* per-device ISR synchronization lock */
/* bus type and regsva for unmap in brcms_free() */
uint bcm_bustype; /* bus type */
/* regsva for unmap in brcms_free() */
void *regsva; /* opaque chip registers virtual address */
/* timer related fields */
......
......@@ -181,8 +181,7 @@
*/
#define BCMCFID(wlc, fid) brcms_b_write_shm((wlc)->hw, M_BCMC_FID, (fid))
#define BRCMS_WAR16165(wlc) (wlc->pub->sih->bustype == PCI_BUS && \
(!AP_ENAB(wlc->pub)) && (wlc->war16165))
#define BRCMS_WAR16165(wlc) ((!AP_ENAB(wlc->pub)) && (wlc->war16165))
/* Find basic rate for a given rate */
#define BRCMS_BASIC_RATE(wlc, rspec) \
......@@ -313,8 +312,8 @@ static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
struct brcms_b_state;
static int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device,
uint unit, bool piomode, void *regsva, uint bustype,
void *btparam);
uint unit, bool piomode, void *regsva,
void *btparam);
/* up/down, reset, clk */
static void brcms_b_reset(struct brcms_hardware *wlc_hw);
......@@ -4302,7 +4301,7 @@ struct brcms_pub *brcms_c_pub(void *wlc)
* put the whole chip in reset(driver down state), no clock
*/
int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device, uint unit,
bool piomode, void *regsva, uint bustype, void *btparam)
bool piomode, void *regsva, void *btparam)
{
struct brcms_hardware *wlc_hw;
struct d11regs *regs;
......@@ -4313,6 +4312,8 @@ int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device, uint unit,
bool wme = false;
struct shared_phy_params sha_params;
struct wiphy *wiphy = wlc->wiphy;
char *var;
unsigned long res;
BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, vendor,
device);
......@@ -4332,7 +4333,7 @@ int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device, uint unit,
* Do the hardware portion of the attach. Also initialize software
* state that depends on the particular hardware we are running.
*/
wlc_hw->sih = ai_attach(regsva, bustype, btparam,
wlc_hw->sih = ai_attach(regsva, btparam,
&wlc_hw->vars, &wlc_hw->vars_size);
if (wlc_hw->sih == NULL) {
wiphy_err(wiphy, "wl%d: brcms_b_attach: si_attach failed\n",
......@@ -4347,37 +4348,29 @@ int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device, uint unit,
* than those the BIOS recognizes for devices on PCMCIA_BUS,
* SDIO_BUS, and SROMless devices on PCI_BUS.
*/
#ifdef BCMBUSTYPE
bustype = BCMBUSTYPE;
#endif
if (bustype != SI_BUS) {
char *var;
unsigned long res;
var = getvar(vars, "vendid");
if (var && !kstrtoul(var, 0, &res)) {
vendor = (u16)res;
wiphy_err(wiphy, "Overriding vendor id = 0x%x\n",
vendor);
}
var = getvar(vars, "devid");
if (var && !kstrtoul(var, 0, &res)) {
u16 devid = (u16)res;
if (devid != 0xffff) {
device = devid;
wiphy_err(wiphy, "Overriding device id = 0x%x"
"\n", device);
}
var = getvar(vars, "vendid");
if (var && !kstrtoul(var, 0, &res)) {
vendor = (u16)res;
wiphy_err(wiphy, "Overriding vendor id = 0x%x\n",
vendor);
}
var = getvar(vars, "devid");
if (var && !kstrtoul(var, 0, &res)) {
u16 devid = (u16)res;
if (devid != 0xffff) {
device = devid;
wiphy_err(wiphy, "Overriding device id = 0x%x"
"\n", device);
}
}
/* verify again the device is supported */
if (!brcms_c_chipmatch(vendor, device)) {
wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported "
"vendor/device (0x%x/0x%x)\n",
unit, vendor, device);
err = 12;
goto fail;
}
/* verify again the device is supported */
if (!brcms_c_chipmatch(vendor, device)) {
wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported "
"vendor/device (0x%x/0x%x)\n",
unit, vendor, device);
err = 12;
goto fail;
}
wlc_hw->vendorid = vendor;
......@@ -4437,8 +4430,7 @@ int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device, uint unit,
if (wlc_hw->boardflags & BFL_NOPLLDOWN)
brcms_b_pllreq(wlc_hw, true, BRCMS_PLLREQ_SHARED);
if ((wlc_hw->sih->bustype == PCI_BUS)
&& (ai_pci_war16165(wlc_hw->sih)))
if (ai_pci_war16165(wlc_hw->sih))
wlc->war16165 = true;
/* check device id(srom, nvram etc.) to set bands */
......@@ -4491,7 +4483,6 @@ int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device, uint unit,
sha_params.boardvendor = wlc_hw->sih->boardvendor;
sha_params.boardflags = wlc_hw->boardflags;
sha_params.boardflags2 = wlc_hw->boardflags2;
sha_params.bustype = wlc_hw->sih->bustype;
sha_params.buscorerev = wlc_hw->sih->buscorerev;
/* alloc and save pointer to shared phy state area */
......@@ -4601,8 +4592,7 @@ int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device, uint unit,
brcms_c_coredisable(wlc_hw);
/* Match driver "down" state */
if (wlc_hw->sih->bustype == PCI_BUS)
ai_pci_down(wlc_hw->sih);
ai_pci_down(wlc_hw->sih);
/* register sb interrupt callback functions */
ai_register_intr_callback(wlc_hw->sih, (void *)brcms_c_wlintrsoff,
......@@ -4655,8 +4645,7 @@ int brcms_b_attach(struct brcms_c_info *wlc, u16 vendor, u16 device, uint unit,
* The common driver entry routine. Error codes should be unique
*/
void *brcms_c_attach(struct brcms_info *wl, u16 vendor, u16 device, uint unit,
bool piomode, void *regsva, uint bustype, void *btparam,
uint *perr)
bool piomode, void *regsva, void *btparam, uint *perr)
{
struct brcms_c_info *wlc;
uint err = 0;
......@@ -4696,7 +4685,7 @@ void *brcms_c_attach(struct brcms_info *wl, u16 vendor, u16 device, uint unit,
* inside, no more in rest of the attach)
*/
err = brcms_b_attach(wlc, vendor, device, unit, piomode, regsva,
bustype, btparam);
btparam);
if (err)
goto fail;
......@@ -5030,9 +5019,7 @@ int brcms_b_detach(struct brcms_c_info *wlc)
* be done before sb core switch
*/
ai_deregister_intr_callback(wlc_hw->sih);
if (wlc_hw->sih->bustype == PCI_BUS)
ai_pci_sleep(wlc_hw->sih);
ai_pci_sleep(wlc_hw->sih);
}
brcms_b_detach_dmapio(wlc_hw);
......@@ -5416,18 +5403,16 @@ void brcms_b_hw_up(struct brcms_hardware *wlc_hw)
ai_clkctl_init(wlc_hw->sih);
brcms_b_clkctl_clk(wlc_hw, CLK_FAST);
if (wlc_hw->sih->bustype == PCI_BUS) {
ai_pci_fixcfg(wlc_hw->sih);
ai_pci_fixcfg(wlc_hw->sih);
/*
* AI chip doesn't restore bar0win2 on
* hibernation/resume, need sw fixup
*/
if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
(wlc_hw->sih->chip == BCM43225_CHIP_ID))
wlc_hw->regs = (struct d11regs *)
ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
}
/*
* AI chip doesn't restore bar0win2 on
* hibernation/resume, need sw fixup
*/
if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
(wlc_hw->sih->chip == BCM43225_CHIP_ID))
wlc_hw->regs = (struct d11regs *)
ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
/*
* Inform phy that a POR reset has occurred so
......@@ -5467,8 +5452,7 @@ int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
*/
coremask = (1 << wlc_hw->wlc->core->coreidx);
if (wlc_hw->sih->bustype == PCI_BUS)
ai_pci_setup(wlc_hw->sih, coremask);
ai_pci_setup(wlc_hw->sih, coremask);
/*
* Need to read the hwradio status here to cover the case where the
......@@ -5477,14 +5461,12 @@ int brcms_b_up_prep(struct brcms_hardware *wlc_hw)
*/
if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
/* put SB PCI in down state again */
if (wlc_hw->sih->bustype == PCI_BUS)
ai_pci_down(wlc_hw->sih);
ai_pci_down(wlc_hw->sih);
brcms_b_xtal(wlc_hw, OFF);
return -ENOMEDIUM;
}
if (wlc_hw->sih->bustype == PCI_BUS)
ai_pci_up(wlc_hw->sih);
ai_pci_up(wlc_hw->sih);
/* reset the d11 core */
brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
......@@ -5707,8 +5689,7 @@ int brcms_b_down_finish(struct brcms_hardware *wlc_hw)
/* turn off primary xtal and pll */
if (!wlc_hw->noreset) {
if (wlc_hw->sih->bustype == PCI_BUS)
ai_pci_down(wlc_hw->sih);
ai_pci_down(wlc_hw->sih);
brcms_b_xtal(wlc_hw, OFF);
}
}
......
......@@ -213,9 +213,7 @@ struct pcicore_info {
/* debug/trace */
#define PCI_ERROR(args)
#define PCIE_PUB(sih) \
(((sih)->bustype == PCI_BUS) && \
((sih)->buscoretype == PCIE_CORE_ID))
#define PCIE_PUB(sih) ((sih)->buscoretype == PCIE_CORE_ID)
/* routines to access mdio slave device registers */
static bool pcie_mdiosetblock(struct pcicore_info *pi, uint blk);
......
......@@ -279,11 +279,9 @@ void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val)
W_REG(&pi->regs->phy4wdatalo, val);
}
if (pi->sh->bustype == PCI_BUS) {
if (++pi->phy_wreg >= pi->phy_wreg_limit) {
(void)R_REG(&pi->regs->maccontrol);
pi->phy_wreg = 0;
}
if (++pi->phy_wreg >= pi->phy_wreg_limit) {
(void)R_REG(&pi->regs->maccontrol);
pi->phy_wreg = 0;
}
}
......@@ -390,11 +388,9 @@ void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val)
#else
W_REG((u32 *)(&regs->phyregaddr),
addr | (val << 16));
if (pi->sh->bustype == PCI_BUS) {
if (++pi->phy_wreg >= pi->phy_wreg_limit) {
pi->phy_wreg = 0;
(void)R_REG(&regs->phyversion);
}
if (++pi->phy_wreg >= pi->phy_wreg_limit) {
pi->phy_wreg = 0;
(void)R_REG(&regs->phyversion);
}
#endif
}
......@@ -496,7 +492,6 @@ struct shared_phy *wlc_phy_shared_attach(struct shared_phy_params *shp)
sh->boardvendor = shp->boardvendor;
sh->boardflags = shp->boardflags;
sh->boardflags2 = shp->boardflags2;
sh->bustype = shp->bustype;
sh->buscorerev = shp->buscorerev;
sh->fast_timer = PHY_SW_TIMER_FAST;
......
......@@ -166,7 +166,6 @@ struct shared_phy_params {
struct phy_shim_info *physhim;
uint unit;
uint corerev;
uint bustype;
uint buscorerev;
char *vars;
u16 vid;
......
......@@ -565,7 +565,6 @@ struct shared_phy {
uint boardvendor;
u32 boardflags;
u32 boardflags2;
uint bustype;
uint buscorerev;
uint fast_timer;
uint slow_timer;
......@@ -1182,7 +1181,7 @@ extern void wlc_phy_table_write_nphy(struct brcms_phy *pi, u32, u32, u32,
(pi->ipa5g_on && CHSPEC_IS5G(pi->radio_chanspec)))
#define BRCMS_PHY_WAR_PR51571(pi) \
if (((pi)->sh->bustype == PCI_BUS) && NREV_LT((pi)->pubpi.phy_rev, 3)) \
if (NREV_LT((pi)->pubpi.phy_rev, 3)) \
(void)R_REG(&(pi)->regs->maccontrol)
extern void wlc_phy_cal_perical_nphy_run(struct brcms_phy *pi, u8 caltype);
......
......@@ -550,7 +550,7 @@ struct brcms_antselcfg {
/* common functions for every port */
extern void *brcms_c_attach(struct brcms_info *wl, u16 vendor, u16 device,
uint unit, bool piomode, void *regsva, uint bustype,
uint unit, bool piomode, void *regsva,
void *btparam, uint *perr);
extern uint brcms_c_detach(struct brcms_c_info *wlc);
extern int brcms_c_up(struct brcms_c_info *wlc);
......
......@@ -860,8 +860,7 @@ static int varbuf_append(struct brcms_varbuf *b, const char *fmt, ...)
* Initialize local vars from the right source for this platform.
* Return 0 on success, nonzero on error.
*/
int srom_var_init(struct si_pub *sih, uint bustype, void *curmap,
char **vars, uint *count)
int srom_var_init(struct si_pub *sih, void *curmap, char **vars, uint *count)
{
uint len;
......@@ -873,7 +872,7 @@ int srom_var_init(struct si_pub *sih, uint bustype, void *curmap,
*vars = NULL;
*count = 0;
if (curmap != NULL && bustype == PCI_BUS)
if (curmap != NULL)
return initvars_srom_pci(sih, curmap, vars, count);
return -EINVAL;
......
......@@ -20,8 +20,8 @@
#include "types.h"
/* Prototypes */
extern int srom_var_init(struct si_pub *sih, uint bus, void *curmap,
char **vars, uint *count);
extern int srom_var_init(struct si_pub *sih, void *curmap, char **vars,
uint *count);
extern int srom_read(struct si_pub *sih, uint bus, void *curmap,
uint byteoff, uint nbytes, u16 *buf, bool check_crc);
......
......@@ -20,14 +20,13 @@
#include <linux/types.h>
#include <linux/io.h>
#if 0
/* Bus types */
#define SI_BUS 0 /* SOC Interconnect */
#define PCI_BUS 1 /* PCI target */
#define SDIO_BUS 3 /* SDIO target */
#define JTAG_BUS 4 /* JTAG */
#define USB_BUS 5 /* USB (does not support R/W REG) */
#define SPI_BUS 6 /* gSPI target */
#define RPC_BUS 7 /* RPC target */
#endif
#define WL_CHAN_FREQ_RANGE_2G 0
#define WL_CHAN_FREQ_RANGE_5GL 1
......
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