Commit 82736d22 authored by Helen Fornazier's avatar Helen Fornazier Committed by Greg Kroah-Hartman

staging: sm750fb: Add space before if statement

This patch fix the checkpatch.pl warning:

ERROR: space required before the open parenthesis '('
Signed-off-by: default avatarHelen Fornazier <helen.fornazier@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent ce02a16a
...@@ -87,7 +87,7 @@ unsigned int getChipClock(void) ...@@ -87,7 +87,7 @@ unsigned int getChipClock(void)
{ {
pll_value_t pll; pll_value_t pll;
#if 1 #if 1
if(getChipType() == SM750LE) if (getChipType() == SM750LE)
return MHz(130); return MHz(130);
#endif #endif
...@@ -225,7 +225,7 @@ unsigned int ddk750_getVMSize(void) ...@@ -225,7 +225,7 @@ unsigned int ddk750_getVMSize(void)
unsigned int data; unsigned int data;
/* sm750le only use 64 mb memory*/ /* sm750le only use 64 mb memory*/
if(getChipType() == SM750LE) if (getChipType() == SM750LE)
return MB(64); return MB(64);
/* for 750,always use power mode0*/ /* for 750,always use power mode0*/
...@@ -252,7 +252,7 @@ int ddk750_initHw(initchip_param_t * pInitParam) ...@@ -252,7 +252,7 @@ int ddk750_initHw(initchip_param_t * pInitParam)
unsigned int ulReg; unsigned int ulReg;
#if 0 #if 0
//move the code to map regiter function. //move the code to map regiter function.
if(getChipType() == SM718) { if (getChipType() == SM718) {
/* turn on big endian bit*/ /* turn on big endian bit*/
ulReg = PEEK32(0x74); ulReg = PEEK32(0x74);
/* now consider register definition in a big endian pattern*/ /* now consider register definition in a big endian pattern*/
...@@ -272,7 +272,7 @@ int ddk750_initHw(initchip_param_t * pInitParam) ...@@ -272,7 +272,7 @@ int ddk750_initHw(initchip_param_t * pInitParam)
ulReg = FIELD_SET(ulReg,CURRENT_GATE,LOCALMEM,ON); ulReg = FIELD_SET(ulReg,CURRENT_GATE,LOCALMEM,ON);
setCurrentGate(ulReg); setCurrentGate(ulReg);
if(getChipType() != SM750LE) { if (getChipType() != SM750LE) {
/* set panel pll and graphic mode via mmio_88 */ /* set panel pll and graphic mode via mmio_88 */
ulReg = PEEK32(VGA_CONFIGURATION); ulReg = PEEK32(VGA_CONFIGURATION);
ulReg = FIELD_SET(ulReg,VGA_CONFIGURATION,PLL,PANEL); ulReg = FIELD_SET(ulReg,VGA_CONFIGURATION,PLL,PANEL);
...@@ -444,7 +444,7 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll) ...@@ -444,7 +444,7 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll)
/* for MXCLK register , no POD provided, so need be treated differently */ /* for MXCLK register , no POD provided, so need be treated differently */
if(pll->clockType != MXCLK_PLL) { if (pll->clockType != MXCLK_PLL) {
xparm = &xparm_PIXEL[0]; xparm = &xparm_PIXEL[0];
xcnt = sizeof(xparm_PIXEL)/sizeof(xparm_PIXEL[0]); xcnt = sizeof(xparm_PIXEL)/sizeof(xparm_PIXEL[0]);
} else { } else {
...@@ -466,11 +466,11 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll) ...@@ -466,11 +466,11 @@ unsigned int calcPllValue(unsigned int request_orig,pll_value_t *pll)
M += fl_quo * X / 10000; M += fl_quo * X / 10000;
/* round step */ /* round step */
M += (fl_quo*X % 10000)>5000?1:0; M += (fl_quo*X % 10000)>5000?1:0;
if(M < 256 && M > 0) { if (M < 256 && M > 0) {
unsigned int diff; unsigned int diff;
tmpClock = pll->inputFreq *M / N / X; tmpClock = pll->inputFreq *M / N / X;
diff = absDiff(tmpClock,request_orig); diff = absDiff(tmpClock,request_orig);
if(diff < miniDiff) { if (diff < miniDiff) {
pll->M = M; pll->M = M;
pll->N = N; pll->N = N;
pll->OD = xparm[d].od; pll->OD = xparm[d].od;
......
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