Commit 82e56393 authored by Paweł Jarosz's avatar Paweł Jarosz Committed by Heiko Stuebner

clk: rockchip: add 400MHz to rk3066 clock rates table

We need this to init PLL_CPLL to 400MHz at boot.
Signed-off-by: default avatarPaweł Jarosz <paweljarosz3691@gmail.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 1dfbec39
...@@ -89,6 +89,7 @@ static struct rockchip_pll_rate_table rk3188_pll_rates[] = { ...@@ -89,6 +89,7 @@ static struct rockchip_pll_rate_table rk3188_pll_rates[] = {
RK3066_PLL_RATE( 504000000, 1, 84, 4), RK3066_PLL_RATE( 504000000, 1, 84, 4),
RK3066_PLL_RATE( 456000000, 1, 76, 4), RK3066_PLL_RATE( 456000000, 1, 76, 4),
RK3066_PLL_RATE( 408000000, 1, 68, 4), RK3066_PLL_RATE( 408000000, 1, 68, 4),
RK3066_PLL_RATE( 400000000, 3, 100, 2),
RK3066_PLL_RATE( 384000000, 2, 128, 4), RK3066_PLL_RATE( 384000000, 2, 128, 4),
RK3066_PLL_RATE( 360000000, 1, 60, 4), RK3066_PLL_RATE( 360000000, 1, 60, 4),
RK3066_PLL_RATE( 312000000, 1, 52, 4), RK3066_PLL_RATE( 312000000, 1, 52, 4),
......
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