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Kirill Smelkov
linux
Commits
831add78
Commit
831add78
authored
Jan 27, 2005
by
Russell King
Browse files
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[ARM] Make vector labels consistent with naming scheme
Signed-off-by:
Russell King
<
rmk@arm.linux.org.uk
>
parent
e2884f24
Changes
1
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11 deletions
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-11
arch/arm/kernel/entry-armv.S
arch/arm/kernel/entry-armv.S
+11
-11
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arch/arm/kernel/entry-armv.S
View file @
831add78
...
@@ -429,7 +429,7 @@ ENTRY(__switch_to)
...
@@ -429,7 +429,7 @@ ENTRY(__switch_to)
__INIT
__INIT
/*
/*
*
Vector
stubs
.
NOTE
that
we
only
align
'vector_
IRQ
'
to
a
cache
line
boundary
,
*
Vector
stubs
.
NOTE
that
we
only
align
'vector_
irq
'
to
a
cache
line
boundary
,
*
and
we
rely
on
each
stub
being
exactly
48
(
1
.5
cache
lines
)
in
size
.
This
*
and
we
rely
on
each
stub
being
exactly
48
(
1
.5
cache
lines
)
in
size
.
This
*
means
that
we
only
ever
load
two
cache
lines
for
this
code
,
or
one
if
we
're
*
means
that
we
only
ever
load
two
cache
lines
for
this
code
,
or
one
if
we
're
*
lucky
.
We
also
copy
this
code
to
0x200
so
that
we
can
use
branches
in
the
*
lucky
.
We
also
copy
this
code
to
0x200
so
that
we
can
use
branches
in
the
...
@@ -441,7 +441,7 @@ __stubs_start:
...
@@ -441,7 +441,7 @@ __stubs_start:
*
Interrupt
dispatcher
*
Interrupt
dispatcher
*
Enter
in
IRQ
mode
,
spsr
=
SVC
/
USR
CPSR
,
lr
=
SVC
/
USR
PC
*
Enter
in
IRQ
mode
,
spsr
=
SVC
/
USR
CPSR
,
lr
=
SVC
/
USR
PC
*/
*/
vector_
IRQ
:
@
vector_
irq
:
@
@
save
mode
specific
registers
@
save
mode
specific
registers
@
@
ldr
r13
,
.
LCsirq
ldr
r13
,
.
LCsirq
...
@@ -484,7 +484,7 @@ vector_IRQ: @
...
@@ -484,7 +484,7 @@ vector_IRQ: @
*
Data
abort
dispatcher
-
dispatches
it
to
the
correct
handler
for
the
processor
mode
*
Data
abort
dispatcher
-
dispatches
it
to
the
correct
handler
for
the
processor
mode
*
Enter
in
ABT
mode
,
spsr
=
USR
CPSR
,
lr
=
USR
PC
*
Enter
in
ABT
mode
,
spsr
=
USR
CPSR
,
lr
=
USR
PC
*/
*/
vector_da
ta
:
@
vector_da
bt
:
@
@
save
mode
specific
registers
@
save
mode
specific
registers
@
@
ldr
r13
,
.
LCsabt
ldr
r13
,
.
LCsabt
...
@@ -527,7 +527,7 @@ vector_data: @
...
@@ -527,7 +527,7 @@ vector_data: @
*
Prefetch
abort
dispatcher
-
dispatches
it
to
the
correct
handler
for
the
processor
mode
*
Prefetch
abort
dispatcher
-
dispatches
it
to
the
correct
handler
for
the
processor
mode
*
Enter
in
ABT
mode
,
spsr
=
USR
CPSR
,
lr
=
USR
PC
*
Enter
in
ABT
mode
,
spsr
=
USR
CPSR
,
lr
=
USR
PC
*/
*/
vector_p
refetch
:
vector_p
abt
:
@
@
@
save
mode
specific
registers
@
save
mode
specific
registers
@
@
...
@@ -571,7 +571,7 @@ vector_prefetch:
...
@@ -571,7 +571,7 @@ vector_prefetch:
*
Undef
instr
entry
dispatcher
-
dispatches
it
to
the
correct
handler
for
the
processor
mode
*
Undef
instr
entry
dispatcher
-
dispatches
it
to
the
correct
handler
for
the
processor
mode
*
Enter
in
UND
mode
,
spsr
=
SVC
/
USR
CPSR
,
lr
=
SVC
/
USR
PC
*
Enter
in
UND
mode
,
spsr
=
SVC
/
USR
CPSR
,
lr
=
SVC
/
USR
PC
*/
*/
vector_und
efinstr
:
vector_und
:
@
@
@
save
mode
specific
registers
@
save
mode
specific
registers
@
@
...
@@ -620,7 +620,7 @@ vector_undefinstr:
...
@@ -620,7 +620,7 @@ vector_undefinstr:
*
other
mode
than
FIQ
...
Ok
you
can
switch
to
another
mode
,
but
you
can
't
*
other
mode
than
FIQ
...
Ok
you
can
switch
to
another
mode
,
but
you
can
't
*
get
out
of
that
mode
without
clobbering
one
register
.
*
get
out
of
that
mode
without
clobbering
one
register
.
*/
*/
vector_
FIQ
:
disable_fiq
vector_
fiq
:
disable_fiq
subs
pc
,
lr
,
#
4
subs
pc
,
lr
,
#
4
/*=============================================================================
/*=============================================================================
...
@@ -650,13 +650,13 @@ __stubs_end:
...
@@ -650,13 +650,13 @@ __stubs_end:
.
equ
__real_stubs_start
,
.
LCvectors
+
0x200
.
equ
__real_stubs_start
,
.
LCvectors
+
0x200
.
LCvectors
:
swi
SYS_ERROR0
.
LCvectors
:
swi
SYS_ERROR0
b
__real_stubs_start
+
(
vector_und
efinstr
-
__stubs_start
)
b
__real_stubs_start
+
(
vector_und
-
__stubs_start
)
ldr
pc
,
__real_stubs_start
+
(
.
LCvswi
-
__stubs_start
)
ldr
pc
,
__real_stubs_start
+
(
.
LCvswi
-
__stubs_start
)
b
__real_stubs_start
+
(
vector_p
refetch
-
__stubs_start
)
b
__real_stubs_start
+
(
vector_p
abt
-
__stubs_start
)
b
__real_stubs_start
+
(
vector_da
ta
-
__stubs_start
)
b
__real_stubs_start
+
(
vector_da
bt
-
__stubs_start
)
b
__real_stubs_start
+
(
vector_addrexcptn
-
__stubs_start
)
b
__real_stubs_start
+
(
vector_addrexcptn
-
__stubs_start
)
b
__real_stubs_start
+
(
vector_
IRQ
-
__stubs_start
)
b
__real_stubs_start
+
(
vector_
irq
-
__stubs_start
)
b
__real_stubs_start
+
(
vector_
FIQ
-
__stubs_start
)
b
__real_stubs_start
+
(
vector_
fiq
-
__stubs_start
)
ENTRY
(
__trap_init
)
ENTRY
(
__trap_init
)
stmfd
sp
!,
{
r4
-
r6
,
lr
}
stmfd
sp
!,
{
r4
-
r6
,
lr
}
...
...
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