Commit 834a4b58 authored by Russell King's avatar Russell King

[ARM] Update CLPS7500 support.

CLPS7500 had lacked behind slightly; this cset brings it back up to
date.
parent c4d190c5
......@@ -8,19 +8,22 @@
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
#include <asm/hardware.h>
#include <asm/hardware/iomd.h>
#include <asm/io.h>
#include <asm/page.h>
#include <asm/proc/domain.h>
#include <asm/setup.h>
#include <asm/irq.h>
#include <asm/mach-types.h>
static void cl7500_mask_irq_ack_a(unsigned int irq)
static void cl7500_ack_irq_a(unsigned int irq)
{
unsigned int val, mask;
......@@ -48,6 +51,12 @@ static void cl7500_unmask_irq_a(unsigned int irq)
iomd_writeb(val | mask, IOMD_IRQMASKA);
}
static struct irqchip clps7500_a_chip = {
.ack = cl7500_ack_irq_a,
.mask = cl7500_mask_irq_a,
.unmask = cl7500_unmask_irq_a,
};
static void cl7500_mask_irq_b(unsigned int irq)
{
unsigned int val, mask;
......@@ -66,6 +75,12 @@ static void cl7500_unmask_irq_b(unsigned int irq)
iomd_writeb(val | mask, IOMD_IRQMASKB);
}
static struct irqchip clps7500_b_chip = {
.ack = cl7500_mask_irq_b,
.mask = cl7500_mask_irq_b,
.unmask = cl7500_unmask_irq_b,
};
static void cl7500_mask_irq_c(unsigned int irq)
{
unsigned int val, mask;
......@@ -84,6 +99,11 @@ static void cl7500_unmask_irq_c(unsigned int irq)
iomd_writeb(val | mask, IOMD_IRQMASKC);
}
static struct irqchip clps7500_c_chip = {
.ack = cl7500_mask_irq_c,
.mask = cl7500_mask_irq_c,
.unmask = cl7500_unmask_irq_c,
};
static void cl7500_mask_irq_d(unsigned int irq)
{
......@@ -103,6 +123,12 @@ static void cl7500_unmask_irq_d(unsigned int irq)
iomd_writeb(val | mask, IOMD_IRQMASKD);
}
static struct irqchip clps7500_d_chip = {
.ack = cl7500_mask_irq_d,
.mask = cl7500_mask_irq_d,
.unmask = cl7500_unmask_irq_d,
};
static void cl7500_mask_irq_dma(unsigned int irq)
{
unsigned int val, mask;
......@@ -121,6 +147,12 @@ static void cl7500_unmask_irq_dma(unsigned int irq)
iomd_writeb(val | mask, IOMD_DMAMASK);
}
static struct irqchip clps7500_dma_chip = {
.ack = cl7500_mask_irq_dma,
.mask = cl7500_mask_irq_dma,
.unmask = cl7500_unmask_irq_dma,
};
static void cl7500_mask_irq_fiq(unsigned int irq)
{
unsigned int val, mask;
......@@ -139,6 +171,22 @@ static void cl7500_unmask_irq_fiq(unsigned int irq)
iomd_writeb(val | mask, IOMD_FIQMASK);
}
static struct irqchip clps7500_fiq_chip = {
.ack = cl7500_mask_irq_fiq,
.mask = cl7500_mask_irq_fiq,
.unmask = cl7500_unmask_irq_fiq,
};
static void cl7500_no_action(unsigned int irq)
{
}
static struct irqchip clps7500_no_chip = {
.ack = cl7500_no_action,
.mask = cl7500_no_action,
.unmask = cl7500_no_action,
};
static void no_action(int cpl, void *dev_id, struct pt_regs *regs)
{
}
......@@ -147,7 +195,7 @@ static struct irqaction irq_isa = { no_action, 0, 0, "isa", NULL, NULL };
static void __init clps7500_init_irq(void)
{
int irq;
unsigned int irq, flags;
iomd_writeb(0, IOMD_IRQMASKA);
iomd_writeb(0, IOMD_IRQMASKB);
......@@ -155,64 +203,58 @@ static void __init clps7500_init_irq(void)
iomd_writeb(0, IOMD_DMAMASK);
for (irq = 0; irq < NR_IRQS; irq++) {
flags = IRQF_VALID;
if (irq <= 6 || (irq >= 9 && irq <= 15) ||
(irq >= 48 && irq <= 55))
flags |= IRQF_PROBE;
switch (irq) {
case 0 ... 6:
irq_desc[irq].probe_ok = 1;
case 7:
irq_desc[irq].valid = 1;
irq_desc[irq].mask_ack = cl7500_mask_irq_ack_a;
irq_desc[irq].mask = cl7500_mask_irq_a;
irq_desc[irq].unmask = cl7500_unmask_irq_a;
case 0 ... 7:
set_irq_chip(irq, &clps7500_a_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_flags(irq, flags);
break;
case 9 ... 15:
irq_desc[irq].probe_ok = 1;
case 8:
irq_desc[irq].valid = 1;
irq_desc[irq].mask_ack = cl7500_mask_irq_b;
irq_desc[irq].mask = cl7500_mask_irq_b;
irq_desc[irq].unmask = cl7500_unmask_irq_b;
case 8 ... 15:
set_irq_chip(irq, &clps7500_b_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_flags(irq, flags);
break;
case 16 ... 22:
irq_desc[irq].valid = 1;
irq_desc[irq].mask_ack = cl7500_mask_irq_dma;
irq_desc[irq].mask = cl7500_mask_irq_dma;
irq_desc[irq].unmask = cl7500_unmask_irq_dma;
set_irq_chip(irq, &clps7500_dma_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_flags(irq, flags);
break;
case 24 ... 31:
irq_desc[irq].valid = 1;
irq_desc[irq].mask_ack = cl7500_mask_irq_c;
irq_desc[irq].mask = cl7500_mask_irq_c;
irq_desc[irq].unmask = cl7500_unmask_irq_c;
set_irq_chip(irq, &clps7500_c_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_flags(irq, flags);
break;
case 40 ... 47:
irq_desc[irq].valid = 1;
irq_desc[irq].mask_ack = cl7500_mask_irq_d;
irq_desc[irq].mask = cl7500_mask_irq_d;
irq_desc[irq].unmask = cl7500_unmask_irq_d;
set_irq_chip(irq, &clps7500_d_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_flags(irq, flags);
break;
case 48 ... 55:
irq_desc[irq].valid = 1;
irq_desc[irq].probe_ok = 1;
irq_desc[irq].mask_ack = no_action;
irq_desc[irq].mask = no_action;
irq_desc[irq].unmask = no_action;
set_irq_chip(irq, &clps7500_no_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_flags(irq, flags);
break;
case 64 ... 72:
irq_desc[irq].valid = 1;
irq_desc[irq].mask_ack = cl7500_mask_irq_fiq;
irq_desc[irq].mask = cl7500_mask_irq_fiq;
irq_desc[irq].unmask = cl7500_unmask_irq_fiq;
set_irq_chip(irq, &clps7500_fiq_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_flags(irq, flags);
break;
}
}
setup_arm_irq(IRQ_ISA, &irq_isa);
setup_irq(IRQ_ISA, &irq_isa);
}
static struct map_desc cl7500_io_desc[] __initdata = {
......
......@@ -239,4 +239,15 @@ DECLARE_IO(int,l,"")
/* the following macro is deprecated */
#define ioaddr(port) __ioaddr((port))
#define insb(p,d,l) __raw_readsb(__ioaddr(p),d,l)
#define insw(p,d,l) __raw_readsw(__ioaddr(p),d,l)
#define outsb(p,d,l) __raw_writesb(__ioaddr(p),d,l)
#define outsw(p,d,l) __raw_writesw(__ioaddr(p),d,l)
/*
* 1:1 mapping for ioremapped regions.
*/
#define __mem_pci(x) (x)
#endif
......@@ -17,6 +17,7 @@
#ifndef __ASSEMBLY__
struct tag;
struct meminfo;
struct machine_desc {
/*
......
......@@ -40,7 +40,6 @@ struct dma_struct {
unsigned int dma_base; /* Controller base address */
int dma_irq; /* Controller IRQ */
int state; /* Controller state */
struct scatterlist cur_sg; /* Current controller buffer */
struct dma_ops *d_ops;
......
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