drm/amd/display: Link training TPS1 workaround add back in dpcd

[Why]
Previously implemented early_cr_pattern we mistook dp_hw_link_settings
for a redundant call of dpcd_set_link_settings

[How]
revert the changes to dpcd_set_link_settings calls for this workaround.
Do not need to revert the entire change since it only affects patched
case
Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: David Galiffi <David.Galiffi@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

@@ -1446,11 +1446,11 @@ enum link_training_result dc_link_dp_perform_link_training(
 			&link->preferred_training_settings,
 			&lt_settings);
 
-	/* 1. set link rate, lane count and spread. */
 	if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
 		start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
-	else
-		dpcd_set_link_settings(link, &lt_settings);
+
+	/* 1. set link rate, lane count and spread. */
+	dpcd_set_link_settings(link, &lt_settings);
 
 	if (link->preferred_training_settings.fec_enable != NULL)
 		fec_enable = *link->preferred_training_settings.fec_enable;
@@ -1669,11 +1669,11 @@ enum link_training_result dc_link_dp_sync_lt_attempt(
 	dp_set_panel_mode(link, panel_mode);
 
 	/* Attempt to train with given link training settings */
-	/* Set link rate, lane count and spread. */
 	if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
 		start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
-	else
-		dpcd_set_link_settings(link, &lt_settings);
+
+	/* Set link rate, lane count and spread. */
+	dpcd_set_link_settings(link, &lt_settings);
 
 	/* 2. perform link training (set link training done
 	 *  to false is done as well)