Commit 8361cd79 authored by Olaf Hering's avatar Olaf Hering Committed by Jeff Garzik

add delay around sl82c105_reset_engine calls

The hald media changed polling does really confuse things.
Noone knows why the delays are needed, but they give us access to the CD.

An udelay(50) will give reliable access to the drive, but there is still
one (or more) EH reset. The drive works without EH resets with udelay(100).
Signed-off-by: default avatarOlaf Hering <olaf@aepfle.de>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent 9f271d57
...@@ -187,7 +187,9 @@ static void sl82c105_bmdma_start(struct ata_queued_cmd *qc) ...@@ -187,7 +187,9 @@ static void sl82c105_bmdma_start(struct ata_queued_cmd *qc)
{ {
struct ata_port *ap = qc->ap; struct ata_port *ap = qc->ap;
udelay(100);
sl82c105_reset_engine(ap); sl82c105_reset_engine(ap);
udelay(100);
/* Set the clocks for DMA */ /* Set the clocks for DMA */
sl82c105_configure_dmamode(ap, qc->dev); sl82c105_configure_dmamode(ap, qc->dev);
...@@ -216,6 +218,7 @@ static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc) ...@@ -216,6 +218,7 @@ static void sl82c105_bmdma_stop(struct ata_queued_cmd *qc)
ata_bmdma_stop(qc); ata_bmdma_stop(qc);
sl82c105_reset_engine(ap); sl82c105_reset_engine(ap);
udelay(100);
/* This will redo the initial setup of the DMA device to matching /* This will redo the initial setup of the DMA device to matching
PIO timings */ PIO timings */
......
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