Commit 84872dc4 authored by Erwan Le Ray's avatar Erwan Le Ray Committed by Greg Kroah-Hartman

serial: stm32: add RX and TX FIFO flush

Adds a flush of RX and TX FIFOs, and fixes some errors:
- adds RX FIFO flush in startup fonction
- removes the useless transmitter enabling in startup fonction
  (e.g. receiver only, see Documentation/serial/driver)
- configures FIFO threshold before enabling it, rather than after
- flushes both TX and RX in set_termios function
Signed-off-by: default avatarErwan Le Ray <erwan.leray@st.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent d0a6a7bc
...@@ -599,11 +599,11 @@ static int stm32_startup(struct uart_port *port) ...@@ -599,11 +599,11 @@ static int stm32_startup(struct uart_port *port)
if (ret) if (ret)
return ret; return ret;
val = stm32_port->cr1_irq | USART_CR1_TE | USART_CR1_RE; /* RX FIFO Flush */
if (stm32_port->fifoen) if (ofs->rqr != UNDEF_REG)
val |= USART_CR1_FIFOEN; stm32_set_bits(port, ofs->rqr, USART_RQR_RXFRQ);
stm32_set_bits(port, ofs->cr1, val);
/* Tx and RX FIFO configuration */
if (stm32_port->fifoen) { if (stm32_port->fifoen) {
val = readl_relaxed(port->membase + ofs->cr3); val = readl_relaxed(port->membase + ofs->cr3);
val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK); val &= ~(USART_CR3_TXFTCFG_MASK | USART_CR3_RXFTCFG_MASK);
...@@ -612,6 +612,12 @@ static int stm32_startup(struct uart_port *port) ...@@ -612,6 +612,12 @@ static int stm32_startup(struct uart_port *port)
writel_relaxed(val, port->membase + ofs->cr3); writel_relaxed(val, port->membase + ofs->cr3);
} }
/* RX FIFO enabling */
val = stm32_port->cr1_irq | USART_CR1_RE;
if (stm32_port->fifoen)
val |= USART_CR1_FIFOEN;
stm32_set_bits(port, ofs->cr1, val);
return 0; return 0;
} }
...@@ -694,8 +700,12 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios, ...@@ -694,8 +700,12 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
/* Stop serial port and reset value */ /* Stop serial port and reset value */
writel_relaxed(0, port->membase + ofs->cr1); writel_relaxed(0, port->membase + ofs->cr1);
cr1 = USART_CR1_TE | USART_CR1_RE; /* flush RX & TX FIFO */
if (ofs->rqr != UNDEF_REG)
stm32_set_bits(port, ofs->rqr,
USART_RQR_TXFRQ | USART_RQR_RXFRQ);
cr1 = USART_CR1_TE | USART_CR1_RE;
if (stm32_port->fifoen) if (stm32_port->fifoen)
cr1 |= USART_CR1_FIFOEN; cr1 |= USART_CR1_FIFOEN;
cr2 = 0; cr2 = 0;
......
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