Commit 84ad2e1b authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher

drm/amdgpu: add picasso support for sdma_v4

Add sdma support to picasso
Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 501a580a
...@@ -48,6 +48,7 @@ MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin"); ...@@ -48,6 +48,7 @@ MODULE_FIRMWARE("amdgpu/vega12_sdma1.bin");
MODULE_FIRMWARE("amdgpu/vega20_sdma.bin"); MODULE_FIRMWARE("amdgpu/vega20_sdma.bin");
MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin"); MODULE_FIRMWARE("amdgpu/vega20_sdma1.bin");
MODULE_FIRMWARE("amdgpu/raven_sdma.bin"); MODULE_FIRMWARE("amdgpu/raven_sdma.bin");
MODULE_FIRMWARE("amdgpu/picasso_sdma.bin");
#define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L #define SDMA0_POWER_CNTL__ON_OFF_CONDITION_HOLD_TIME_MASK 0x000000F8L
#define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L #define SDMA0_POWER_CNTL__ON_OFF_STATUS_DURATION_TIME_MASK 0xFC000000L
...@@ -221,6 +222,7 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) ...@@ -221,6 +222,7 @@ static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev)
ARRAY_SIZE(golden_settings_sdma1_4_2)); ARRAY_SIZE(golden_settings_sdma1_4_2));
break; break;
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
soc15_program_register_sequence(adev, soc15_program_register_sequence(adev,
golden_settings_sdma_4_1, golden_settings_sdma_4_1,
ARRAY_SIZE(golden_settings_sdma_4_1)); ARRAY_SIZE(golden_settings_sdma_4_1));
...@@ -269,6 +271,9 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev) ...@@ -269,6 +271,9 @@ static int sdma_v4_0_init_microcode(struct amdgpu_device *adev)
case CHIP_RAVEN: case CHIP_RAVEN:
chip_name = "raven"; chip_name = "raven";
break; break;
case CHIP_PICASSO:
chip_name = "picasso";
break;
default: default:
BUG(); BUG();
} }
...@@ -849,6 +854,7 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev) ...@@ -849,6 +854,7 @@ static void sdma_v4_0_init_pg(struct amdgpu_device *adev)
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
sdma_v4_1_init_power_gating(adev); sdma_v4_1_init_power_gating(adev);
sdma_v4_1_update_power_gating(adev, true); sdma_v4_1_update_power_gating(adev, true);
break; break;
...@@ -1256,7 +1262,7 @@ static int sdma_v4_0_early_init(void *handle) ...@@ -1256,7 +1262,7 @@ static int sdma_v4_0_early_init(void *handle)
{ {
struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_device *adev = (struct amdgpu_device *)handle;
if (adev->asic_type == CHIP_RAVEN) if (adev->asic_type == CHIP_RAVEN || adev->asic_type == CHIP_PICASSO)
adev->sdma.num_instances = 1; adev->sdma.num_instances = 1;
else else
adev->sdma.num_instances = 2; adev->sdma.num_instances = 2;
...@@ -1599,6 +1605,7 @@ static int sdma_v4_0_set_clockgating_state(void *handle, ...@@ -1599,6 +1605,7 @@ static int sdma_v4_0_set_clockgating_state(void *handle,
case CHIP_VEGA12: case CHIP_VEGA12:
case CHIP_VEGA20: case CHIP_VEGA20:
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
sdma_v4_0_update_medium_grain_clock_gating(adev, sdma_v4_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE ? true : false); state == AMD_CG_STATE_GATE ? true : false);
sdma_v4_0_update_medium_grain_light_sleep(adev, sdma_v4_0_update_medium_grain_light_sleep(adev,
...@@ -1617,6 +1624,7 @@ static int sdma_v4_0_set_powergating_state(void *handle, ...@@ -1617,6 +1624,7 @@ static int sdma_v4_0_set_powergating_state(void *handle,
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_RAVEN: case CHIP_RAVEN:
case CHIP_PICASSO:
sdma_v4_1_update_power_gating(adev, sdma_v4_1_update_power_gating(adev,
state == AMD_PG_STATE_GATE ? true : false); state == AMD_PG_STATE_GATE ? true : false);
break; break;
......
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