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Commit 84e0f1c1 authored by Igal Liberman's avatar Igal Liberman Committed by Scott Wood
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powerpc/mpc85xx: Add MDIO bus muxing support to the board device tree(s) 

Describe the PHY topology for all configurations supported by each board

Based on prior work by Andy Fleming <afleming@freescale.com>
Signed-off-by: default avatarShruti Kanetkar <Shruti@freescale.com>
Signed-off-by: default avatarEmil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: default avatarIgal Liberman <Igal.Liberman@freescale.com>
Signed-off-by: default avatarScott Wood <oss@buserror.net>
parent 334479d1
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Showing with 2198 additions and 19 deletions
arch/powerpc/boot/dts/fsl/b4860qds.dts
View file @ 84e0f1c1
/* /*
* B4860DS Device Tree Source * B4860DS Device Tree Source
* *
* Copyright 2012 Freescale Semiconductor Inc. * Copyright 2012 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -39,12 +39,69 @@ / { ...@@ -39,12 +39,69 @@ / {
model = "fsl,B4860QDS"; model = "fsl,B4860QDS";
compatible = "fsl,B4860QDS"; compatible = "fsl,B4860QDS";
aliases {
phy_sgmii_1e = &phy_sgmii_1e;
phy_sgmii_1f = &phy_sgmii_1f;
phy_xaui_slot1 = &phy_xaui_slot1;
phy_xaui_slot2 = &phy_xaui_slot2;
};
ifc: localbus@ffe124000 { ifc: localbus@ffe124000 {
board-control@3,0 { board-control@3,0 {
compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis"; compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
}; };
}; };
soc@ffe000000 {
fman@400000 {
ethernet@e8000 {
phy-handle = <&phy_sgmii_1e>;
phy-connection-type = "sgmii";
};
ethernet@ea000 {
phy-handle = <&phy_sgmii_1f>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xaui_slot1>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&phy_xaui_slot2>;
phy-connection-type = "xgmii";
};
mdio@fc000 {
phy_sgmii_1e: ethernet-phy@1e {
reg = <0x1e>;
status = "disabled";
};
phy_sgmii_1f: ethernet-phy@1f {
reg = <0x1f>;
status = "disabled";
};
};
mdio@fd000 {
phy_xaui_slot1: xaui-phy@slot1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x7>;
status = "disabled";
};
phy_xaui_slot2: xaui-phy@slot2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x6>;
status = "disabled";
};
};
};
};
rio: rapidio@ffe0c0000 { rio: rapidio@ffe0c0000 {
reg = <0xf 0xfe0c0000 0 0x11000>; reg = <0xf 0xfe0c0000 0 0x11000>;
...@@ -55,7 +112,6 @@ port2 { ...@@ -55,7 +112,6 @@ port2 {
ranges = <0 0 0xc 0x30000000 0 0x10000000>; ranges = <0 0 0xc 0x30000000 0 0x10000000>;
}; };
}; };
}; };
/include/ "b4860si-post.dtsi" /include/ "b4860si-post.dtsi"
arch/powerpc/boot/dts/fsl/b4qds.dtsi
View file @ 84e0f1c1
/* /*
* B4420DS Device Tree Source * B4420DS Device Tree Source
* *
* Copyright 2012 - 2014 Freescale Semiconductor, Inc. * Copyright 2012 - 2015 Freescale Semiconductor, Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -39,6 +39,13 @@ / { ...@@ -39,6 +39,13 @@ / {
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases {
phy_sgmii_10 = &phy_sgmii_10;
phy_sgmii_11 = &phy_sgmii_11;
phy_sgmii_1c = &phy_sgmii_1c;
phy_sgmii_1d = &phy_sgmii_1d;
};
ifc: localbus@ffe124000 { ifc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x2000>; reg = <0xf 0xfe124000 0 0x2000>;
ranges = <0 0 0xf 0xe8000000 0x08000000 ranges = <0 0 0xf 0xe8000000 0x08000000
...@@ -210,6 +217,47 @@ usb@210000 { ...@@ -210,6 +217,47 @@ usb@210000 {
phy_type = "ulpi"; phy_type = "ulpi";
}; };
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy_sgmii_10>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_11>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_1c>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy_sgmii_1d>;
phy-connection-type = "sgmii";
};
mdio@fc000 {
phy_sgmii_10: ethernet-phy@10 {
reg = <0x10>;
};
phy_sgmii_11: ethernet-phy@11 {
reg = <0x11>;
};
phy_sgmii_1c: ethernet-phy@1c {
reg = <0x1c>;
status = "disabled";
};
phy_sgmii_1d: ethernet-phy@1d {
reg = <0x1d>;
status = "disabled";
};
};
};
}; };
pci0: pcie@ffe200000 { pci0: pcie@ffe200000 {
...@@ -226,7 +274,6 @@ pcie@0 { ...@@ -226,7 +274,6 @@ pcie@0 {
0 0x00010000>; 0 0x00010000>;
}; };
}; };
}; };
/include/ "b4si-post.dtsi" /include/ "b4si-post.dtsi"
arch/powerpc/boot/dts/fsl/p2041rdb.dts
View file @ 84e0f1c1
/* /*
* P2041RDB Device Tree Source * P2041RDB Device Tree Source
* *
* Copyright 2011 - 2014 Freescale Semiconductor Inc. * Copyright 2011 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -41,6 +41,19 @@ / { ...@@ -41,6 +41,19 @@ / {
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases {
phy_rgmii_0 = &phy_rgmii_0;
phy_rgmii_1 = &phy_rgmii_1;
phy_sgmii_2 = &phy_sgmii_2;
phy_sgmii_3 = &phy_sgmii_3;
phy_sgmii_4 = &phy_sgmii_4;
phy_sgmii_1c = &phy_sgmii_1c;
phy_sgmii_1d = &phy_sgmii_1d;
phy_sgmii_1e = &phy_sgmii_1e;
phy_sgmii_1f = &phy_sgmii_1f;
phy_xgmii_2 = &phy_xgmii_2;
};
memory { memory {
device_type = "memory"; device_type = "memory";
}; };
...@@ -137,6 +150,83 @@ eeprom@50 { ...@@ -137,6 +150,83 @@ eeprom@50 {
usb1: usb@211000 { usb1: usb@211000 {
dr_mode = "host"; dr_mode = "host";
}; };
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy_sgmii_2>;
phy-connection-type = "sgmii";
};
mdio@e1120 {
phy_rgmii_0: ethernet-phy@0 {
reg = <0x0>;
};
phy_rgmii_1: ethernet-phy@1 {
reg = <0x1>;
};
phy_sgmii_2: ethernet-phy@2 {
reg = <0x2>;
};
phy_sgmii_3: ethernet-phy@3 {
reg = <0x3>;
};
phy_sgmii_4: ethernet-phy@4 {
reg = <0x4>;
};
phy_sgmii_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_3>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_4>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_0>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_2>;
phy-connection-type = "xgmii";
};
mdio@f1000 {
phy_xgmii_2: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
};
}; };
rio: rapidio@ffe0c0000 { rio: rapidio@ffe0c0000 {
......
arch/powerpc/boot/dts/fsl/p3041ds.dts
View file @ 84e0f1c1
/* /*
* P3041DS Device Tree Source * P3041DS Device Tree Source
* *
* Copyright 2010 - 2014 Freescale Semiconductor Inc. * Copyright 2010 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -41,6 +41,20 @@ / { ...@@ -41,6 +41,20 @@ / {
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases{
phy_rgmii_0 = &phy_rgmii_0;
phy_rgmii_1 = &phy_rgmii_1;
phy_sgmii_1c = &phy_sgmii_1c;
phy_sgmii_1d = &phy_sgmii_1d;
phy_sgmii_1e = &phy_sgmii_1e;
phy_sgmii_1f = &phy_sgmii_1f;
phy_xgmii_1 = &phy_xgmii_1;
phy_xgmii_2 = &phy_xgmii_2;
emi1_rgmii = &hydra_mdio_rgmii;
emi1_sgmii = &hydra_mdio_sgmii;
emi2_xgmii = &hydra_mdio_xgmii;
};
memory { memory {
device_type = "memory"; device_type = "memory";
}; };
...@@ -150,6 +164,52 @@ adt7461@4c { ...@@ -150,6 +164,52 @@ adt7461@4c {
reg = <0x4c>; reg = <0x4c>;
}; };
}; };
fman@400000{
ethernet@e0000 {
phy-handle = <&phy_sgmii_1c>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_1d>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_1e>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy_sgmii_1f>;
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_1>;
phy-connection-type = "xgmii";
};
hydra_mdio_xgmii: mdio@f1000 {
status = "disabled";
phy_xgmii_1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x4>;
};
phy_xgmii_2: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
};
}; };
rio: rapidio@ffe0c0000 { rio: rapidio@ffe0c0000 {
...@@ -215,8 +275,58 @@ partition@1f000000 { ...@@ -215,8 +275,58 @@ partition@1f000000 {
}; };
board-control@3,0 { board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis"; compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x30>; reg = <3 0 0x30>;
ranges = <0 3 0 0x30>;
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
reg = <9 1>;
mux-mask = <0x78>;
hydra_mdio_rgmii: rgmii-mdio@8 {
#address-cells = <1>;
#size-cells = <0>;
reg = <8>;
status = "disabled";
phy_rgmii_0: ethernet-phy@0 {
reg = <0x0>;
};
phy_rgmii_1: ethernet-phy@1 {
reg = <0x1>;
};
};
hydra_mdio_sgmii: sgmii-mdio@28 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x28>;
status = "disabled";
phy_sgmii_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
}; };
}; };
......
arch/powerpc/boot/dts/fsl/p4080ds.dts
View file @ 84e0f1c1
/* /*
* P4080DS Device Tree Source * P4080DS Device Tree Source
* *
* Copyright 2009 - 2014 Freescale Semiconductor Inc. * Copyright 2009 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -41,6 +41,20 @@ / { ...@@ -41,6 +41,20 @@ / {
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases {
phy_rgmii = &phyrgmii;
phy5_slot3 = &phy5slot3;
phy6_slot3 = &phy6slot3;
phy7_slot3 = &phy7slot3;
phy8_slot3 = &phy8slot3;
emi1_slot3 = &p4080mdio2;
emi1_slot4 = &p4080mdio1;
emi1_slot5 = &p4080mdio3;
emi1_rgmii = &p4080mdio0;
emi2_slot4 = &p4080xmdio1;
emi2_slot5 = &p4080xmdio3;
};
memory { memory {
device_type = "memory"; device_type = "memory";
}; };
...@@ -137,6 +151,60 @@ usb1: usb@211000 { ...@@ -137,6 +151,60 @@ usb1: usb@211000 {
dr_mode = "host"; dr_mode = "host";
phy_type = "ulpi"; phy_type = "ulpi";
}; };
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy0>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy1>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy2>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy3>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&phy10>;
phy-connection-type = "xgmii";
};
};
fman@500000 {
ethernet@e0000 {
phy-handle = <&phy5>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy6>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy7>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy8>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&phy11>;
phy-connection-type = "xgmii";
};
};
}; };
rio: rapidio@ffe0c0000 { rio: rapidio@ffe0c0000 {
...@@ -213,6 +281,120 @@ pcie@0 { ...@@ -213,6 +281,120 @@ pcie@0 {
}; };
}; };
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-gpio", "mdio-mux";
mdio-parent-bus = <&mdio0>;
gpios = <&gpio0 1 0>, <&gpio0 0 0>;
p4080mdio0: mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
phyrgmii: ethernet-phy@0 {
reg = <0x0>;
};
};
p4080mdio1: mdio@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
phy5: ethernet-phy@1c {
reg = <0x1c>;
};
phy6: ethernet-phy@1d {
reg = <0x1d>;
};
phy7: ethernet-phy@1e {
reg = <0x1e>;
};
phy8: ethernet-phy@1f {
reg = <0x1f>;
};
};
p4080mdio2: mdio@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "disabled";
phy5slot3: ethernet-phy@1c {
reg = <0x1c>;
};
phy6slot3: ethernet-phy@1d {
reg = <0x1d>;
};
phy7slot3: ethernet-phy@1e {
reg = <0x1e>;
};
phy8slot3: ethernet-phy@1f {
reg = <0x1f>;
};
};
p4080mdio3: mdio@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
phy0: ethernet-phy@1c {
reg = <0x1c>;
};
phy1: ethernet-phy@1d {
reg = <0x1d>;
};
phy2: ethernet-phy@1e {
reg = <0x1e>;
};
phy3: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
mdio-mux-emi2 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-gpio", "mdio-mux";
mdio-parent-bus = <&xmdio0>;
gpios = <&gpio0 3 0>, <&gpio0 2 0>;
p4080xmdio1: mdio@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
phy11: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
p4080xmdio3: mdio@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
phy10: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x4>;
};
};
};
}; };
/include/ "p4080si-post.dtsi" /include/ "p4080si-post.dtsi"
arch/powerpc/boot/dts/fsl/p5020ds.dts
View file @ 84e0f1c1
/* /*
* P5020DS Device Tree Source * P5020DS Device Tree Source
* *
* Copyright 2010 - 2014 Freescale Semiconductor Inc. * Copyright 2010 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -41,6 +41,20 @@ / { ...@@ -41,6 +41,20 @@ / {
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases {
phy_rgmii_0 = &phy_rgmii_0;
phy_rgmii_1 = &phy_rgmii_1;
phy_sgmii_1c = &phy_sgmii_1c;
phy_sgmii_1d = &phy_sgmii_1d;
phy_sgmii_1e = &phy_sgmii_1e;
phy_sgmii_1f = &phy_sgmii_1f;
phy_xgmii_1 = &phy_xgmii_1;
phy_xgmii_2 = &phy_xgmii_2;
emi1_rgmii = &hydra_mdio_rgmii;
emi1_sgmii = &hydra_mdio_sgmii;
emi2_xgmii = &hydra_mdio_xgmii;
};
memory { memory {
device_type = "memory"; device_type = "memory";
}; };
...@@ -150,6 +164,52 @@ adt7461@4c { ...@@ -150,6 +164,52 @@ adt7461@4c {
reg = <0x4c>; reg = <0x4c>;
}; };
}; };
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy_sgmii_1c>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_1d>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_1e>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy_sgmii_1f>;
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_1>;
phy-connection-type = "xgmii";
};
hydra_mdio_xgmii: mdio@f1000 {
status = "disabled";
phy_xgmii_1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x4>;
};
phy_xgmii_2: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
};
}; };
rio: rapidio@ffe0c0000 { rio: rapidio@ffe0c0000 {
...@@ -215,8 +275,58 @@ partition@1f000000 { ...@@ -215,8 +275,58 @@ partition@1f000000 {
}; };
board-control@3,0 { board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis"; compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x30>; reg = <3 0 0x30>;
ranges = <0 3 0 0x30>;
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
reg = <9 1>;
mux-mask = <0x78>;
hydra_mdio_rgmii: rgmii-mdio@8 {
#address-cells = <1>;
#size-cells = <0>;
reg = <8>;
status = "disabled";
phy_rgmii_0: ethernet-phy@0 {
reg = <0x0>;
};
phy_rgmii_1: ethernet-phy@1 {
reg = <0x1>;
};
};
hydra_mdio_sgmii: sgmii-mdio@28 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x28>;
status = "disabled";
phy_sgmii_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
}; };
}; };
......
arch/powerpc/boot/dts/fsl/p5040ds.dts
View file @ 84e0f1c1
/* /*
* P5040DS Device Tree Source * P5040DS Device Tree Source
* *
* Copyright 2012 - 2014 Freescale Semiconductor Inc. * Copyright 2012 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -41,6 +41,32 @@ / { ...@@ -41,6 +41,32 @@ / {
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases{
phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c;
phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d;
phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e;
phy_sgmii_slot2_1f = &phy_sgmii_slot2_1f;
phy_sgmii_slot3_1c = &phy_sgmii_slot3_1c;
phy_sgmii_slot3_1d = &phy_sgmii_slot3_1d;
phy_sgmii_slot3_1e = &phy_sgmii_slot3_1e;
phy_sgmii_slot3_1f = &phy_sgmii_slot3_1f;
phy_sgmii_slot5_1c = &phy_sgmii_slot5_1c;
phy_sgmii_slot5_1d = &phy_sgmii_slot5_1d;
phy_sgmii_slot5_1e = &phy_sgmii_slot5_1e;
phy_sgmii_slot5_1f = &phy_sgmii_slot5_1f;
phy_sgmii_slot6_1c = &phy_sgmii_slot6_1c;
phy_sgmii_slot6_1d = &phy_sgmii_slot6_1d;
phy_sgmii_slot6_1e = &phy_sgmii_slot6_1e;
phy_sgmii_slot6_1f = &phy_sgmii_slot6_1f;
hydra_rg = &hydra_rg;
hydra_sg_slot2 = &hydra_sg_slot2;
hydra_sg_slot3 = &hydra_sg_slot3;
hydra_sg_slot5 = &hydra_sg_slot5;
hydra_sg_slot6 = &hydra_sg_slot6;
hydra_xg_slot1 = &hydra_xg_slot1;
hydra_xg_slot2 = &hydra_xg_slot2;
};
memory { memory {
device_type = "memory"; device_type = "memory";
}; };
...@@ -147,6 +173,62 @@ adt7461@4c { ...@@ -147,6 +173,62 @@ adt7461@4c {
reg = <0x4c>; reg = <0x4c>;
}; };
}; };
fman@400000 {
ethernet@e0000 {
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_0>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_slot_2>;
phy-connection-type = "xgmii";
};
};
fman@500000 {
ethernet@e0000 {
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_slot_1>;
phy-connection-type = "xgmii";
};
};
}; };
lbc: localbus@ffe124000 { lbc: localbus@ffe124000 {
...@@ -200,8 +282,158 @@ partition@1f000000 { ...@@ -200,8 +282,158 @@ partition@1f000000 {
}; };
board-control@3,0 { board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis"; compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x40>; reg = <3 0 0x40>;
ranges = <0 3 0 0x40>;
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
reg = <9 1>;
mux-mask = <0x78>;
hydra_rg:rgmii-mdio@8 {
#address-cells = <1>;
#size-cells = <0>;
reg = <8>;
status = "disabled";
phy_rgmii_0: ethernet-phy@0 {
reg = <0x0>;
};
phy_rgmii_1: ethernet-phy@1 {
reg = <0x1>;
};
};
hydra_sg_slot2: sgmii-mdio@28 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x28>;
status = "disabled";
phy_sgmii_slot2_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_slot2_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_slot2_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_slot2_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
hydra_sg_slot3: sgmii-mdio@68 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x68>;
status = "disabled";
phy_sgmii_slot3_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_slot3_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_slot3_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_slot3_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
hydra_sg_slot5: sgmii-mdio@38 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x38>;
status = "disabled";
phy_sgmii_slot5_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_slot5_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_slot5_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_slot5_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
hydra_sg_slot6: sgmii-mdio@48 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x48>;
status = "disabled";
phy_sgmii_slot6_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_slot6_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_slot6_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_slot6_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
mdio-mux-emi2 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&xmdio0>;
reg = <9 1>;
mux-mask = <0x06>;
hydra_xg_slot1: hydra-xg-slot1@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
phy_xgmii_slot_1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <4>;
};
};
hydra_xg_slot2: hydra-xg-slot2@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
phy_xgmii_slot_2: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
};
};
}; };
}; };
......
arch/powerpc/boot/dts/fsl/t1023rdb.dts
View file @ 84e0f1c1
...@@ -111,6 +111,47 @@ current-sensor@41 { ...@@ -111,6 +111,47 @@ current-sensor@41 {
shunt-resistor = <1000>; shunt-resistor = <1000>;
}; };
}; };
fman@400000 {
fm1mac1: ethernet@e0000 {
phy-handle = <&sgmii_rtk_phy2>;
phy-connection-type = "sgmii";
sleep = <&rcpm 0x80000000>;
};
fm1mac2: ethernet@e2000 {
sleep = <&rcpm 0x40000000>;
};
fm1mac3: ethernet@e4000 {
phy-handle = <&sgmii_aqr_phy3>;
phy-connection-type = "sgmii-2500";
sleep = <&rcpm 0x20000000>;
};
fm1mac4: ethernet@e6000 {
phy-handle = <&rgmii_rtk_phy1>;
phy-connection-type = "rgmii";
sleep = <&rcpm 0x10000000>;
};
mdio0: mdio@fc000 {
rgmii_rtk_phy1: ethernet-phy@1 {
reg = <0x1>;
};
sgmii_rtk_phy2: ethernet-phy@3 {
reg = <0x3>;
};
};
xmdio0: mdio@fd000 {
sgmii_aqr_phy3: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x2>;
};
};
};
}; };
pci0: pcie@ffe240000 { pci0: pcie@ffe240000 {
......
arch/powerpc/boot/dts/fsl/t1024rdb.dts
View file @ 84e0f1c1
...@@ -140,6 +140,51 @@ pca9546@77 { ...@@ -140,6 +140,51 @@ pca9546@77 {
#size-cells = <0>; #size-cells = <0>;
}; };
}; };
fman@400000 {
fm1mac1: ethernet@e0000 {
phy-handle = <&xg_aqr105_phy3>;
phy-connection-type = "xgmii";
sleep = <&rcpm 0x80000000>;
};
fm1mac2: ethernet@e2000 {
sleep = <&rcpm 0x40000000>;
};
fm1mac3: ethernet@e4000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
sleep = <&rcpm 0x20000000>;
};
fm1mac4: ethernet@e6000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
sleep = <&rcpm 0x10000000>;
};
mdio0: mdio@fc000 {
rgmii_phy1: ethernet-phy@2 {
reg = <0x2>;
};
rgmii_phy2: ethernet-phy@6 {
reg = <0x6>;
};
};
xmdio0: mdio@fd000 {
xg_aqr105_phy3: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
sg_2500_aqr105_phy4: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x2>;
};
};
};
}; };
pci0: pcie@ffe240000 { pci0: pcie@ffe240000 {
......
arch/powerpc/boot/dts/fsl/t1040rdb.dts
View file @ 84e0f1c1
/* /*
* T1040RDB Device Tree Source * T1040RDB Device Tree Source
* *
* Copyright 2014 Freescale Semiconductor Inc. * Copyright 2014 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -38,6 +38,36 @@ ...@@ -38,6 +38,36 @@
/ { / {
model = "fsl,T1040RDB"; model = "fsl,T1040RDB";
compatible = "fsl,T1040RDB"; compatible = "fsl,T1040RDB";
aliases {
phy_sgmii_2 = &phy_sgmii_2;
};
soc@ffe000000 {
fman@400000 {
ethernet@e0000 {
fixed-link = <0 1 1000 0 0>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_2>;
phy-connection-type = "sgmii";
};
mdio@fc000 {
phy_sgmii_2: ethernet-phy@03 {
reg = <0x03>;
};
};
};
};
ifc: localbus@ffe124000 { ifc: localbus@ffe124000 {
cpld@3,0 { cpld@3,0 {
compatible = "fsl,t1040rdb-cpld"; compatible = "fsl,t1040rdb-cpld";
......
arch/powerpc/boot/dts/fsl/t1042rdb.dts
View file @ 84e0f1c1
/* /*
* T1042RDB Device Tree Source * T1042RDB Device Tree Source
* *
* Copyright 2014 Freescale Semiconductor Inc. * Copyright 2014 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -38,6 +38,34 @@ ...@@ -38,6 +38,34 @@
/ { / {
model = "fsl,T1042RDB"; model = "fsl,T1042RDB";
compatible = "fsl,T1042RDB"; compatible = "fsl,T1042RDB";
aliases {
phy_sgmii_2 = &phy_sgmii_2;
};
soc@ffe000000 {
fman@400000 {
ethernet@e0000 {
status = "disabled";
};
ethernet@e2000 {
status = "disabled";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_2>;
phy-connection-type = "sgmii";
};
mdio@fc000 {
phy_sgmii_2: ethernet-phy@03 {
reg = <0x03>;
};
};
};
};
ifc: localbus@ffe124000 { ifc: localbus@ffe124000 {
cpld@3,0 { cpld@3,0 {
compatible = "fsl,t1042rdb-cpld"; compatible = "fsl,t1042rdb-cpld";
......
arch/powerpc/boot/dts/fsl/t1042rdb_pi.dts
View file @ 84e0f1c1
/* /*
* T1042RDB_PI Device Tree Source * T1042RDB_PI Device Tree Source
* *
* Copyright 2014 Freescale Semiconductor Inc. * Copyright 2014 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -38,11 +38,13 @@ ...@@ -38,11 +38,13 @@
/ { / {
model = "fsl,T1042RDB_PI"; model = "fsl,T1042RDB_PI";
compatible = "fsl,T1042RDB_PI"; compatible = "fsl,T1042RDB_PI";
ifc: localbus@ffe124000 { ifc: localbus@ffe124000 {
cpld@3,0 { cpld@3,0 {
compatible = "fsl,t1042rdb_pi-cpld"; compatible = "fsl,t1042rdb_pi-cpld";
}; };
}; };
soc: soc@ffe000000 { soc: soc@ffe000000 {
i2c@118000 { i2c@118000 {
rtc@68 { rtc@68 {
...@@ -51,6 +53,20 @@ rtc@68 { ...@@ -51,6 +53,20 @@ rtc@68 {
interrupts = <0x2 0x1 0 0>; interrupts = <0x2 0x1 0 0>;
}; };
}; };
fman@400000 {
ethernet@e0000 {
status = "disabled";
};
ethernet@e2000 {
status = "disabled";
};
ethernet@e4000 {
status = "disabled";
};
};
}; };
}; };
......
arch/powerpc/boot/dts/fsl/t104xqds.dtsi
View file @ 84e0f1c1
/* /*
* T104xQDS Device Tree Source * T104xQDS Device Tree Source
* *
* Copyright 2013 - 2014 Freescale Semiconductor Inc. * Copyright 2013 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -38,6 +38,33 @@ / { ...@@ -38,6 +38,33 @@ / {
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases {
emi1_rgmii0 = &t1040mdio0;
emi1_rgmii1 = &t1040mdio1;
emi1_slot3 = &t1040mdio3;
emi1_slot5 = &t1040mdio5;
emi1_slot6 = &t1040mdio6;
emi1_slot7 = &t1040mdio7;
rgmii_phy1 = &rgmii_phy1;
rgmii_phy2 = &rgmii_phy2;
phy_s3_01 = &phy_s3_01;
phy_s3_02 = &phy_s3_02;
phy_s3_03 = &phy_s3_03;
phy_s3_04 = &phy_s3_04;
phy_s5_01 = &phy_s5_01;
phy_s5_02 = &phy_s5_02;
phy_s5_03 = &phy_s5_03;
phy_s5_04 = &phy_s5_04;
phy_s6_01 = &phy_s6_01;
phy_s6_02 = &phy_s6_02;
phy_s6_03 = &phy_s6_03;
phy_s6_04 = &phy_s6_04;
phy_s7_01 = &phy_s7_01;
phy_s7_02 = &phy_s7_02;
phy_s7_03 = &phy_s7_03;
phy_s7_04 = &phy_s7_04;
};
reserved-memory { reserved-memory {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
...@@ -85,6 +112,128 @@ board-control@3,0 { ...@@ -85,6 +112,128 @@ board-control@3,0 {
#size-cells = <1>; #size-cells = <1>;
compatible = "fsl,fpga-qixis"; compatible = "fsl,fpga-qixis";
reg = <3 0 0x300>; reg = <3 0 0x300>;
ranges = <0 3 0 0x300>;
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
reg = <0x54 1>;
mux-mask = <0xe0>;
t1040mdio0: mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00>;
status = "disabled";
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
};
t1040mdio1: mdio@20 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x20>;
status = "disabled";
rgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
};
t1040mdio3: mdio@60 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x60>;
status = "disabled";
phy_s3_01: ethernet-phy@1c {
reg = <0x1c>;
};
phy_s3_02: ethernet-phy@1d {
reg = <0x1d>;
};
phy_s3_03: ethernet-phy@1e {
reg = <0x1e>;
};
phy_s3_04: ethernet-phy@1f {
reg = <0x1f>;
};
};
t1040mdio5: mdio@a0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xa0>;
phy_s5_01: ethernet-phy@1c {
reg = <0x14>;
};
phy_s5_02: ethernet-phy@1d {
reg = <0x15>;
};
phy_s5_03: ethernet-phy@1e {
reg = <0x16>;
};
phy_s5_04: ethernet-phy@1f {
reg = <0x17>;
};
};
t1040mdio6: mdio@c0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc0>;
phy_s6_01: ethernet-phy@1c {
reg = <0x18>;
};
phy_s6_02: ethernet-phy@1d {
reg = <0x19>;
};
phy_s6_03: ethernet-phy@1e {
reg = <0x1a>;
};
phy_s6_04: ethernet-phy@1f {
reg = <0x1b>;
};
};
t1040mdio7: mdio@e0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xe0>;
status = "disabled";
phy_s7_01: ethernet-phy@1c {
reg = <0x1c>;
};
phy_s7_02: ethernet-phy@1d {
reg = <0x1d>;
};
phy_s7_03: ethernet-phy@1e {
reg = <0x1e>;
};
phy_s7_04: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
}; };
}; };
...@@ -129,6 +278,33 @@ rtc@68 { ...@@ -129,6 +278,33 @@ rtc@68 {
interrupts = <0x1 0x1 0 0>; interrupts = <0x1 0x1 0 0>;
}; };
}; };
fman@400000 {
ethernet@e0000 {
fixed-link = <0 1 1000 0 0>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_s7_03>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
};
};
}; };
pci0: pcie@ffe240000 { pci0: pcie@ffe240000 {
......
arch/powerpc/boot/dts/fsl/t104xrdb.dtsi
View file @ 84e0f1c1
/* /*
* T1040RDB/T1042RDB Device Tree Source * T1040RDB/T1042RDB Device Tree Source
* *
* Copyright 2014 Freescale Semiconductor Inc. * Copyright 2014 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -33,6 +33,12 @@ ...@@ -33,6 +33,12 @@
*/ */
/ { / {
aliases {
phy_rgmii_0 = &phy_rgmii_0;
phy_rgmii_1 = &phy_rgmii_1;
phy_sgmii_2 = &phy_sgmii_2;
};
reserved-memory { reserved-memory {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
...@@ -125,6 +131,31 @@ pca9546@77 { ...@@ -125,6 +131,31 @@ pca9546@77 {
}; };
}; };
fman@400000 {
ethernet@e6000 {
phy-handle = <&phy_rgmii_0>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
mdio0: mdio@fc000 {
phy_sgmii_2: ethernet-phy@03 {
reg = <0x03>;
};
phy_rgmii_0: ethernet-phy@01 {
reg = <0x01>;
};
phy_rgmii_1: ethernet-phy@02 {
reg = <0x02>;
};
};
};
}; };
pci0: pcie@ffe240000 { pci0: pcie@ffe240000 {
......
arch/powerpc/boot/dts/fsl/t2080qds.dts
View file @ 84e0f1c1
/* /*
* T2080QDS Device Tree Source * T2080QDS Device Tree Source
* *
* Copyright 2013 Freescale Semiconductor Inc. * Copyright 2013 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -42,6 +42,12 @@ / { ...@@ -42,6 +42,12 @@ / {
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases {
emi1_slot1 = &t2080mdio2;
emi1_slot2 = &t2080mdio3;
emi1_slot3 = &t2080mdio4;
};
rio: rapidio@ffe0c0000 { rio: rapidio@ffe0c0000 {
reg = <0xf 0xfe0c0000 0 0x11000>; reg = <0xf 0xfe0c0000 0 0x11000>;
...@@ -54,4 +60,154 @@ port2 { ...@@ -54,4 +60,154 @@ port2 {
}; };
}; };
&soc {
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy_sgmii_s3_1e>;
phy-connection-type = "xgmii";
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_s3_1f>;
phy-connection-type = "xgmii";
};
ethernet@e4000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
};
ethernet@e6000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&phy_sgmii_s2_1e>;
phy-connection-type = "sgmii";
};
ethernet@ea000 {
phy-handle = <&phy_sgmii_s2_1d>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xaui_slot3>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&phy_sgmii_s3_1f>;
phy-connection-type = "xgmii";
};
mdio@fd000 {
phy_xaui_slot3: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x3>;
};
};
};
};
&boardctrl {
mdio-mux-emi1 {
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x54 1>;
mux-mask = <0xe0>;
t2080mdio0: mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
};
t2080mdio1: mdio@20 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x20>;
rgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
};
t2080mdio2: mdio@40 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40>;
status = "disabled";
phy_sgmii_s1_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_s1_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_s1_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_s1_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
t2080mdio3: mdio@c0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc0>;
phy_sgmii_s2_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_s2_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_s2_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_s2_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
t2080mdio4: mdio@60 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x60>;
status = "disabled";
phy_sgmii_s3_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_s3_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_s3_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_s3_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
};
/include/ "t2080si-post.dtsi" /include/ "t2080si-post.dtsi"
arch/powerpc/boot/dts/fsl/t2080rdb.dts
View file @ 84e0f1c1
/* /*
* T2080PCIe-RDB Board Device Tree Source * T2080PCIe-RDB Board Device Tree Source
* *
* Copyright 2014 Freescale Semiconductor Inc. * Copyright 2014 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -54,4 +54,69 @@ port2 { ...@@ -54,4 +54,69 @@ port2 {
}; };
}; };
&soc {
fman@400000 {
ethernet@e0000 {
phy-handle = <&xg_aq1202_phy3>;
phy-connection-type = "xgmii";
};
ethernet@e2000 {
phy-handle = <&xg_aq1202_phy4>;
phy-connection-type = "xgmii";
};
ethernet@e4000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
};
ethernet@e6000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&xg_cs4315_phy1>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&xg_cs4315_phy2>;
phy-connection-type = "xgmii";
};
mdio@fc000 {
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
rgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
};
mdio@fd000 {
xg_cs4315_phy1: ethernet-phy@c {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0xc>;
};
xg_cs4315_phy2: ethernet-phy@d {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0xd>;
};
xg_aq1202_phy3: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
xg_aq1202_phy4: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
};
};
};
/include/ "t2080si-post.dtsi" /include/ "t2080si-post.dtsi"
arch/powerpc/boot/dts/fsl/t2081qds.dts
View file @ 84e0f1c1
/* /*
* T2081QDS Device Tree Source * T2081QDS Device Tree Source
* *
* Copyright 2013 Freescale Semiconductor Inc. * Copyright 2013 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -41,6 +41,225 @@ / { ...@@ -41,6 +41,225 @@ / {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases {
emi1_slot1 = &t2081mdio2;
emi1_slot2 = &t2081mdio3;
emi1_slot3 = &t2081mdio4;
emi1_slot5 = &t2081mdio5;
emi1_slot6 = &t2081mdio6;
emi1_slot7 = &t2081mdio7;
};
};
&soc {
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy_sgmii_s7_1c>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_s7_1d>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
};
ethernet@e6000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&phy_sgmii_s3_1c>;
phy-connection-type = "sgmii";
};
ethernet@ea000 {
phy-handle = <&phy_sgmii_s7_1f>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&phy_sgmii_s2_1c>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&phy_sgmii_s7_1e>;
phy-connection-type = "xgmii";
};
};
};
&boardctrl {
mdio-mux-emi1 {
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x54 1>;
mux-mask = <0xe0>;
t2081mdio0: mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};
};
t2081mdio1: mdio@20 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x20>;
rgmii_phy2: ethernet-phy@2 {
reg = <0x2>;
};
};
t2081mdio2: mdio@40 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40>;
phy_sgmii_s1_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_s1_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_s1_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_s1_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
t2081mdio3: mdio@60 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x60>;
phy_sgmii_s2_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_s2_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_s2_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_s2_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
t2081mdio4: mdio@80 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80>;
status = "disabled";
phy_sgmii_s3_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_s3_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_s3_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_s3_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
t2081mdio5: mdio@a0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xa0>;
status = "disabled";
phy_sgmii_s5_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_s5_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_s5_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_s5_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
t2081mdio6: mdio@c0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xc0>;
status = "disabled";
phy_sgmii_s6_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_s6_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_s6_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_s6_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
t2081mdio7: mdio@e0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0xe0>;
phy_sgmii_s7_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_s7_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_s7_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_s7_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
}; };
/include/ "t2081si-post.dtsi" /include/ "t2081si-post.dtsi"
arch/powerpc/boot/dts/fsl/t4240qds.dts
View file @ 84e0f1c1
/* /*
* T4240QDS Device Tree Source * T4240QDS Device Tree Source
* *
* Copyright 2012 - 2014 Freescale Semiconductor Inc. * Copyright 2012 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -41,6 +41,44 @@ / { ...@@ -41,6 +41,44 @@ / {
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases{
phy_rgmii1 = &phyrgmii1;
phy_rgmii2 = &phyrgmii2;
phy_sgmii3 = &phy3;
phy_sgmii4 = &phy4;
phy_sgmii11 = &phy11;
phy_sgmii12 = &phy12;
sgmii_phy11 = &sgmiiphy11;
sgmii_phy12 = &sgmiiphy12;
sgmii_phy13 = &sgmiiphy13;
sgmii_phy14 = &sgmiiphy14;
sgmii_phy21 = &sgmiiphy21;
sgmii_phy22 = &sgmiiphy22;
sgmii_phy23 = &sgmiiphy23;
sgmii_phy24 = &sgmiiphy24;
sgmii_phy31 = &sgmiiphy31;
sgmii_phy32 = &sgmiiphy32;
sgmii_phy33 = &sgmiiphy33;
sgmii_phy34 = &sgmiiphy34;
sgmii_phy41 = &sgmiiphy41;
sgmii_phy42 = &sgmiiphy42;
sgmii_phy43 = &sgmiiphy43;
sgmii_phy44 = &sgmiiphy44;
phy_xfi1 = &xfiphy1;
phy_xfi2 = &xfiphy2;
phy_xfi3 = &xfiphy3;
phy_xfi4 = &xfiphy4;
xfi_pcs_mdio1 = &xfimdio0;
xfi_pcs_mdio2 = &xfimdio1;
xfi_pcs_mdio3 = &xfimdio2;
xfi_pcs_mdio4 = &xfimdio3;
emi1_rgmii = &t4240mdio0;
emi1_slot1 = &t4240mdio1;
emi1_slot2 = &t4240mdio2;
emi1_slot3 = &t4240mdio3;
emi1_slot4 = &t4240mdio4;
};
ifc: localbus@ffe124000 { ifc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x2000>; reg = <0xf 0xfe124000 0 0x2000>;
ranges = <0 0 0xf 0xe8000000 0x08000000 ranges = <0 0 0xf 0xe8000000 0x08000000
...@@ -91,8 +129,190 @@ partition@C00000 { ...@@ -91,8 +129,190 @@ partition@C00000 {
}; };
board-control@3,0 { board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,t4240qds-fpga", "fsl,fpga-qixis"; compatible = "fsl,t4240qds-fpga", "fsl,fpga-qixis";
reg = <3 0 0x300>; reg = <3 0 0x300>;
ranges = <0 3 0 0x300>;
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio1>;
reg = <0x54 1>;
mux-mask = <0xe0>;
t4240mdio0: mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
phyrgmii1: ethernet-phy@1 {
reg = <0x1>;
};
phyrgmii2: ethernet-phy@2 {
reg = <0x2>;
};
};
t4240mdio1: mdio@20 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x20>;
status = "disabled";
phy1: ethernet-phy@0 {
reg = <0x0>;
};
phy2: ethernet-phy@1 {
reg = <0x1>;
};
phy3: ethernet-phy@2 {
reg = <0x2>;
};
phy4: ethernet-phy@3 {
reg = <0x3>;
};
sgmiiphy11: ethernet-phy@1c {
reg = <0x1c>;
};
sgmiiphy12: ethernet-phy@1d {
reg = <0x1d>;
};
sgmiiphy13: ethernet-phy@1e {
reg = <0x1e>;
};
sgmiiphy14: ethernet-phy@1f {
reg = <0x1f>;
};
};
t4240mdio2: mdio@40 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40>;
status = "disabled";
phy5: ethernet-phy@4 {
reg = <0x4>;
};
phy6: ethernet-phy@5 {
reg = <0x5>;
};
phy7: ethernet-phy@6 {
reg = <0x6>;
};
phy8: ethernet-phy@7 {
reg = <0x7>;
};
sgmiiphy21: ethernet-phy@1c {
reg = <0x1c>;
};
sgmiiphy22: ethernet-phy@1d {
reg = <0x1d>;
};
sgmiiphy23: ethernet-phy@1e {
reg = <0x1e>;
};
sgmiiphy24: ethernet-phy@1f {
reg = <0x1f>;
};
};
t4240mdio3: mdio@60 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x60>;
status = "disabled";
phy9: ethernet-phy@8 {
reg = <0x8>;
};
phy10: ethernet-phy@9 {
reg = <0x9>;
};
phy11: ethernet-phy@a {
reg = <0xa>;
};
phy12: ethernet-phy@b {
reg = <0xb>;
};
sgmiiphy31: ethernet-phy@1c {
reg = <0x1c>;
};
sgmiiphy32: ethernet-phy@1d {
reg = <0x1d>;
};
sgmiiphy33: ethernet-phy@1e {
reg = <0x1e>;
};
sgmiiphy34: ethernet-phy@1f {
reg = <0x1f>;
};
};
t4240mdio4: mdio@80 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80>;
status = "disabled";
phy13: ethernet-phy@c {
reg = <0xc>;
};
phy14: ethernet-phy@d {
reg = <0xd>;
};
phy15: ethernet-phy@e {
reg = <0xe>;
};
phy16: ethernet-phy@f {
reg = <0xf>;
};
sgmiiphy41: ethernet-phy@1c {
reg = <0x1c>;
};
sgmiiphy42: ethernet-phy@1d {
reg = <0x1d>;
};
sgmiiphy43: ethernet-phy@1e {
reg = <0x1e>;
};
sgmiiphy44: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
}; };
}; };
...@@ -234,6 +454,184 @@ ina220@47 { ...@@ -234,6 +454,184 @@ ina220@47 {
sdhc@114000 { sdhc@114000 {
voltage-ranges = <1800 1800 3300 3300>; voltage-ranges = <1800 1800 3300 3300>;
}; };
fman@400000 {
port@83000 {
status = "disabled";
};
port@84000 {
status = "disabled";
};
port@85000 {
status = "disabled";
};
port@86000 {
status = "disabled";
};
port@87000 {
status = "disabled";
};
ethernet@e0000 {
phy-handle = <&phy5>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy6>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy7>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy8>;
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phyrgmii2>;
phy-connection-type = "rgmii";
};
ethernet@ea000 {
phy-handle = <&phy2>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&xauiphy1>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&xauiphy2>;
phy-connection-type = "xgmii";
};
xfimdio0: mdio@f1000 {
status = "disabled";
xfiphy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
xfimdio1: mdio@f3000 {
status = "disabled";
xfiphy2: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
};
fman@500000 {
port@84000 {
status = "disabled";
};
port@85000 {
status = "disabled";
};
port@86000 {
status = "disabled";
};
port@87000 {
status = "disabled";
};
ethernet@e0000 {
phy-handle = <&phy13>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy14>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy15>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy16>;
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phyrgmii1>;
phy-connection-type = "rgmii";
};
ethernet@ea000 {
phy-handle = <&phy10>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&xauiphy3>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&xauiphy4>;
phy-connection-type = "xgmii";
};
xfimdio2: mdio@f1000 {
status = "disabled";
xfiphy3: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
xfimdio3: mdio@f3000 {
status = "disabled";
xfiphy4: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
mdio@fd000 {
xauiphy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
xauiphy2: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
xauiphy3: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x2>;
};
xauiphy4: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x3>;
};
};
};
}; };
pci0: pcie@ffe240000 { pci0: pcie@ffe240000 {
......
arch/powerpc/boot/dts/fsl/t4240rdb.dts
View file @ 84e0f1c1
/* /*
* T4240RDB Device Tree Source * T4240RDB Device Tree Source
* *
* Copyright 2014 Freescale Semiconductor Inc. * Copyright 2014 - 2015 Freescale Semiconductor Inc.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -41,6 +41,17 @@ / { ...@@ -41,6 +41,17 @@ / {
#size-cells = <2>; #size-cells = <2>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
aliases {
sgmii_phy21 = &sgmiiphy21;
sgmii_phy22 = &sgmiiphy22;
sgmii_phy23 = &sgmiiphy23;
sgmii_phy24 = &sgmiiphy24;
sgmii_phy41 = &sgmiiphy41;
sgmii_phy42 = &sgmiiphy42;
sgmii_phy43 = &sgmiiphy43;
sgmii_phy44 = &sgmiiphy44;
};
ifc: localbus@ffe124000 { ifc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x2000>; reg = <0xf 0xfe124000 0 0x2000>;
ranges = <0 0 0xf 0xe8000000 0x08000000 ranges = <0 0 0xf 0xe8000000 0x08000000
...@@ -136,6 +147,142 @@ rtc@68 { ...@@ -136,6 +147,142 @@ rtc@68 {
sdhc@114000 { sdhc@114000 {
voltage-ranges = <1800 1800 3300 3300>; voltage-ranges = <1800 1800 3300 3300>;
}; };
fman@400000 {
ethernet@e0000 {
phy-handle = <&sgmiiphy21>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&sgmiiphy22>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&sgmiiphy23>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&sgmiiphy24>;
phy-connection-type = "sgmii";
};
ethernet@e8000 {
status = "disabled";
};
ethernet@ea000 {
status = "disabled";
};
ethernet@f0000 {
phy-handle = <&xfiphy1>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&xfiphy2>;
phy-connection-type = "xgmii";
};
};
fman@500000 {
ethernet@e0000 {
phy-handle = <&sgmiiphy41>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&sgmiiphy42>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&sgmiiphy43>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&sgmiiphy44>;
phy-connection-type = "sgmii";
};
ethernet@e8000 {
status = "disabled";
};
ethernet@ea000 {
status = "disabled";
};
ethernet@f0000 {
phy-handle = <&xfiphy3>;
phy-connection-type = "xgmii";
};
ethernet@f2000 {
phy-handle = <&xfiphy4>;
phy-connection-type = "xgmii";
};
mdio@fc000 {
sgmiiphy21: ethernet-phy@0 {
reg = <0x0>;
};
sgmiiphy22: ethernet-phy@1 {
reg = <0x1>;
};
sgmiiphy23: ethernet-phy@2 {
reg = <0x2>;
};
sgmiiphy24: ethernet-phy@3 {
reg = <0x3>;
};
sgmiiphy41: ethernet-phy@4 {
reg = <0x4>;
};
sgmiiphy42: ethernet-phy@5 {
reg = <0x5>;
};
sgmiiphy43: ethernet-phy@6 {
reg = <0x6>;
};
sgmiiphy44: ethernet-phy@7 {
reg = <0x7>;
};
};
mdio@fd000 {
xfiphy1: ethernet-phy@10 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x10>;
};
xfiphy2: ethernet-phy@11 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x11>;
};
xfiphy3: ethernet-phy@13 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x13>;
};
xfiphy4: ethernet-phy@12 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x12>;
};
};
};
}; };
pci0: pcie@ffe240000 { pci0: pcie@ffe240000 {
......
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