Commit 8614a5e9 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard

ARM: dts: sun8i: r40: Add device node for CSI0

The CSI0 and CSI1 blocks are the same as found on the A20. However only
CSI0 is supported upstream right now.

Add a device node for CSI0 using the A20 compatible as a fallback, and
the standard pinctrl options. Also add the MBUS interconnect.
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
parent 2c247940
......@@ -181,6 +181,20 @@ nmi_intc: interrupt-controller@1c00030 {
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
csi0: csi@1c09000 {
compatible = "allwinner,sun8i-r40-csi0",
"allwinner,sun7i-a20-csi0";
reg = <0x01c09000 0x1000>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_BUS_CSI0>, <&ccu CLK_CSI_SCLK>,
<&ccu CLK_DRAM_CSI0>;
clock-names = "bus", "isp", "ram";
resets = <&ccu RST_BUS_CSI0>;
interconnects = <&mbus 5>;
interconnect-names = "dma-mem";
status = "disabled";
};
mmc0: mmc@1c0f000 {
compatible = "allwinner,sun8i-r40-mmc",
"allwinner,sun50i-a64-mmc";
......@@ -356,6 +370,20 @@ clk_out_a_pin: clk-out-a-pin {
function = "clk_out_a";
};
/omit-if-no-ref/
csi0_8bits_pins: csi0-8bits-pins {
pins = "PE0", "PE2", "PE3", "PE4", "PE5",
"PE6", "PE7", "PE8", "PE9", "PE10",
"PE11";
function = "csi0";
};
/omit-if-no-ref/
csi0_mclk_pin: csi0-mclk-pin {
pins = "PE1";
function = "csi0";
};
gmac_rgmii_pins: gmac-rgmii-pins {
pins = "PA0", "PA1", "PA2", "PA3",
"PA4", "PA5", "PA6", "PA7",
......@@ -625,6 +653,14 @@ gmac_mdio: mdio {
};
};
mbus: dram-controller@1c62000 {
compatible = "allwinner,sun8i-r40-mbus";
reg = <0x01c62000 0x1000>;
clocks = <&ccu 155>;
dma-ranges = <0x00000000 0x40000000 0x80000000>;
#interconnect-cells = <1>;
};
tcon_top: tcon-top@1c70000 {
compatible = "allwinner,sun8i-r40-tcon-top";
reg = <0x01c70000 0x1000>;
......
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