Commit 86d8c07f authored by Sascha Hauer's avatar Sascha Hauer Committed by David S. Miller

net/davinci: do not use all descriptors for tx packets

The driver uses a shared pool for both rx and tx descriptors.
During open it queues fixed number of 128 descriptors for receive
packets. For each received packet it tries to queue another
descriptor. If this fails the descriptor is lost for rx.
The driver has no limitation on tx descriptors to use, so it
can happen during a nmap / ping -f attack that the driver
allocates all descriptors for tx and looses all rx descriptors.
The driver stops working then.
To fix this limit the number of tx descriptors used to half of
the descriptors available, the rx path uses the other half.

Tested on a custom board using nmap / ping -f to the board from
two different hosts.
Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent fa0f5aa7
...@@ -115,6 +115,7 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1"; ...@@ -115,6 +115,7 @@ static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1";
#define EMAC_DEF_TX_CH (0) /* Default 0th channel */ #define EMAC_DEF_TX_CH (0) /* Default 0th channel */
#define EMAC_DEF_RX_CH (0) /* Default 0th channel */ #define EMAC_DEF_RX_CH (0) /* Default 0th channel */
#define EMAC_DEF_RX_NUM_DESC (128) #define EMAC_DEF_RX_NUM_DESC (128)
#define EMAC_DEF_TX_NUM_DESC (128)
#define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */
#define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */
#define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */
...@@ -336,6 +337,7 @@ struct emac_priv { ...@@ -336,6 +337,7 @@ struct emac_priv {
u32 mac_hash2; u32 mac_hash2;
u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
u32 rx_addr_type; u32 rx_addr_type;
atomic_t cur_tx;
const char *phy_id; const char *phy_id;
struct phy_device *phydev; struct phy_device *phydev;
spinlock_t lock; spinlock_t lock;
...@@ -1044,6 +1046,9 @@ static void emac_tx_handler(void *token, int len, int status) ...@@ -1044,6 +1046,9 @@ static void emac_tx_handler(void *token, int len, int status)
{ {
struct sk_buff *skb = token; struct sk_buff *skb = token;
struct net_device *ndev = skb->dev; struct net_device *ndev = skb->dev;
struct emac_priv *priv = netdev_priv(ndev);
atomic_dec(&priv->cur_tx);
if (unlikely(netif_queue_stopped(ndev))) if (unlikely(netif_queue_stopped(ndev)))
netif_start_queue(ndev); netif_start_queue(ndev);
...@@ -1092,6 +1097,9 @@ static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev) ...@@ -1092,6 +1097,9 @@ static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev)
goto fail_tx; goto fail_tx;
} }
if (atomic_inc_return(&priv->cur_tx) >= EMAC_DEF_TX_NUM_DESC)
netif_stop_queue(ndev);
return NETDEV_TX_OK; return NETDEV_TX_OK;
fail_tx: fail_tx:
......
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