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Commit 8788e066 authored by Wenjing Liu's avatar Wenjing Liu Committed by Alex Deucher
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drm/amd/display: add set dp lane settings to link_hwss 

[why]
Factor set dp lane settings to link_hwss.

v2: fix statement with no effect warning (Alex)
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarJun Lei <Jun.Lei@amd.com>
Acked-by: default avatarStylon Wang <stylon.wang@amd.com>
Signed-off-by: default avatarWenjing Liu <wenjing.liu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b9d3d50a
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Inline Side-by-side
Showing with 59 additions and 32 deletions
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
View file @ 8788e066
...@@ -295,22 +295,16 @@ void dp_set_hw_lane_settings( ...@@ -295,22 +295,16 @@ void dp_set_hw_lane_settings(
const struct link_training_settings *link_settings, const struct link_training_settings *link_settings,
uint32_t offset) uint32_t offset)
{ {
struct link_encoder *encoder = link->link_enc; const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && !is_immediate_downstream(link, offset)) if ((link->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && !is_immediate_downstream(link, offset))
return; return;
/* call Encoder to set lane settings */ if (link_hwss->ext.set_dp_lane_settings)
if (dp_get_link_encoding_format(&link_settings->link_settings) == link_hwss->ext.set_dp_lane_settings(link, link_res,
DP_128b_132b_ENCODING) {
link_res->hpo_dp_link_enc->funcs->set_ffe(
link_res->hpo_dp_link_enc,
&link_settings->link_settings, &link_settings->link_settings,
link_settings->lane_settings[0].FFE_PRESET.raw); link_settings->hw_lane_settings);
} else if (dp_get_link_encoding_format(&link_settings->link_settings)
== DP_8b_10b_ENCODING) {
encoder->funcs->dp_set_lane_settings(encoder, link_settings);
}
memmove(link->cur_lane_setting, memmove(link->cur_lane_setting,
link_settings->lane_settings, link_settings->lane_settings,
sizeof(link->cur_lane_setting)); sizeof(link->cur_lane_setting));
...@@ -748,6 +742,16 @@ static void set_dio_dp_link_test_pattern(struct dc_link *link, ...@@ -748,6 +742,16 @@ static void set_dio_dp_link_test_pattern(struct dc_link *link,
dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN); dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);
} }
static void set_dio_dp_lane_settings(struct dc_link *link,
const struct link_resource *link_res,
const struct dc_link_settings *link_settings,
const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
{
struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link);
link_enc->funcs->dp_set_lane_settings(link_enc, link_settings, lane_settings);
}
static const struct link_hwss dio_link_hwss = { static const struct link_hwss dio_link_hwss = {
.setup_stream_encoder = setup_dio_stream_encoder, .setup_stream_encoder = setup_dio_stream_encoder,
.reset_stream_encoder = reset_dio_stream_encoder, .reset_stream_encoder = reset_dio_stream_encoder,
...@@ -756,6 +760,7 @@ static const struct link_hwss dio_link_hwss = { ...@@ -756,6 +760,7 @@ static const struct link_hwss dio_link_hwss = {
.enable_dp_link_output = enable_dio_dp_link_output, .enable_dp_link_output = enable_dio_dp_link_output,
.disable_dp_link_output = disable_dio_dp_link_output, .disable_dp_link_output = disable_dio_dp_link_output,
.set_dp_link_test_pattern = set_dio_dp_link_test_pattern, .set_dp_link_test_pattern = set_dio_dp_link_test_pattern,
.set_dp_lane_settings = set_dio_dp_lane_settings,
}, },
}; };
...@@ -931,6 +936,17 @@ static void set_hpo_dp_link_test_pattern(struct dc_link *link, ...@@ -931,6 +936,17 @@ static void set_hpo_dp_link_test_pattern(struct dc_link *link,
dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN); dp_source_sequence_trace(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN);
} }
static void set_hpo_dp_lane_settings(struct dc_link *link,
const struct link_resource *link_res,
const struct dc_link_settings *link_settings,
const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
{
link_res->hpo_dp_link_enc->funcs->set_ffe(
link_res->hpo_dp_link_enc,
link_settings,
lane_settings[0].FFE_PRESET.raw);
}
static const struct link_hwss hpo_dp_link_hwss = { static const struct link_hwss hpo_dp_link_hwss = {
.setup_stream_encoder = setup_hpo_dp_stream_encoder, .setup_stream_encoder = setup_hpo_dp_stream_encoder,
.reset_stream_encoder = reset_hpo_dp_stream_encoder, .reset_stream_encoder = reset_hpo_dp_stream_encoder,
...@@ -940,6 +956,7 @@ static const struct link_hwss hpo_dp_link_hwss = { ...@@ -940,6 +956,7 @@ static const struct link_hwss hpo_dp_link_hwss = {
.enable_dp_link_output = enable_hpo_dp_link_output, .enable_dp_link_output = enable_hpo_dp_link_output,
.disable_dp_link_output = disable_hpo_dp_link_output, .disable_dp_link_output = disable_hpo_dp_link_output,
.set_dp_link_test_pattern = set_hpo_dp_link_test_pattern, .set_dp_link_test_pattern = set_hpo_dp_link_test_pattern,
.set_dp_lane_settings = set_hpo_dp_lane_settings,
}, },
}; };
/*********************** below goes to dpia_link_hwss *************************/ /*********************** below goes to dpia_link_hwss *************************/
...@@ -958,6 +975,7 @@ static const struct link_hwss dpia_link_hwss = { ...@@ -958,6 +975,7 @@ static const struct link_hwss dpia_link_hwss = {
.enable_dp_link_output = enable_dio_dp_link_output, .enable_dp_link_output = enable_dio_dp_link_output,
.disable_dp_link_output = disable_dio_dp_link_output, .disable_dp_link_output = disable_dio_dp_link_output,
.set_dp_link_test_pattern = set_dio_dp_link_test_pattern, .set_dp_link_test_pattern = set_dio_dp_link_test_pattern,
.set_dp_lane_settings = set_dio_dp_lane_settings,
}, },
}; };
......
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
View file @ 8788e066
...@@ -1325,7 +1325,8 @@ void dce110_link_encoder_disable_output( ...@@ -1325,7 +1325,8 @@ void dce110_link_encoder_disable_output(
void dce110_link_encoder_dp_set_lane_settings( void dce110_link_encoder_dp_set_lane_settings(
struct link_encoder *enc, struct link_encoder *enc,
const struct link_training_settings *link_settings) const struct dc_link_settings *link_settings,
const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
{ {
struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc); struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
union dpcd_training_lane_set training_lane_set = { { 0 } }; union dpcd_training_lane_set training_lane_set = { { 0 } };
...@@ -1340,26 +1341,26 @@ void dce110_link_encoder_dp_set_lane_settings( ...@@ -1340,26 +1341,26 @@ void dce110_link_encoder_dp_set_lane_settings(
cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS; cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
cntl.transmitter = enc110->base.transmitter; cntl.transmitter = enc110->base.transmitter;
cntl.connector_obj_id = enc110->base.connector; cntl.connector_obj_id = enc110->base.connector;
cntl.lanes_number = link_settings->link_settings.lane_count; cntl.lanes_number = link_settings->lane_count;
cntl.hpd_sel = enc110->base.hpd_source; cntl.hpd_sel = enc110->base.hpd_source;
cntl.pixel_clock = link_settings->link_settings.link_rate * cntl.pixel_clock = link_settings->link_rate *
LINK_RATE_REF_FREQ_IN_KHZ; LINK_RATE_REF_FREQ_IN_KHZ;
for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { for (lane = 0; lane < link_settings->lane_count; lane++) {
/* translate lane settings */ /* translate lane settings */
training_lane_set.bits.VOLTAGE_SWING_SET = training_lane_set.bits.VOLTAGE_SWING_SET =
link_settings->lane_settings[lane].VOLTAGE_SWING; lane_settings[lane].VOLTAGE_SWING;
training_lane_set.bits.PRE_EMPHASIS_SET = training_lane_set.bits.PRE_EMPHASIS_SET =
link_settings->lane_settings[lane].PRE_EMPHASIS; lane_settings[lane].PRE_EMPHASIS;
/* post cursor 2 setting only applies to HBR2 link rate */ /* post cursor 2 setting only applies to HBR2 link rate */
if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) { if (link_settings->link_rate == LINK_RATE_HIGH2) {
/* this is passed to VBIOS /* this is passed to VBIOS
* to program post cursor 2 level */ * to program post cursor 2 level */
training_lane_set.bits.POST_CURSOR2_SET = training_lane_set.bits.POST_CURSOR2_SET =
link_settings->lane_settings[lane].POST_CURSOR2; lane_settings[lane].POST_CURSOR2;
} }
cntl.lane_select = lane; cntl.lane_select = lane;
......
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h
View file @ 8788e066
...@@ -279,7 +279,8 @@ void dce110_link_encoder_disable_output( ...@@ -279,7 +279,8 @@ void dce110_link_encoder_disable_output(
/* set DP lane settings */ /* set DP lane settings */
void dce110_link_encoder_dp_set_lane_settings( void dce110_link_encoder_dp_set_lane_settings(
struct link_encoder *enc, struct link_encoder *enc,
const struct link_training_settings *link_settings); const struct dc_link_settings *link_settings,
const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
void dce110_link_encoder_dp_set_phy_pattern( void dce110_link_encoder_dp_set_phy_pattern(
struct link_encoder *enc, struct link_encoder *enc,
......
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.c
View file @ 8788e066
...@@ -1101,7 +1101,8 @@ void dcn10_link_encoder_disable_output( ...@@ -1101,7 +1101,8 @@ void dcn10_link_encoder_disable_output(
void dcn10_link_encoder_dp_set_lane_settings( void dcn10_link_encoder_dp_set_lane_settings(
struct link_encoder *enc, struct link_encoder *enc,
const struct link_training_settings *link_settings) const struct dc_link_settings *link_settings,
const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX])
{ {
struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
union dpcd_training_lane_set training_lane_set = { { 0 } }; union dpcd_training_lane_set training_lane_set = { { 0 } };
...@@ -1116,26 +1117,25 @@ void dcn10_link_encoder_dp_set_lane_settings( ...@@ -1116,26 +1117,25 @@ void dcn10_link_encoder_dp_set_lane_settings(
cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS; cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS;
cntl.transmitter = enc10->base.transmitter; cntl.transmitter = enc10->base.transmitter;
cntl.connector_obj_id = enc10->base.connector; cntl.connector_obj_id = enc10->base.connector;
cntl.lanes_number = link_settings->link_settings.lane_count; cntl.lanes_number = link_settings->lane_count;
cntl.hpd_sel = enc10->base.hpd_source; cntl.hpd_sel = enc10->base.hpd_source;
cntl.pixel_clock = link_settings->link_settings.link_rate * cntl.pixel_clock = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
LINK_RATE_REF_FREQ_IN_KHZ;
for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { for (lane = 0; lane < link_settings->lane_count; lane++) {
/* translate lane settings */ /* translate lane settings */
training_lane_set.bits.VOLTAGE_SWING_SET = training_lane_set.bits.VOLTAGE_SWING_SET =
link_settings->lane_settings[lane].VOLTAGE_SWING; lane_settings[lane].VOLTAGE_SWING;
training_lane_set.bits.PRE_EMPHASIS_SET = training_lane_set.bits.PRE_EMPHASIS_SET =
link_settings->lane_settings[lane].PRE_EMPHASIS; lane_settings[lane].PRE_EMPHASIS;
/* post cursor 2 setting only applies to HBR2 link rate */ /* post cursor 2 setting only applies to HBR2 link rate */
if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) { if (link_settings->link_rate == LINK_RATE_HIGH2) {
/* this is passed to VBIOS /* this is passed to VBIOS
* to program post cursor 2 level * to program post cursor 2 level
*/ */
training_lane_set.bits.POST_CURSOR2_SET = training_lane_set.bits.POST_CURSOR2_SET =
link_settings->lane_settings[lane].POST_CURSOR2; lane_settings[lane].POST_CURSOR2;
} }
cntl.lane_select = lane; cntl.lane_select = lane;
......
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
View file @ 8788e066
...@@ -581,7 +581,8 @@ void dcn10_link_encoder_disable_output( ...@@ -581,7 +581,8 @@ void dcn10_link_encoder_disable_output(
/* set DP lane settings */ /* set DP lane settings */
void dcn10_link_encoder_dp_set_lane_settings( void dcn10_link_encoder_dp_set_lane_settings(
struct link_encoder *enc, struct link_encoder *enc,
const struct link_training_settings *link_settings); const struct dc_link_settings *link_settings,
const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
void dcn10_link_encoder_dp_set_phy_pattern( void dcn10_link_encoder_dp_set_phy_pattern(
struct link_encoder *enc, struct link_encoder *enc,
......
drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h
View file @ 8788e066
...@@ -162,7 +162,8 @@ struct link_encoder_funcs { ...@@ -162,7 +162,8 @@ struct link_encoder_funcs {
void (*disable_output)(struct link_encoder *link_enc, void (*disable_output)(struct link_encoder *link_enc,
enum signal_type signal); enum signal_type signal);
void (*dp_set_lane_settings)(struct link_encoder *enc, void (*dp_set_lane_settings)(struct link_encoder *enc,
const struct link_training_settings *link_settings); const struct dc_link_settings *link_settings,
const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
void (*dp_set_phy_pattern)(struct link_encoder *enc, void (*dp_set_phy_pattern)(struct link_encoder *enc,
const struct encoder_set_dp_phy_pattern_param *para); const struct encoder_set_dp_phy_pattern_param *para);
void (*update_mst_stream_allocation_table)( void (*update_mst_stream_allocation_table)(
......
drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
View file @ 8788e066
...@@ -97,6 +97,10 @@ struct link_hwss_ext { ...@@ -97,6 +97,10 @@ struct link_hwss_ext {
void (*set_dp_link_test_pattern)(struct dc_link *link, void (*set_dp_link_test_pattern)(struct dc_link *link,
const struct link_resource *link_res, const struct link_resource *link_res,
struct encoder_set_dp_phy_pattern_param *tp_params); struct encoder_set_dp_phy_pattern_param *tp_params);
void (*set_dp_lane_settings)(struct dc_link *link,
const struct link_resource *link_res,
const struct dc_link_settings *link_settings,
const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]);
}; };
struct link_hwss { struct link_hwss {
......
drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c
View file @ 8788e066
...@@ -63,7 +63,8 @@ static void virtual_link_encoder_disable_output( ...@@ -63,7 +63,8 @@ static void virtual_link_encoder_disable_output(
static void virtual_link_encoder_dp_set_lane_settings( static void virtual_link_encoder_dp_set_lane_settings(
struct link_encoder *enc, struct link_encoder *enc,
const struct link_training_settings *link_settings) {} const struct dc_link_settings *link_settings,
const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) {}
static void virtual_link_encoder_dp_set_phy_pattern( static void virtual_link_encoder_dp_set_phy_pattern(
struct link_encoder *enc, struct link_encoder *enc,
......
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