Commit 882589bb authored by Richard Fitzgerald's avatar Richard Fitzgerald Committed by Mark Brown

ASoC: cs42l42: Only start PLL if it is needed

The PLL is only needed for sclk < 11289600 Hz and cs42l42_pll_config()
will not configure it for higher rates. So it must only be enabled
when it is needed.
Signed-off-by: default avatarRichard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: default avatarLucas Tanure <tanureal@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20210306185553.62053-15-tanureal@opensource.cirrus.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 0ea23660
...@@ -887,8 +887,9 @@ static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream) ...@@ -887,8 +887,9 @@ static int cs42l42_mute_stream(struct snd_soc_dai *dai, int mute, int stream)
} else { } else {
if (!cs42l42->stream_use) { if (!cs42l42->stream_use) {
/* SCLK must be running before codec unmute */ /* SCLK must be running before codec unmute */
snd_soc_component_update_bits(component, CS42L42_PLL_CTL1, if ((cs42l42->bclk < 11289600) && (cs42l42->sclk < 11289600))
CS42L42_PLL_START_MASK, 1); snd_soc_component_update_bits(component, CS42L42_PLL_CTL1,
CS42L42_PLL_START_MASK, 1);
/* Mark SCLK as present, turn off internal oscillator */ /* Mark SCLK as present, turn off internal oscillator */
regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq, regmap_multi_reg_write(cs42l42->regmap, cs42l42_to_sclk_seq,
......
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