Commit 88412a4e authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'drm-fixes-2020-04-24' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "Weekly regular fixes for drm, The usual rc3 uptick here, but nothing
  too crazy or notable.

  core:
   - mst: zero pbn when releasing vcpi slots

  amdgpu:
   - Fix resume issue on renoir
   - Thermal fix for older CI dGPUs
   - Fix some fallout from dropping drm load/unload callbacks

  i915:
   - Tigerlake Workaround - disabling media recompression (Matt)
   - Fix RPS interrupts for right GPU frequency (Chris)
   - HDCP fix prime check (Oliver)
   - Tigerlake Thunderbolt power well fix (Matt)
   - Tigerlake DP link training fixes (Jose)
   - Documentation sphinx build fix (Jani)
   - Fix enable_dpcd_backlight modparam (Lyude)

  analogix-dp:
   - binding fix

  meson:
   - remove unneeded error message

  bindings:
   - fix warnings
   - fix lvds binding

  scheduler:
   - thread racing fix

  tidss:
   - use after free fix"

* tag 'drm-fixes-2020-04-24' of git://anongit.freedesktop.org/drm/drm:
  drm/i915/dpcd_bl: Unbreak enable_dpcd_backlight modparam
  drm/i915: fix Sphinx build duplicate label warning
  drm/i915/display: Load DP_TP_CTL/STATUS offset before use it
  drm/i915/tgl: TBT AUX should use TC power well ops
  drm/i915: HDCP: fix Ri prime check done during link check
  drm/i915/gt: Update PMINTRMSK holding fw
  drm/i915/tgl: Add Wa_14010477008:tgl
  drm/tidss: fix crash related to accessing freed memory
  drm/dp_mst: Zero assigned PBN when releasing VCPI slots
  drm/amdgpu/display: give aux i2c buses more meaningful names
  drm/amdgpu/display: fix aux registration (v2)
  drm/amdgpu: Correctly initialize thermal controller for GPUs with Powerplay table v0 (e.g Hawaii)
  drm/amd/powerplay: fix resume failed as smu table initialize early exit
  drm/scheduler: fix drm_sched_get_cleanup_job
  drm/meson: Delete an error message in meson_dw_hdmi_bind()
  drm/bridge: anx6345: set correct BPC for display_info of connector
  dt-bindings: display: allow port and ports in panel-lvds
  dt-bindings: display: xpp055c272: Remove the reg property
  dt-bindings: display: ltk500hd1829: Remove the reg property
  drm/bridge: analogix_dp: Split bind() into probe() and real bind()
parents b4f63322 e32b2484
...@@ -37,7 +37,6 @@ examples: ...@@ -37,7 +37,6 @@ examples:
dsi { dsi {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <0xff450000 0x1000>;
panel@0 { panel@0 {
compatible = "leadtek,ltk500hd1829"; compatible = "leadtek,ltk500hd1829";
......
...@@ -96,12 +96,20 @@ properties: ...@@ -96,12 +96,20 @@ properties:
If set, reverse the bit order described in the data mappings below on all If set, reverse the bit order described in the data mappings below on all
data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6. data lanes, transmitting bits for slots 6 to 0 instead of 0 to 6.
port: true
ports: true
required: required:
- compatible - compatible
- data-mapping - data-mapping
- width-mm - width-mm
- height-mm - height-mm
- panel-timing - panel-timing
- port
oneOf:
- required:
- port
- required:
- ports
... ...
...@@ -37,7 +37,6 @@ examples: ...@@ -37,7 +37,6 @@ examples:
dsi { dsi {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg = <0xff450000 0x1000>;
panel@0 { panel@0 {
compatible = "xinpeng,xpp055c272"; compatible = "xinpeng,xpp055c272";
......
...@@ -4664,6 +4664,7 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector) ...@@ -4664,6 +4664,7 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
i2c_del_adapter(&aconnector->i2c->base); i2c_del_adapter(&aconnector->i2c->base);
kfree(aconnector->i2c); kfree(aconnector->i2c);
} }
kfree(aconnector->dm_dp_aux.aux.name);
kfree(connector); kfree(connector);
} }
...@@ -4723,10 +4724,19 @@ amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) ...@@ -4723,10 +4724,19 @@ amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
static int static int
amdgpu_dm_connector_late_register(struct drm_connector *connector) amdgpu_dm_connector_late_register(struct drm_connector *connector)
{ {
#if defined(CONFIG_DEBUG_FS)
struct amdgpu_dm_connector *amdgpu_dm_connector = struct amdgpu_dm_connector *amdgpu_dm_connector =
to_amdgpu_dm_connector(connector); to_amdgpu_dm_connector(connector);
int r;
if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
(connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev;
r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux);
if (r)
return r;
}
#if defined(CONFIG_DEBUG_FS)
connector_debugfs_init(amdgpu_dm_connector); connector_debugfs_init(amdgpu_dm_connector);
#endif #endif
...@@ -6092,7 +6102,7 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, ...@@ -6092,7 +6102,7 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
if (connector_type == DRM_MODE_CONNECTOR_DisplayPort if (connector_type == DRM_MODE_CONNECTOR_DisplayPort
|| connector_type == DRM_MODE_CONNECTOR_eDP) || connector_type == DRM_MODE_CONNECTOR_eDP)
amdgpu_dm_initialize_dp_connector(dm, aconnector); amdgpu_dm_initialize_dp_connector(dm, aconnector, link->link_index);
out_free: out_free:
if (res) { if (res) {
......
...@@ -156,16 +156,16 @@ amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) ...@@ -156,16 +156,16 @@ amdgpu_dm_mst_connector_late_register(struct drm_connector *connector)
to_amdgpu_dm_connector(connector); to_amdgpu_dm_connector(connector);
int r; int r;
amdgpu_dm_connector->dm_dp_aux.aux.dev = connector->kdev; r = drm_dp_mst_connector_late_register(connector,
r = drm_dp_aux_register(&amdgpu_dm_connector->dm_dp_aux.aux); amdgpu_dm_connector->port);
if (r) if (r < 0)
return r; return r;
#if defined(CONFIG_DEBUG_FS) #if defined(CONFIG_DEBUG_FS)
connector_debugfs_init(amdgpu_dm_connector); connector_debugfs_init(amdgpu_dm_connector);
#endif #endif
return r; return 0;
} }
static void static void
...@@ -472,9 +472,12 @@ static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { ...@@ -472,9 +472,12 @@ static const struct drm_dp_mst_topology_cbs dm_mst_cbs = {
}; };
void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
struct amdgpu_dm_connector *aconnector) struct amdgpu_dm_connector *aconnector,
int link_index)
{ {
aconnector->dm_dp_aux.aux.name = "dmdc"; aconnector->dm_dp_aux.aux.name =
kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d",
link_index);
aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer; aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer;
aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc; aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc;
......
...@@ -32,7 +32,8 @@ struct amdgpu_dm_connector; ...@@ -32,7 +32,8 @@ struct amdgpu_dm_connector;
int dm_mst_get_pbn_divider(struct dc_link *link); int dm_mst_get_pbn_divider(struct dc_link *link);
void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm,
struct amdgpu_dm_connector *aconnector); struct amdgpu_dm_connector *aconnector,
int link_index);
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_DCN)
bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, bool compute_mst_dsc_configs_for_state(struct drm_atomic_state *state,
......
...@@ -984,6 +984,32 @@ static int init_thermal_controller( ...@@ -984,6 +984,32 @@ static int init_thermal_controller(
struct pp_hwmgr *hwmgr, struct pp_hwmgr *hwmgr,
const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table) const ATOM_PPLIB_POWERPLAYTABLE *powerplay_table)
{ {
hwmgr->thermal_controller.ucType =
powerplay_table->sThermalController.ucType;
hwmgr->thermal_controller.ucI2cLine =
powerplay_table->sThermalController.ucI2cLine;
hwmgr->thermal_controller.ucI2cAddress =
powerplay_table->sThermalController.ucI2cAddress;
hwmgr->thermal_controller.fanInfo.bNoFan =
(0 != (powerplay_table->sThermalController.ucFanParameters &
ATOM_PP_FANPARAMETERS_NOFAN));
hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution =
powerplay_table->sThermalController.ucFanParameters &
ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
hwmgr->thermal_controller.fanInfo.ulMinRPM
= powerplay_table->sThermalController.ucFanMinRPM * 100UL;
hwmgr->thermal_controller.fanInfo.ulMaxRPM
= powerplay_table->sThermalController.ucFanMaxRPM * 100UL;
set_hw_cap(hwmgr,
ATOM_PP_THERMALCONTROLLER_NONE != hwmgr->thermal_controller.ucType,
PHM_PlatformCaps_ThermalController);
hwmgr->thermal_controller.use_hw_fan_control = 1;
return 0; return 0;
} }
......
...@@ -895,12 +895,17 @@ static int renoir_read_sensor(struct smu_context *smu, ...@@ -895,12 +895,17 @@ static int renoir_read_sensor(struct smu_context *smu,
static bool renoir_is_dpm_running(struct smu_context *smu) static bool renoir_is_dpm_running(struct smu_context *smu)
{ {
struct amdgpu_device *adev = smu->adev;
/* /*
* Util now, the pmfw hasn't exported the interface of SMU * Util now, the pmfw hasn't exported the interface of SMU
* feature mask to APU SKU so just force on all the feature * feature mask to APU SKU so just force on all the feature
* at early initial stage. * at early initial stage.
*/ */
return true; if (adev->in_suspend)
return false;
else
return true;
} }
......
...@@ -485,6 +485,9 @@ static int anx6345_get_modes(struct drm_connector *connector) ...@@ -485,6 +485,9 @@ static int anx6345_get_modes(struct drm_connector *connector)
num_modes += drm_add_edid_modes(connector, anx6345->edid); num_modes += drm_add_edid_modes(connector, anx6345->edid);
/* Driver currently supports only 6bpc */
connector->display_info.bpc = 6;
unlock: unlock:
if (power_off) if (power_off)
anx6345_poweroff(anx6345); anx6345_poweroff(anx6345);
......
...@@ -4295,6 +4295,7 @@ int drm_dp_atomic_release_vcpi_slots(struct drm_atomic_state *state, ...@@ -4295,6 +4295,7 @@ int drm_dp_atomic_release_vcpi_slots(struct drm_atomic_state *state,
if (pos->vcpi) { if (pos->vcpi) {
drm_dp_mst_put_port_malloc(port); drm_dp_mst_put_port_malloc(port);
pos->vcpi = 0; pos->vcpi = 0;
pos->pbn = 0;
} }
return 0; return 0;
......
...@@ -3141,9 +3141,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder, ...@@ -3141,9 +3141,6 @@ static void hsw_ddi_pre_enable_dp(struct intel_encoder *encoder,
intel_dp_set_link_params(intel_dp, crtc_state->port_clock, intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
crtc_state->lane_count, is_mst); crtc_state->lane_count, is_mst);
intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
intel_edp_panel_on(intel_dp); intel_edp_panel_on(intel_dp);
intel_ddi_clk_select(encoder, crtc_state); intel_ddi_clk_select(encoder, crtc_state);
...@@ -3848,12 +3845,18 @@ void intel_ddi_get_config(struct intel_encoder *encoder, ...@@ -3848,12 +3845,18 @@ void intel_ddi_get_config(struct intel_encoder *encoder,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc); struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
u32 temp, flags = 0; u32 temp, flags = 0;
/* XXX: DSI transcoder paranoia */ /* XXX: DSI transcoder paranoia */
if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder))) if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
return; return;
if (INTEL_GEN(dev_priv) >= 12) {
intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(cpu_transcoder);
intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(cpu_transcoder);
}
intel_dsc_get_config(encoder, pipe_config); intel_dsc_get_config(encoder, pipe_config);
temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
...@@ -4173,6 +4176,7 @@ static const struct drm_encoder_funcs intel_ddi_funcs = { ...@@ -4173,6 +4176,7 @@ static const struct drm_encoder_funcs intel_ddi_funcs = {
static struct intel_connector * static struct intel_connector *
intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
{ {
struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
struct intel_connector *connector; struct intel_connector *connector;
enum port port = intel_dig_port->base.port; enum port port = intel_dig_port->base.port;
...@@ -4183,6 +4187,10 @@ intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) ...@@ -4183,6 +4187,10 @@ intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
intel_dig_port->dp.prepare_link_retrain = intel_dig_port->dp.prepare_link_retrain =
intel_ddi_prepare_link_retrain; intel_ddi_prepare_link_retrain;
if (INTEL_GEN(dev_priv) < 12) {
intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
}
if (!intel_dp_init_connector(intel_dig_port, connector)) { if (!intel_dp_init_connector(intel_dig_port, connector)) {
kfree(connector); kfree(connector);
......
...@@ -4140,7 +4140,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { ...@@ -4140,7 +4140,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
{ {
.name = "AUX D TBT1", .name = "AUX D TBT1",
.domains = TGL_AUX_D_TBT1_IO_POWER_DOMAINS, .domains = TGL_AUX_D_TBT1_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops, .ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE, .id = DISP_PW_ID_NONE,
{ {
.hsw.regs = &icl_aux_power_well_regs, .hsw.regs = &icl_aux_power_well_regs,
...@@ -4151,7 +4151,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { ...@@ -4151,7 +4151,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
{ {
.name = "AUX E TBT2", .name = "AUX E TBT2",
.domains = TGL_AUX_E_TBT2_IO_POWER_DOMAINS, .domains = TGL_AUX_E_TBT2_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops, .ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE, .id = DISP_PW_ID_NONE,
{ {
.hsw.regs = &icl_aux_power_well_regs, .hsw.regs = &icl_aux_power_well_regs,
...@@ -4162,7 +4162,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { ...@@ -4162,7 +4162,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
{ {
.name = "AUX F TBT3", .name = "AUX F TBT3",
.domains = TGL_AUX_F_TBT3_IO_POWER_DOMAINS, .domains = TGL_AUX_F_TBT3_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops, .ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE, .id = DISP_PW_ID_NONE,
{ {
.hsw.regs = &icl_aux_power_well_regs, .hsw.regs = &icl_aux_power_well_regs,
...@@ -4173,7 +4173,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { ...@@ -4173,7 +4173,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
{ {
.name = "AUX G TBT4", .name = "AUX G TBT4",
.domains = TGL_AUX_G_TBT4_IO_POWER_DOMAINS, .domains = TGL_AUX_G_TBT4_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops, .ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE, .id = DISP_PW_ID_NONE,
{ {
.hsw.regs = &icl_aux_power_well_regs, .hsw.regs = &icl_aux_power_well_regs,
...@@ -4184,7 +4184,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { ...@@ -4184,7 +4184,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
{ {
.name = "AUX H TBT5", .name = "AUX H TBT5",
.domains = TGL_AUX_H_TBT5_IO_POWER_DOMAINS, .domains = TGL_AUX_H_TBT5_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops, .ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE, .id = DISP_PW_ID_NONE,
{ {
.hsw.regs = &icl_aux_power_well_regs, .hsw.regs = &icl_aux_power_well_regs,
...@@ -4195,7 +4195,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = { ...@@ -4195,7 +4195,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
{ {
.name = "AUX I TBT6", .name = "AUX I TBT6",
.domains = TGL_AUX_I_TBT6_IO_POWER_DOMAINS, .domains = TGL_AUX_I_TBT6_IO_POWER_DOMAINS,
.ops = &hsw_power_well_ops, .ops = &icl_tc_phy_aux_power_well_ops,
.id = DISP_PW_ID_NONE, .id = DISP_PW_ID_NONE,
{ {
.hsw.regs = &icl_aux_power_well_regs, .hsw.regs = &icl_aux_power_well_regs,
......
...@@ -2517,9 +2517,6 @@ static void intel_dp_prepare(struct intel_encoder *encoder, ...@@ -2517,9 +2517,6 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
intel_crtc_has_type(pipe_config, intel_crtc_has_type(pipe_config,
INTEL_OUTPUT_DP_MST)); INTEL_OUTPUT_DP_MST));
intel_dp->regs.dp_tp_ctl = DP_TP_CTL(port);
intel_dp->regs.dp_tp_status = DP_TP_STATUS(port);
/* /*
* There are four kinds of DP registers: * There are four kinds of DP registers:
* *
...@@ -7836,6 +7833,8 @@ bool intel_dp_init(struct drm_i915_private *dev_priv, ...@@ -7836,6 +7833,8 @@ bool intel_dp_init(struct drm_i915_private *dev_priv,
intel_dig_port->dp.output_reg = output_reg; intel_dig_port->dp.output_reg = output_reg;
intel_dig_port->max_lanes = 4; intel_dig_port->max_lanes = 4;
intel_dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
intel_dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
intel_encoder->type = INTEL_OUTPUT_DP; intel_encoder->type = INTEL_OUTPUT_DP;
intel_encoder->power_domain = intel_port_to_power_domain(port); intel_encoder->power_domain = intel_port_to_power_domain(port);
......
...@@ -342,6 +342,7 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector) ...@@ -342,6 +342,7 @@ int intel_dp_aux_init_backlight_funcs(struct intel_connector *intel_connector)
*/ */
if (dev_priv->vbt.backlight.type != if (dev_priv->vbt.backlight.type !=
INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE && INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE &&
i915_modparams.enable_dpcd_backlight != 1 &&
!drm_dp_has_quirk(&intel_dp->desc, intel_dp->edid_quirks, !drm_dp_has_quirk(&intel_dp->desc, intel_dp->edid_quirks,
DP_QUIRK_FORCE_DPCD_BACKLIGHT)) { DP_QUIRK_FORCE_DPCD_BACKLIGHT)) {
DRM_DEV_INFO(dev->dev, DRM_DEV_INFO(dev->dev,
......
...@@ -1536,7 +1536,8 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port) ...@@ -1536,7 +1536,8 @@ bool intel_hdmi_hdcp_check_link(struct intel_digital_port *intel_dig_port)
intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg); intel_de_write(i915, HDCP_RPRIME(i915, cpu_transcoder, port), ri.reg);
/* Wait for Ri prime match */ /* Wait for Ri prime match */
if (wait_for(intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) & if (wait_for((intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)) &
(HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC)) ==
(HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) { (HDCP_STATUS_RI_MATCH | HDCP_STATUS_ENC), 1)) {
DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n", DRM_ERROR("Ri' mismatch detected, link check failed (%x)\n",
intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port))); intel_de_read(i915, HDCP_STATUS(i915, cpu_transcoder, port)));
......
...@@ -2817,19 +2817,25 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane, ...@@ -2817,19 +2817,25 @@ static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
} }
} }
static bool gen12_plane_supports_mc_ccs(enum plane_id plane_id) static bool gen12_plane_supports_mc_ccs(struct drm_i915_private *dev_priv,
enum plane_id plane_id)
{ {
/* Wa_14010477008:tgl[a0..c0] */
if (IS_TGL_REVID(dev_priv, TGL_REVID_A0, TGL_REVID_C0))
return false;
return plane_id < PLANE_SPRITE4; return plane_id < PLANE_SPRITE4;
} }
static bool gen12_plane_format_mod_supported(struct drm_plane *_plane, static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
u32 format, u64 modifier) u32 format, u64 modifier)
{ {
struct drm_i915_private *dev_priv = to_i915(_plane->dev);
struct intel_plane *plane = to_intel_plane(_plane); struct intel_plane *plane = to_intel_plane(_plane);
switch (modifier) { switch (modifier) {
case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
if (!gen12_plane_supports_mc_ccs(plane->id)) if (!gen12_plane_supports_mc_ccs(dev_priv, plane->id))
return false; return false;
/* fall through */ /* fall through */
case DRM_FORMAT_MOD_LINEAR: case DRM_FORMAT_MOD_LINEAR:
...@@ -2998,9 +3004,10 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv, ...@@ -2998,9 +3004,10 @@ static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
} }
} }
static const u64 *gen12_get_plane_modifiers(enum plane_id plane_id) static const u64 *gen12_get_plane_modifiers(struct drm_i915_private *dev_priv,
enum plane_id plane_id)
{ {
if (gen12_plane_supports_mc_ccs(plane_id)) if (gen12_plane_supports_mc_ccs(dev_priv, plane_id))
return gen12_plane_format_modifiers_mc_ccs; return gen12_plane_format_modifiers_mc_ccs;
else else
return gen12_plane_format_modifiers_rc_ccs; return gen12_plane_format_modifiers_rc_ccs;
...@@ -3070,7 +3077,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, ...@@ -3070,7 +3077,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id); plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe, plane_id);
if (INTEL_GEN(dev_priv) >= 12) { if (INTEL_GEN(dev_priv) >= 12) {
modifiers = gen12_get_plane_modifiers(plane_id); modifiers = gen12_get_plane_modifiers(dev_priv, plane_id);
plane_funcs = &gen12_plane_funcs; plane_funcs = &gen12_plane_funcs;
} else { } else {
if (plane->has_ccs) if (plane->has_ccs)
......
...@@ -81,13 +81,14 @@ static void rps_enable_interrupts(struct intel_rps *rps) ...@@ -81,13 +81,14 @@ static void rps_enable_interrupts(struct intel_rps *rps)
events = (GEN6_PM_RP_UP_THRESHOLD | events = (GEN6_PM_RP_UP_THRESHOLD |
GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_THRESHOLD |
GEN6_PM_RP_DOWN_TIMEOUT); GEN6_PM_RP_DOWN_TIMEOUT);
WRITE_ONCE(rps->pm_events, events); WRITE_ONCE(rps->pm_events, events);
spin_lock_irq(&gt->irq_lock); spin_lock_irq(&gt->irq_lock);
gen6_gt_pm_enable_irq(gt, rps->pm_events); gen6_gt_pm_enable_irq(gt, rps->pm_events);
spin_unlock_irq(&gt->irq_lock); spin_unlock_irq(&gt->irq_lock);
set(gt->uncore, GEN6_PMINTRMSK, rps_pm_mask(rps, rps->cur_freq)); intel_uncore_write(gt->uncore,
GEN6_PMINTRMSK, rps_pm_mask(rps, rps->last_freq));
} }
static void gen6_rps_reset_interrupts(struct intel_rps *rps) static void gen6_rps_reset_interrupts(struct intel_rps *rps)
...@@ -120,7 +121,9 @@ static void rps_disable_interrupts(struct intel_rps *rps) ...@@ -120,7 +121,9 @@ static void rps_disable_interrupts(struct intel_rps *rps)
struct intel_gt *gt = rps_to_gt(rps); struct intel_gt *gt = rps_to_gt(rps);
WRITE_ONCE(rps->pm_events, 0); WRITE_ONCE(rps->pm_events, 0);
set(gt->uncore, GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
intel_uncore_write(gt->uncore,
GEN6_PMINTRMSK, rps_pm_sanitize_mask(rps, ~0u));
spin_lock_irq(&gt->irq_lock); spin_lock_irq(&gt->irq_lock);
gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS); gen6_gt_pm_disable_irq(gt, GEN6_PM_RPS_EVENTS);
......
...@@ -1507,6 +1507,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, ...@@ -1507,6 +1507,8 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
(IS_ICELAKE(p) && IS_REVID(p, since, until)) (IS_ICELAKE(p) && IS_REVID(p, since, until))
#define TGL_REVID_A0 0x0 #define TGL_REVID_A0 0x0
#define TGL_REVID_B0 0x1
#define TGL_REVID_C0 0x2
#define IS_TGL_REVID(p, since, until) \ #define IS_TGL_REVID(p, since, until) \
(IS_TIGERLAKE(p) && IS_REVID(p, since, until)) (IS_TIGERLAKE(p) && IS_REVID(p, since, until))
......
...@@ -34,8 +34,8 @@ ...@@ -34,8 +34,8 @@
* Follow the style described here for new macros, and while changing existing * Follow the style described here for new macros, and while changing existing
* macros. Do **not** mass change existing definitions just to update the style. * macros. Do **not** mass change existing definitions just to update the style.
* *
* Layout * File Layout
* ~~~~~~ * ~~~~~~~~~~~
* *
* Keep helper macros near the top. For example, _PIPE() and friends. * Keep helper macros near the top. For example, _PIPE() and friends.
* *
......
...@@ -1034,10 +1034,8 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master, ...@@ -1034,10 +1034,8 @@ static int meson_dw_hdmi_bind(struct device *dev, struct device *master,
return PTR_ERR(dw_plat_data->regm); return PTR_ERR(dw_plat_data->regm);
irq = platform_get_irq(pdev, 0); irq = platform_get_irq(pdev, 0);
if (irq < 0) { if (irq < 0)
dev_err(dev, "Failed to get hdmi top irq\n");
return irq; return irq;
}
ret = devm_request_threaded_irq(dev, irq, dw_hdmi_top_irq, ret = devm_request_threaded_irq(dev, irq, dw_hdmi_top_irq,
dw_hdmi_top_thread_irq, IRQF_SHARED, dw_hdmi_top_thread_irq, IRQF_SHARED,
......
...@@ -676,7 +676,7 @@ drm_sched_get_cleanup_job(struct drm_gpu_scheduler *sched) ...@@ -676,7 +676,7 @@ drm_sched_get_cleanup_job(struct drm_gpu_scheduler *sched)
*/ */
if ((sched->timeout != MAX_SCHEDULE_TIMEOUT && if ((sched->timeout != MAX_SCHEDULE_TIMEOUT &&
!cancel_delayed_work(&sched->work_tdr)) || !cancel_delayed_work(&sched->work_tdr)) ||
__kthread_should_park(sched->thread)) kthread_should_park())
return NULL; return NULL;
spin_lock(&sched->job_list_lock); spin_lock(&sched->job_list_lock);
......
...@@ -379,9 +379,17 @@ static struct drm_crtc_state *tidss_crtc_duplicate_state(struct drm_crtc *crtc) ...@@ -379,9 +379,17 @@ static struct drm_crtc_state *tidss_crtc_duplicate_state(struct drm_crtc *crtc)
return &state->base; return &state->base;
} }
static void tidss_crtc_destroy(struct drm_crtc *crtc)
{
struct tidss_crtc *tcrtc = to_tidss_crtc(crtc);
drm_crtc_cleanup(crtc);
kfree(tcrtc);
}
static const struct drm_crtc_funcs tidss_crtc_funcs = { static const struct drm_crtc_funcs tidss_crtc_funcs = {
.reset = tidss_crtc_reset, .reset = tidss_crtc_reset,
.destroy = drm_crtc_cleanup, .destroy = tidss_crtc_destroy,
.set_config = drm_atomic_helper_set_config, .set_config = drm_atomic_helper_set_config,
.page_flip = drm_atomic_helper_page_flip, .page_flip = drm_atomic_helper_page_flip,
.atomic_duplicate_state = tidss_crtc_duplicate_state, .atomic_duplicate_state = tidss_crtc_duplicate_state,
...@@ -400,7 +408,7 @@ struct tidss_crtc *tidss_crtc_create(struct tidss_device *tidss, ...@@ -400,7 +408,7 @@ struct tidss_crtc *tidss_crtc_create(struct tidss_device *tidss,
bool has_ctm = tidss->feat->vp_feat.color.has_ctm; bool has_ctm = tidss->feat->vp_feat.color.has_ctm;
int ret; int ret;
tcrtc = devm_kzalloc(tidss->dev, sizeof(*tcrtc), GFP_KERNEL); tcrtc = kzalloc(sizeof(*tcrtc), GFP_KERNEL);
if (!tcrtc) if (!tcrtc)
return ERR_PTR(-ENOMEM); return ERR_PTR(-ENOMEM);
...@@ -411,8 +419,10 @@ struct tidss_crtc *tidss_crtc_create(struct tidss_device *tidss, ...@@ -411,8 +419,10 @@ struct tidss_crtc *tidss_crtc_create(struct tidss_device *tidss,
ret = drm_crtc_init_with_planes(&tidss->ddev, crtc, primary, ret = drm_crtc_init_with_planes(&tidss->ddev, crtc, primary,
NULL, &tidss_crtc_funcs, NULL); NULL, &tidss_crtc_funcs, NULL);
if (ret < 0) if (ret < 0) {
kfree(tcrtc);
return ERR_PTR(ret); return ERR_PTR(ret);
}
drm_crtc_helper_add(crtc, &tidss_crtc_helper_funcs); drm_crtc_helper_add(crtc, &tidss_crtc_helper_funcs);
......
...@@ -55,12 +55,18 @@ static int tidss_encoder_atomic_check(struct drm_encoder *encoder, ...@@ -55,12 +55,18 @@ static int tidss_encoder_atomic_check(struct drm_encoder *encoder,
return 0; return 0;
} }
static void tidss_encoder_destroy(struct drm_encoder *encoder)
{
drm_encoder_cleanup(encoder);
kfree(encoder);
}
static const struct drm_encoder_helper_funcs encoder_helper_funcs = { static const struct drm_encoder_helper_funcs encoder_helper_funcs = {
.atomic_check = tidss_encoder_atomic_check, .atomic_check = tidss_encoder_atomic_check,
}; };
static const struct drm_encoder_funcs encoder_funcs = { static const struct drm_encoder_funcs encoder_funcs = {
.destroy = drm_encoder_cleanup, .destroy = tidss_encoder_destroy,
}; };
struct drm_encoder *tidss_encoder_create(struct tidss_device *tidss, struct drm_encoder *tidss_encoder_create(struct tidss_device *tidss,
...@@ -69,7 +75,7 @@ struct drm_encoder *tidss_encoder_create(struct tidss_device *tidss, ...@@ -69,7 +75,7 @@ struct drm_encoder *tidss_encoder_create(struct tidss_device *tidss,
struct drm_encoder *enc; struct drm_encoder *enc;
int ret; int ret;
enc = devm_kzalloc(tidss->dev, sizeof(*enc), GFP_KERNEL); enc = kzalloc(sizeof(*enc), GFP_KERNEL);
if (!enc) if (!enc)
return ERR_PTR(-ENOMEM); return ERR_PTR(-ENOMEM);
...@@ -77,8 +83,10 @@ struct drm_encoder *tidss_encoder_create(struct tidss_device *tidss, ...@@ -77,8 +83,10 @@ struct drm_encoder *tidss_encoder_create(struct tidss_device *tidss,
ret = drm_encoder_init(&tidss->ddev, enc, &encoder_funcs, ret = drm_encoder_init(&tidss->ddev, enc, &encoder_funcs,
encoder_type, NULL); encoder_type, NULL);
if (ret < 0) if (ret < 0) {
kfree(enc);
return ERR_PTR(ret); return ERR_PTR(ret);
}
drm_encoder_helper_add(enc, &encoder_helper_funcs); drm_encoder_helper_add(enc, &encoder_helper_funcs);
......
...@@ -141,6 +141,14 @@ static void tidss_plane_atomic_disable(struct drm_plane *plane, ...@@ -141,6 +141,14 @@ static void tidss_plane_atomic_disable(struct drm_plane *plane,
dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false); dispc_plane_enable(tidss->dispc, tplane->hw_plane_id, false);
} }
static void drm_plane_destroy(struct drm_plane *plane)
{
struct tidss_plane *tplane = to_tidss_plane(plane);
drm_plane_cleanup(plane);
kfree(tplane);
}
static const struct drm_plane_helper_funcs tidss_plane_helper_funcs = { static const struct drm_plane_helper_funcs tidss_plane_helper_funcs = {
.atomic_check = tidss_plane_atomic_check, .atomic_check = tidss_plane_atomic_check,
.atomic_update = tidss_plane_atomic_update, .atomic_update = tidss_plane_atomic_update,
...@@ -151,7 +159,7 @@ static const struct drm_plane_funcs tidss_plane_funcs = { ...@@ -151,7 +159,7 @@ static const struct drm_plane_funcs tidss_plane_funcs = {
.update_plane = drm_atomic_helper_update_plane, .update_plane = drm_atomic_helper_update_plane,
.disable_plane = drm_atomic_helper_disable_plane, .disable_plane = drm_atomic_helper_disable_plane,
.reset = drm_atomic_helper_plane_reset, .reset = drm_atomic_helper_plane_reset,
.destroy = drm_plane_cleanup, .destroy = drm_plane_destroy,
.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
.atomic_destroy_state = drm_atomic_helper_plane_destroy_state, .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
}; };
...@@ -175,7 +183,7 @@ struct tidss_plane *tidss_plane_create(struct tidss_device *tidss, ...@@ -175,7 +183,7 @@ struct tidss_plane *tidss_plane_create(struct tidss_device *tidss,
BIT(DRM_MODE_BLEND_COVERAGE)); BIT(DRM_MODE_BLEND_COVERAGE));
int ret; int ret;
tplane = devm_kzalloc(tidss->dev, sizeof(*tplane), GFP_KERNEL); tplane = kzalloc(sizeof(*tplane), GFP_KERNEL);
if (!tplane) if (!tplane)
return ERR_PTR(-ENOMEM); return ERR_PTR(-ENOMEM);
...@@ -190,7 +198,7 @@ struct tidss_plane *tidss_plane_create(struct tidss_device *tidss, ...@@ -190,7 +198,7 @@ struct tidss_plane *tidss_plane_create(struct tidss_device *tidss,
formats, num_formats, formats, num_formats,
NULL, type, NULL); NULL, type, NULL);
if (ret < 0) if (ret < 0)
return ERR_PTR(ret); goto err;
drm_plane_helper_add(&tplane->plane, &tidss_plane_helper_funcs); drm_plane_helper_add(&tplane->plane, &tidss_plane_helper_funcs);
...@@ -203,15 +211,19 @@ struct tidss_plane *tidss_plane_create(struct tidss_device *tidss, ...@@ -203,15 +211,19 @@ struct tidss_plane *tidss_plane_create(struct tidss_device *tidss,
default_encoding, default_encoding,
default_range); default_range);
if (ret) if (ret)
return ERR_PTR(ret); goto err;
ret = drm_plane_create_alpha_property(&tplane->plane); ret = drm_plane_create_alpha_property(&tplane->plane);
if (ret) if (ret)
return ERR_PTR(ret); goto err;
ret = drm_plane_create_blend_mode_property(&tplane->plane, blend_modes); ret = drm_plane_create_blend_mode_property(&tplane->plane, blend_modes);
if (ret) if (ret)
return ERR_PTR(ret); goto err;
return tplane; return tplane;
err:
kfree(tplane);
return ERR_PTR(ret);
} }
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