Skip to content

L
linux
Commit 8892e4ec authored by Nick Kossifidis's avatar Nick Kossifidis Committed by John W. Linville
Browse files
Options

ath5k: Update RF Buffer handling 

 * Use the new way to modify rf buffer and put some rf buffer
   documentation on rfbufer.h

 * Merge all rf regs functions to one

 * Sync with legacy HAL and Sam's HAL

 * Set gain_F settings so that gain_F optimization engine works
   on RF5111/RF5112 (note that both HALs only use step 0 for RF5111
   and they don't use gain_F optimization for this chip, code is
   there but is never used)
Signed-off-by: default avatarNick Kossifidis <mickflemm@gmail.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 6f3b414a
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 379 additions and 317 deletions
drivers/net/wireless/ath5k/ath5k.h
View file @ 8892e4ec
......@@ -165,9 +165,6 @@
#define AR5K_INI_VAL_XR 0
#define AR5K_INI_VAL_MAX 5
#define AR5K_RF5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
#define AR5K_RF5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
/* Used for BSSID etc manipulation */
#define AR5K_LOW_ID(_a)( \
(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
......@@ -342,6 +339,7 @@ struct ath5k_srev_name {
#define AR5K_SREV_PHY_5211 0x30
#define AR5K_SREV_PHY_5212 0x41
#define AR5K_SREV_PHY_5212A 0x42
#define AR5K_SREV_PHY_2112B 0x43
#define AR5K_SREV_PHY_2413 0x45
#define AR5K_SREV_PHY_5413 0x61
......@@ -1083,8 +1081,9 @@ struct ath5k_hw {
u32 ah_txq_isr;
u32 *ah_rf_banks;
size_t ah_rf_banks_size;
size_t ah_rf_regs_count;
struct ath5k_gain ah_gain;
u32 ah_offset[AR5K_MAX_RF_BANKS];
u8 ah_offset[AR5K_MAX_RF_BANKS];
struct {
u16 txp_pcdac[AR5K_EEPROM_POWER_TABLE_SIZE];
......@@ -1232,7 +1231,9 @@ extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
/* Initialize RF */
extern int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel *channel, unsigned int mode);
extern int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
struct ieee80211_channel *channel,
unsigned int mode);
extern int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
extern enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
......
drivers/net/wireless/ath5k/phy.c
View file @ 8892e4ec
This diff is collapsed.
drivers/net/wireless/ath5k/reg.h
View file @ 8892e4ec
......@@ -2101,34 +2101,10 @@
/*
* RF Buffer register
*
* There are some special control registers on the RF chip
* that hold various operation settings related mostly to
* the analog parts (channel, gain adjustment etc).
*
* We don't write on those registers directly but
* we send a data packet on the buffer register and
* then write on another special register to notify hw
* to apply the settings. This is done so that control registers
* can be dynamicaly programmed during operation and the settings
* are applied faster on the hw.
*
* We sent such data packets during rf initialization and channel change
* through ath5k_hw_rf*_rfregs and ath5k_hw_rf*_channel functions.
*
* The data packets we send during initializadion are inside ath5k_ini_rf
* struct (see ath5k_hw.h) and each one is related to an "rf register bank".
* We use *rfregs functions to modify them acording to current operation
* mode and eeprom values and pass them all together to the chip.
*
* It's obvious from the code that 0x989c is the buffer register but
* for the other special registers that we write to after sending each
* packet, i have no idea. So i'll name them BUFFER_CONTROL_X registers
* for now. It's interesting that they are also used for some other operations.
*
* Also check out hw.h and U.S. Patent 6677779 B1 (about buffer
* registers and control registers):
*
* http://www.google.com/patents?id=qNURAAAAEBAJ
*/
#define AR5K_RF_BUFFER 0x989c
......
drivers/net/wireless/ath5k/reset.c
View file @ 8892e4ec
......@@ -600,7 +600,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
/*
* Write RF registers
*/
ret = ath5k_hw_rfregs(ah, channel, mode);
ret = ath5k_hw_rfregs_init(ah, channel, mode);
if (ret)
return ret;
......
drivers/net/wireless/ath5k/rfbuffer.h
View file @ 8892e4ec
......@@ -17,6 +17,33 @@
*
*/
/*
* There are some special registers on the RF chip
* that control various operation settings related mostly to
* the analog parts (channel, gain adjustment etc).
*
* We don't write on those registers directly but
* we send a data packet on the chip, using a special register,
* that holds all the settings we need. After we 've sent the
* data packet, we write on another special register to notify hw
* to apply the settings. This is done so that control registers
* can be dynamicaly programmed during operation and the settings
* are applied faster on the hw.
*
* We call each data packet an "RF Bank" and all the data we write
* (all RF Banks) "RF Buffer". This file holds initial RF Buffer
* data for the different RF chips, and various info to match RF
* Buffer offsets with specific RF registers so that we can access
* them. We tweak these settings on rfregs_init function.
*
* Also check out reg.h and U.S. Patent 6677779 B1 (about buffer
* registers and control registers):
*
* http://www.google.com/patents?id=qNURAAAAEBAJ
*/
/*
* Struct to hold default mode specific RF
* register values (RF Banks)
......@@ -72,15 +99,28 @@ enum ath5k_rf_regs_idx {
AR5K_RF_XB2_LVL,
AR5K_RF_XB5_LVL,
AR5K_RF_PWD_ICLOBUF_2G,
AR5K_RF_PWD_84,
AR5K_RF_PWD_90,
AR5K_RF_PWD_130,
AR5K_RF_PWD_131,
AR5K_RF_PWD_132,
AR5K_RF_PWD_136,
AR5K_RF_PWD_137,
AR5K_RF_PWD_138,
AR5K_RF_PWD_166,
AR5K_RF_PWD_167,
AR5K_RF_DERBY_CHAN_SEL_MODE,
/* BANK 7 */
AR5K_RF_GAIN_I,
AR5K_RF_PLO_SEL,
AR5K_RF_RFGAIN_SEL,
AR5K_RF_RFGAIN_STEP,
AR5K_RF_WAIT_S,
AR5K_RF_WAIT_I,
AR5K_RF_MAX_TIME,
AR5K_RF_MIXVGA_OVR,
AR5K_RF_MIXGAIN_OVR,
AR5K_RF_MIXGAIN_STEP,
AR5K_RF_PD_DELAY_A,
AR5K_RF_PD_DELAY_B,
AR5K_RF_PD_DELAY_XR,
......@@ -118,19 +158,21 @@ enum ath5k_rf_regs_idx {
#define AR5K_RF5111_MAX_TIME { 2, 49, 0 }
static const struct ath5k_rf_reg rf_regs_5111[] = {
{6, AR5K_RF_OB_2GHZ, AR5K_RF5111_OB_2GHZ},
{6, AR5K_RF_DB_2GHZ, AR5K_RF5111_DB_2GHZ},
{6, AR5K_RF_OB_5GHZ, AR5K_RF5111_OB_5GHZ},
{6, AR5K_RF_DB_5GHZ, AR5K_RF5111_DB_5GHZ},
{6, AR5K_RF_PWD_XPD, AR5K_RF5111_PWD_XPD},
{6, AR5K_RF_XPD_GAIN, AR5K_RF5111_XPD_GAIN},
{7, AR5K_RF_GAIN_I, AR5K_RF5111_GAIN_I},
{7, AR5K_RF_PLO_SEL, AR5K_RF5111_PLO_SEL},
{7, AR5K_RF_RFGAIN_SEL, AR5K_RF5111_RFGAIN_SEL},
{7, AR5K_RF_WAIT_S, AR5K_RF5111_WAIT_S},
{7, AR5K_RF_WAIT_I, AR5K_RF5111_WAIT_I},
{7, AR5K_RF_MAX_TIME, AR5K_RF5111_MAX_TIME}
{6, AR5K_RF_OB_2GHZ, AR5K_RF5111_OB_2GHZ},
{6, AR5K_RF_DB_2GHZ, AR5K_RF5111_DB_2GHZ},
{6, AR5K_RF_OB_5GHZ, AR5K_RF5111_OB_5GHZ},
{6, AR5K_RF_DB_5GHZ, AR5K_RF5111_DB_5GHZ},
{6, AR5K_RF_PWD_XPD, AR5K_RF5111_PWD_XPD},
{6, AR5K_RF_XPD_GAIN, AR5K_RF5111_XPD_GAIN},
{6, AR5K_RF_PWD_84, AR5K_RF5111_PWD(84)},
{6, AR5K_RF_PWD_90, AR5K_RF5111_PWD(90)},
{7, AR5K_RF_GAIN_I, AR5K_RF5111_GAIN_I},
{7, AR5K_RF_PLO_SEL, AR5K_RF5111_PLO_SEL},
{7, AR5K_RF_RFGAIN_SEL, AR5K_RF5111_RFGAIN_SEL},
{7, AR5K_RF_RFGAIN_STEP, AR5K_RF5111_RFGAIN_STEP},
{7, AR5K_RF_WAIT_S, AR5K_RF5111_WAIT_S},
{7, AR5K_RF_WAIT_I, AR5K_RF5111_WAIT_I},
{7, AR5K_RF_MAX_TIME, AR5K_RF5111_MAX_TIME}
};
/* Default mode specific settings */
......@@ -273,8 +315,16 @@ static const struct ath5k_rf_reg rf_regs_5112[] = {
{6, AR5K_RF_FIXED_BIAS_B, AR5K_RF5112_FIXED_BIAS_B},
{6, AR5K_RF_XPD_SEL, AR5K_RF5112_XPD_SEL},
{6, AR5K_RF_XPD_GAIN, AR5K_RF5112_XPD_GAIN},
{6, AR5K_RF_PWD_130, AR5K_RF5112_PWD(130)},
{6, AR5K_RF_PWD_131, AR5K_RF5112_PWD(131)},
{6, AR5K_RF_PWD_132, AR5K_RF5112_PWD(132)},
{6, AR5K_RF_PWD_136, AR5K_RF5112_PWD(136)},
{6, AR5K_RF_PWD_137, AR5K_RF5112_PWD(137)},
{6, AR5K_RF_PWD_138, AR5K_RF5112_PWD(138)},
{7, AR5K_RF_GAIN_I, AR5K_RF5112X_GAIN_I},
{7, AR5K_RF_MIXVGA_OVR, AR5K_RF5112X_MIXVGA_OVR},
{7, AR5K_RF_MIXGAIN_OVR, AR5K_RF5112X_MIXGAIN_OVR},
{7, AR5K_RF_MIXGAIN_STEP, AR5K_RF5112X_MIXGAIN_STEP},
{7, AR5K_RF_PD_DELAY_A, AR5K_RF5112X_PD_DELAY_A},
{7, AR5K_RF_PD_DELAY_B, AR5K_RF5112X_PD_DELAY_B},
{7, AR5K_RF_PD_DELAY_XR, AR5K_RF5112X_PD_DELAY_XR},
......@@ -419,7 +469,7 @@ static const struct ath5k_ini_rfbuffer rfb_5112[] = {
#define AR5K_RF5112A_HIGH_VC_CP { 2, 90, 2 }
#define AR5K_RF5112A_MID_VC_CP { 2, 92, 2 }
#define AR5K_RF5112A_LOW_VC_CP { 2, 94, 2 }
#define AR5K_RF5112A_PUSH_UP { 2, 94, 2 }
#define AR5K_RF5112A_PUSH_UP { 1, 254, 2 }
/* Power consumption */
#define AR5K_RF5112A_PAD2GND { 1, 281, 1 }
......@@ -436,6 +486,14 @@ static const struct ath5k_rf_reg rf_regs_5112a[] = {
{6, AR5K_RF_XPD_SEL, AR5K_RF5112A_XPD_SEL},
{6, AR5K_RF_PD_GAIN_LO, AR5K_RF5112A_PDGAINLO},
{6, AR5K_RF_PD_GAIN_HI, AR5K_RF5112A_PDGAINHI},
{6, AR5K_RF_PWD_130, AR5K_RF5112A_PWD(130)},
{6, AR5K_RF_PWD_131, AR5K_RF5112A_PWD(131)},
{6, AR5K_RF_PWD_132, AR5K_RF5112A_PWD(132)},
{6, AR5K_RF_PWD_136, AR5K_RF5112A_PWD(136)},
{6, AR5K_RF_PWD_137, AR5K_RF5112A_PWD(137)},
{6, AR5K_RF_PWD_138, AR5K_RF5112A_PWD(138)},
{6, AR5K_RF_PWD_166, AR5K_RF5112A_PWD(166)},
{6, AR5K_RF_PWD_167, AR5K_RF5112A_PWD(167)},
{6, AR5K_RF_HIGH_VC_CP, AR5K_RF5112A_HIGH_VC_CP},
{6, AR5K_RF_MID_VC_CP, AR5K_RF5112A_MID_VC_CP},
{6, AR5K_RF_LOW_VC_CP, AR5K_RF5112A_LOW_VC_CP},
......@@ -444,7 +502,9 @@ static const struct ath5k_rf_reg rf_regs_5112a[] = {
{6, AR5K_RF_XB2_LVL, AR5K_RF5112A_XB2_LVL},
{6, AR5K_RF_XB5_LVL, AR5K_RF5112A_XB5_LVL},
{7, AR5K_RF_GAIN_I, AR5K_RF5112X_GAIN_I},
{7, AR5K_RF_MIXVGA_OVR, AR5K_RF5112X_MIXVGA_OVR},
{7, AR5K_RF_MIXGAIN_OVR, AR5K_RF5112X_MIXGAIN_OVR},
{7, AR5K_RF_MIXGAIN_STEP, AR5K_RF5112X_MIXGAIN_STEP},
{7, AR5K_RF_PD_DELAY_A, AR5K_RF5112X_PD_DELAY_A},
{7, AR5K_RF_PD_DELAY_B, AR5K_RF5112X_PD_DELAY_B},
{7, AR5K_RF_PD_DELAY_XR, AR5K_RF5112X_PD_DELAY_XR},
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7