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Commit 89ec9a1d authored by Linus Torvalds's avatar Linus Torvalds
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Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk 

into ppc970.osdl.org:/home/torvalds/v2.6/linux
parents 47fcd4f0 433a3e8e
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Showing with 2776 additions and 1 deletion
arch/arm/Kconfig
View file @ 89ec9a1d
...@@ -167,6 +167,11 @@ config ARCH_VERSATILE_PB ...@@ -167,6 +167,11 @@ config ARCH_VERSATILE_PB
config ARCH_IMX config ARCH_IMX
bool "IMX" bool "IMX"
config ARCH_H720X
bool "Hynix-HMS720x-based"
help
This enables support for systems based on the Hynix HMS720x
endchoice endchoice
source "arch/arm/mach-clps711x/Kconfig" source "arch/arm/mach-clps711x/Kconfig"
...@@ -195,6 +200,8 @@ source "arch/arm/mach-lh7a40x/Kconfig" ...@@ -195,6 +200,8 @@ source "arch/arm/mach-lh7a40x/Kconfig"
source "arch/arm/mach-imx/Kconfig" source "arch/arm/mach-imx/Kconfig"
source "arch/arm/mach-h720x/Kconfig"
# Definitions to make life easier # Definitions to make life easier
config ARCH_ACORN config ARCH_ACORN
bool bool
......
arch/arm/Makefile
View file @ 89ec9a1d
...@@ -95,6 +95,7 @@ textaddr-$(CONFIG_ARCH_FORTUNET) := 0xc0008000 ...@@ -95,6 +95,7 @@ textaddr-$(CONFIG_ARCH_FORTUNET) := 0xc0008000
machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x machine-$(CONFIG_ARCH_LH7A40X) := lh7a40x
machine-$(CONFIG_ARCH_VERSATILE_PB) := versatile machine-$(CONFIG_ARCH_VERSATILE_PB) := versatile
machine-$(CONFIG_ARCH_IMX) := imx machine-$(CONFIG_ARCH_IMX) := imx
machine-$(CONFIG_ARCH_H720X) := h720x
ifeq ($(CONFIG_ARCH_EBSA110),y) ifeq ($(CONFIG_ARCH_EBSA110),y)
# This is what happens if you forget the IOCS16 line. # This is what happens if you forget the IOCS16 line.
......
arch/arm/boot/Makefile
View file @ 89ec9a1d
...@@ -71,6 +71,7 @@ params_phys-$(CONFIG_ARCH_S3C2410) := 0x30000100 ...@@ -71,6 +71,7 @@ params_phys-$(CONFIG_ARCH_S3C2410) := 0x30000100
zreladdr-$(CONFIG_ARCH_VERSATILE_PB) := 0x00008000 zreladdr-$(CONFIG_ARCH_VERSATILE_PB) := 0x00008000
params_phys-$(CONFIG_ARCH_VERSATILE_PB) := 0x00000100 params_phys-$(CONFIG_ARCH_VERSATILE_PB) := 0x00000100
initrd_phys-$(CONFIG_ARCH_VERSATILE_PB) := 0x00800000 initrd_phys-$(CONFIG_ARCH_VERSATILE_PB) := 0x00800000
zreladdr-$(CONFIG_ARCH_H720X) := 0x40008000
ZRELADDR := $(zreladdr-y) ZRELADDR := $(zreladdr-y)
PARAMS_PHYS := $(params_phys-y) PARAMS_PHYS := $(params_phys-y)
......
arch/arm/configs/h7201_defconfig 0 → 100644
View file @ 89ec9a1d
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.9-rc1
# Thu Sep 2 11:04:11 2004
#
CONFIG_ARM=y
CONFIG_MMU=y
CONFIG_UID16=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
#
# Code maturity level options
#
CONFIG_EXPERIMENTAL=y
CONFIG_CLEAN_COMPILE=y
CONFIG_BROKEN_ON_SMP=y
#
# General setup
#
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
# CONFIG_BSD_PROCESS_ACCT is not set
CONFIG_SYSCTL=y
# CONFIG_AUDIT is not set
CONFIG_LOG_BUF_SHIFT=14
CONFIG_HOTPLUG=y
# CONFIG_IKCONFIG is not set
# CONFIG_EMBEDDED is not set
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_FUTEX=y
CONFIG_EPOLL=y
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
#
# Loadable module support
#
CONFIG_MODULES=y
# CONFIG_MODULE_UNLOAD is not set
CONFIG_OBSOLETE_MODPARM=y
# CONFIG_MODVERSIONS is not set
CONFIG_KMOD=y
#
# System Type
#
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_CO285 is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_CAMELOT is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_IOP3XX is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_VERSATILE_PB is not set
# CONFIG_ARCH_IMX is not set
CONFIG_ARCH_H720X=y
#
# h720x Implementations
#
CONFIG_ARCH_H7201=y
# CONFIG_ARCH_H7202 is not set
CONFIG_CPU_H7201=y
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_ARM720T=y
CONFIG_CPU_32v4=y
CONFIG_CPU_ABRT_LV4T=y
CONFIG_CPU_CACHE_V4=y
CONFIG_CPU_COPY_V4WT=y
CONFIG_CPU_TLB_V4WT=y
#
# Processor Features
#
CONFIG_ARM_THUMB=y
#
# General setup
#
# CONFIG_ZBOOT_ROM is not set
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
#
# PCMCIA/CardBus support
#
CONFIG_PCMCIA=y
# CONFIG_PCMCIA_DEBUG is not set
# CONFIG_TCIC is not set
#
# At least one math emulation must be selected
#
CONFIG_FPE_NWFPE=y
# CONFIG_FPE_NWFPE_XP is not set
# CONFIG_FPE_FASTFPE is not set
# CONFIG_VFP is not set
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set
#
# Generic Driver Options
#
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
# CONFIG_FW_LOADER is not set
# CONFIG_PM is not set
# CONFIG_PREEMPT is not set
# CONFIG_ARTHUR is not set
CONFIG_CMDLINE=""
CONFIG_ALIGNMENT_TRAP=y
#
# Parallel port support
#
# CONFIG_PARPORT is not set
#
# Memory Technology Devices (MTD)
#
CONFIG_MTD=y
CONFIG_MTD_DEBUG=y
CONFIG_MTD_DEBUG_VERBOSE=0
CONFIG_MTD_PARTITIONS=y
# CONFIG_MTD_CONCAT is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
# CONFIG_MTD_CMDLINE_PARTS is not set
# CONFIG_MTD_AFS_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_NOSWAP=y
# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
# CONFIG_MTD_CFI_GEOMETRY is not set
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
CONFIG_MTD_CFI_INTELEXT=y
# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
# CONFIG_MTD_PHYSMAP is not set
# CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_EDB7312 is not set
# CONFIG_MTD_H720X is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLKMTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
#
# NAND Flash Device Drivers
#
# CONFIG_MTD_NAND is not set
#
# Plug and Play support
#
#
# Block devices
#
# CONFIG_BLK_DEV_FD is not set
# CONFIG_BLK_DEV_LOOP is not set
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_SIZE=8192
CONFIG_BLK_DEV_INITRD=y
#
# Multi-device support (RAID and LVM)
#
# CONFIG_MD is not set
#
# Networking support
#
# CONFIG_NET is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
#
# SCSI device support
#
# CONFIG_SCSI is not set
#
# Fusion MPT device support
#
#
# IEEE 1394 (FireWire) support
#
#
# I2O device support
#
#
# ISDN subsystem
#
#
# Input device support
#
CONFIG_INPUT=y
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
CONFIG_INPUT_MOUSEDEV_PSAUX=y
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_TSDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input I/O drivers
#
# CONFIG_GAMEPORT is not set
CONFIG_SOUND_GAMEPORT=y
CONFIG_SERIO=y
# CONFIG_SERIO_I8042 is not set
CONFIG_SERIO_SERPORT=y
# CONFIG_SERIO_CT82C710 is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_UNIX98_PTYS=y
CONFIG_LEGACY_PTYS=y
CONFIG_LEGACY_PTY_COUNT=256
# CONFIG_QIC02_TAPE is not set
#
# IPMI
#
# CONFIG_IPMI_HANDLER is not set
#
# Watchdog Cards
#
# CONFIG_WATCHDOG is not set
# CONFIG_NVRAM is not set
# CONFIG_RTC is not set
# CONFIG_GEN_RTC is not set
# CONFIG_DTLK is not set
# CONFIG_R3964 is not set
#
# Ftape, the floppy tape device driver
#
# CONFIG_AGP is not set
# CONFIG_DRM is not set
#
# PCMCIA character devices
#
# CONFIG_SYNCLINK_CS is not set
# CONFIG_RAW_DRIVER is not set
#
# I2C support
#
# CONFIG_I2C is not set
#
# Multimedia devices
#
# CONFIG_VIDEO_DEV is not set
#
# Digital Video Broadcasting Devices
#
#
# File systems
#
CONFIG_EXT2_FS=y
# CONFIG_EXT2_FS_XATTR is not set
# CONFIG_EXT3_FS is not set
# CONFIG_JBD is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_XFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_SYSFS=y
# CONFIG_DEVFS_FS is not set
# CONFIG_DEVPTS_FS_XATTR is not set
# CONFIG_TMPFS is not set
# CONFIG_HUGETLB_PAGE is not set
CONFIG_RAMFS=y
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_JFFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
# CONFIG_JFFS2_FS_NAND is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
#
# Native Language Support
#
# CONFIG_NLS is not set
#
# Profiling support
#
# CONFIG_PROFILING is not set
#
# Graphics support
#
# CONFIG_FB is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
# CONFIG_MDA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
#
# Sound
#
CONFIG_SOUND=m
#
# Advanced Linux Sound Architecture
#
# CONFIG_SND is not set
#
# Open Sound System
#
# CONFIG_SOUND_PRIME is not set
#
# Misc devices
#
#
# USB support
#
#
# USB Gadget Support
#
# CONFIG_USB_GADGET is not set
#
# MMC/SD Card support
#
# CONFIG_MMC is not set
#
# Kernel hacking
#
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_DEBUG_INFO is not set
CONFIG_FRAME_POINTER=y
CONFIG_DEBUG_USER=y
#
# Security options
#
# CONFIG_SECURITY is not set
#
# Cryptographic options
#
# CONFIG_CRYPTO is not set
#
# Library routines
#
# CONFIG_CRC_CCITT is not set
CONFIG_CRC32=y
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
arch/arm/configs/h7202_defconfig 0 → 100644
View file @ 89ec9a1d
This diff is collapsed.
arch/arm/kernel/debug.S
View file @ 89ec9a1d
...@@ -675,6 +675,36 @@ ...@@ -675,6 +675,36 @@
tst \rd, #1 << 3 @ TXDC tst \rd, #1 << 3 @ TXDC
beq 1002b @ wait until transmit done beq 1002b @ wait until transmit done
.endm .endm
#elif defined(CONFIG_ARCH_H720X)
.equ io_virt, IO_BASE
.equ io_phys, IO_START
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
moveq \rx, #io_phys @ physical base address
movne \rx, #io_virt @ virtual address
add \rx, \rx, #0x00020000 @ UART1
.endm
.macro senduart,rd,rx
str \rd, [\rx, #0x0] @ UARTDR
.endm
.macro waituart,rd,rx
1001: ldr \rd, [\rx, #0x18] @ UARTFLG
tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
bne 1001b
.endm
.macro busyuart,rd,rx
1001: ldr \rd, [\rx, #0x18] @ UARTFLG
tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
bne 1001b
.endm
#else #else
#error Unknown architecture #error Unknown architecture
#endif #endif
......
arch/arm/kernel/entry-armv.S
View file @ 89ec9a1d
...@@ -962,6 +962,57 @@ ENTRY(soft_irq_mask) ...@@ -962,6 +962,57 @@ ENTRY(soft_irq_mask)
.macro irq_prio_table .macro irq_prio_table
.endm .endm
#elif defined(CONFIG_ARCH_H720X)
.macro disable_fiq
.endm
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
#if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202)
@ we could use the id register on H7202, but this is not
@ properly updated when we come back from asm_do_irq
@ without a previous return from interrupt
@ (see loops below in irq_svc, irq_usr)
@ We see unmasked pending ints only, as the masked pending ints
@ are not visible here
mov \base, #0xf0000000 @ base register
orr \base, \base, #0x24000 @ irqbase
ldr \irqstat, [\base, #0x04] @ get interrupt status
#if defined (CONFIG_CPU_H7201)
ldr \tmp, =0x001fffff
#else
mvn \tmp, #0xc0000000
#endif
and \irqstat, \irqstat, \tmp @ mask out unused ints
mov \irqnr, #0
mov \tmp, #0xff00
orr \tmp, \tmp, #0xff
tst \irqstat, \tmp
addeq \irqnr, \irqnr, #16
moveq \irqstat, \irqstat, lsr #16
tst \irqstat, #255
addeq \irqnr, \irqnr, #8
moveq \irqstat, \irqstat, lsr #8
tst \irqstat, #15
addeq \irqnr, \irqnr, #4
moveq \irqstat, \irqstat, lsr #4
tst \irqstat, #3
addeq \irqnr, \irqnr, #2
moveq \irqstat, \irqstat, lsr #2
tst \irqstat, #1
addeq \irqnr, \irqnr, #1
moveq \irqstat, \irqstat, lsr #1
tst \irqstat, #1 @ bit 0 should be set
.endm
.macro irq_prio_table
.endm
#else
#error hynix processor selection missmatch
#endif
#else #else
#error Unknown architecture #error Unknown architecture
#endif #endif
......
arch/arm/mach-h720x/Kconfig 0 → 100644
View file @ 89ec9a1d
menu "h720x Implementations"
config ARCH_H7201
bool "gms30c7201"
depends on ARCH_H720X
select CPU_H7201
help
Say Y here if you are using the Hynix GMS30C7201 Reference Board
config ARCH_H7202
bool "hms30c7202"
select CPU_H7202
depends on ARCH_H720X
help
Say Y here if you are using the Hynix HMS30C7202 Reference Board
endmenu
config CPU_H7201
bool
help
Select code specific to h7201 variants
config CPU_H7202
bool
help
Select code specific to h7202 variants
arch/arm/mach-h720x/Makefile 0 → 100644
View file @ 89ec9a1d
#
# Makefile for the linux kernel.
#
# Common support
obj-y := common.o
obj-m :=
obj-n :=
obj- :=
# Specific board support
obj-$(CONFIG_ARCH_H7201) += h7201-eval.o
obj-$(CONFIG_ARCH_H7202) += h7202-eval.o
obj-$(CONFIG_CPU_H7201) += cpu-h7201.o
obj-$(CONFIG_CPU_H7202) += cpu-h7202.o
arch/arm/mach-h720x/common.c 0 → 100644
View file @ 89ec9a1d
/*
* linux/arch/arm/mach-h720x/common.c
*
* Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* 2004 Sascha Hauer <s.hauer@pengutronix.de>
*
* common stuff for Hynix h720x processors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/mman.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/arch/irqs.h>
#include <asm/mach/dma.h>
#if 0
#define IRQDBG(args...) printk(args)
#else
#define IRQDBG(args...) do {} while(0)
#endif
void __init arch_dma_init(dma_t *dma)
{
}
/*
* Return usecs since last timer reload
* (timercount * (usecs perjiffie)) / (ticks per jiffie)
*/
unsigned long h720x_gettimeoffset(void)
{
return (CPU_REG (TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH;
}
/*
* mask Global irq's
*/
static void mask_global_irq (unsigned int irq )
{
CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << irq);
}
/*
* unmask Global irq's
*/
static void unmask_global_irq (unsigned int irq )
{
CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << irq);
}
/*
* ack GPIO irq's
* Ack only for edge triggered int's valid
*/
static void inline ack_gpio_irq(u32 irq)
{
u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
u32 bit = IRQ_TO_BIT(irq);
if ( (CPU_REG (reg_base, GPIO_EDGE) & bit))
CPU_REG (reg_base, GPIO_CLR) = bit;
}
/*
* mask GPIO irq's
*/
static void inline mask_gpio_irq(u32 irq)
{
u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
u32 bit = IRQ_TO_BIT(irq);
CPU_REG (reg_base, GPIO_MASK) &= ~bit;
}
/*
* unmask GPIO irq's
*/
static void inline unmask_gpio_irq(u32 irq)
{
u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(irq));
u32 bit = IRQ_TO_BIT(irq);
CPU_REG (reg_base, GPIO_MASK) |= bit;
}
static void
h720x_gpio_handler(unsigned int mask, unsigned int irq,
struct irqdesc *desc, struct pt_regs *regs)
{
IRQDBG("%s irq: %d\n",__FUNCTION__,irq);
desc = irq_desc + irq;
while (mask) {
if (mask & 1) {
IRQDBG("handling irq %d\n", irq);
desc->handle(irq, desc, regs);
}
irq++;
desc++;
mask >>= 1;
}
}
static void
h720x_gpioa_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
struct pt_regs *regs)
{
unsigned int mask, irq;
mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT);
irq = IRQ_CHAINED_GPIOA(0);
IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
h720x_gpio_handler(mask, irq, desc, regs);
}
static void
h720x_gpiob_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
struct pt_regs *regs)
{
unsigned int mask, irq;
mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
irq = IRQ_CHAINED_GPIOB(0);
IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
h720x_gpio_handler(mask, irq, desc, regs);
}
static void
h720x_gpioc_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
struct pt_regs *regs)
{
unsigned int mask, irq;
mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT);
irq = IRQ_CHAINED_GPIOC(0);
IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
h720x_gpio_handler(mask, irq, desc, regs);
}
static void
h720x_gpiod_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
struct pt_regs *regs)
{
unsigned int mask, irq;
mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT);
irq = IRQ_CHAINED_GPIOD(0);
IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
h720x_gpio_handler(mask, irq, desc, regs);
}
#ifdef CONFIG_CPU_H7202
static void
h720x_gpioe_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
struct pt_regs *regs)
{
unsigned int mask, irq;
mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT);
irq = IRQ_CHAINED_GPIOE(0);
IRQDBG("%s mask: 0x%08x irq: %d\n",__FUNCTION__,mask,irq);
h720x_gpio_handler(mask, irq, desc, regs);
}
#endif
static struct irqchip h720x_global_chip = {
.ack = mask_global_irq,
.mask = mask_global_irq,
.unmask = unmask_global_irq,
};
static struct irqchip h720x_gpio_chip = {
.ack = ack_gpio_irq,
.mask = mask_gpio_irq,
.unmask = unmask_gpio_irq,
};
/*
* Initialize IRQ's, mask all, enable multiplexed irq's
*/
void __init h720x_init_irq (void)
{
int irq;
/* Mask global irq's */
CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0;
/* Mask all multiplexed irq's */
CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0;
CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0;
CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0;
CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0;
/* Initialize global IRQ's, fast path */
for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
set_irq_chip(irq, &h720x_global_chip);
set_irq_handler(irq, do_level_IRQ);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
/* Initialize multiplexed IRQ's, slow path */
for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
set_irq_chip(irq, &h720x_gpio_chip);
set_irq_handler(irq, do_edge_IRQ);
set_irq_flags(irq, IRQF_VALID );
}
set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
#ifdef CONFIG_CPU_H7202
for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
set_irq_chip(irq, &h720x_gpio_chip);
set_irq_handler(irq, do_edge_IRQ);
set_irq_flags(irq, IRQF_VALID );
}
set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
#endif
/* Enable multiplexed irq's */
CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX;
}
static struct map_desc h720x_io_desc[] __initdata = {
{ IO_VIRT, IO_PHYS, IO_SIZE, MT_DEVICE },
};
/* Initialize io tables */
void __init h720x_map_io(void)
{
iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc));
}
arch/arm/mach-h720x/cpu-h7201.c 0 → 100644
View file @ 89ec9a1d
/*
* linux/arch/arm/mach-h720x/cpu-h7201.c
*
* Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* 2004 Sascha Hauer <s.hauer@pengutronix.de>
*
* processor specific stuff for the Hynix h7201
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <asm/types.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/arch/irqs.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
extern unsigned long h720x_gettimeoffset(void);
extern void __init h720x_init_irq (void);
/*
* Timer interrupt handler
*/
static irqreturn_t
h7201_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
timer_tick(regs);
return IRQ_HANDLED;
}
static struct irqaction h7201_timer_irq = {
.name = "h7201 Timer Tick",
.flags = SA_INTERRUPT,
.handler = h7201_timer_interrupt
};
/*
* Setup TIMER0 as system timer
*/
void __init h7201_init_time(void)
{
gettimeoffset = h720x_gettimeoffset;
CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
setup_irq(IRQ_TIMER0, &h7201_timer_irq);
}
arch/arm/mach-h720x/cpu-h7202.c 0 → 100644
View file @ 89ec9a1d
/*
* linux/arch/arm/mach-h720x/cpu-h7202.c
*
* Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* 2004 Sascha Hauer <s.hauer@pengutronix.de>
*
* processor specific stuff for the Hynix h7201
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <asm/types.h>
#include <asm/hardware.h>
#include <asm/irq.h>
#include <asm/arch/irqs.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <linux/device.h>
static struct resource h7202ps2_resources[] = {
[0] = {
.start = 0x8002c000,
.end = 0x8002c040,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_PS2,
.end = IRQ_PS2,
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device h7202ps2_device = {
.name = "h7202ps2",
.id = -1,
.num_resources = ARRAY_SIZE(h7202ps2_resources),
.resource = h7202ps2_resources,
};
static struct platform_device *devices[] __initdata = {
&h7202ps2_device,
};
extern unsigned long h720x_gettimeoffset(void);
extern void __init h720x_init_irq (void);
/* Although we have two interrupt lines for the timers, we only have one
* status register which clears all pending timer interrupts on reading. So
* we have to handle all timer interrupts in one place.
*/
static void
h7202_timerx_demux_handler(unsigned int irq_unused, struct irqdesc *desc,
struct pt_regs *regs)
{
unsigned int mask, irq;
mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
if ( mask & TSTAT_T0INT ) {
timer_tick(regs);
if( mask == TSTAT_T0INT )
return;
}
mask >>= 1;
irq = IRQ_TIMER1;
desc = irq_desc + irq;
while (mask) {
if (mask & 1)
desc->handle(irq, desc, regs);
irq++;
desc++;
mask >>= 1;
}
}
/*
* Timer interrupt handler
*/
static irqreturn_t
h7202_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
h7202_timerx_demux_handler(0, NULL, regs);
return IRQ_HANDLED;
}
/*
* mask multiplexed timer irq's
*/
static void inline mask_timerx_irq (u32 irq)
{
unsigned int bit;
bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
}
/*
* unmask multiplexed timer irq's
*/
static void inline unmask_timerx_irq (u32 irq)
{
unsigned int bit;
bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
}
static struct irqchip h7202_timerx_chip = {
.ack = mask_timerx_irq,
.mask = mask_timerx_irq,
.unmask = unmask_timerx_irq,
};
static struct irqaction h7202_timer_irq = {
.name = "h7202 Timer Tick",
.flags = SA_INTERRUPT,
.handler = h7202_timer_interrupt
};
/*
* Setup TIMER0 as system timer
*/
void __init h7202_init_time(void)
{
gettimeoffset = h720x_gettimeoffset;
CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
setup_irq(IRQ_TIMER0, &h7202_timer_irq);
}
void __init h7202_init_irq (void)
{
int irq;
CPU_REG (GPIO_E_VIRT, GPIO_MASK) = 0x0;
for (irq = IRQ_TIMER1;
irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
mask_timerx_irq(irq);
set_irq_chip(irq, &h7202_timerx_chip);
set_irq_handler(irq, do_edge_IRQ);
set_irq_flags(irq, IRQF_VALID );
}
set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
h720x_init_irq();
}
void __init init_hw_h7202(void)
{
/* Enable clocks */
CPU_REG (PMU_BASE, PMU_PLL_CTRL) |= PLL_2_EN | PLL_1_EN | PLL_3_MUTE;
(void) platform_add_devices(devices, ARRAY_SIZE(devices));
}
arch/arm/mach-h720x/h7201-eval.c 0 → 100644
View file @ 89ec9a1d
/*
* linux/arch/arm/mach-h720x/h7201-eval.c
*
* Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* 2004 Sascha Hauer <s.hauer@pengutronix.de>
*
* Architecture specific stuff for Hynix GMS30C7201 development board
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/device.h>
#include <asm/setup.h>
#include <asm/types.h>
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/mach/arch.h>
#include <asm/hardware.h>
extern void h720x_init_irq (void);
extern void h7201_init_time(void);
extern void __init h720x_map_io(void);
MACHINE_START(H7201, "Hynix GMS30C7201")
MAINTAINER("Robert Schwebel, Pengutronix")
BOOT_MEM(0x40000000, 0x80000000, 0xf0000000)
BOOT_PARAMS(0xc0001000)
MAPIO(h720x_map_io)
INITIRQ(h720x_init_irq)
INITTIME(h7201_init_time)
MACHINE_END
arch/arm/mach-h720x/h7202-eval.c 0 → 100644
View file @ 89ec9a1d
/*
* linux/arch/arm/mach-h720x/h7202-eval.c
*
* Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* 2004 Sascha Hauer <s.hauer@pengutronix.de>
*
* Architecture specific stuff for Hynix HMS30C7202 development board
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <linux/config.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/string.h>
#include <linux/device.h>
#include <asm/setup.h>
#include <asm/types.h>
#include <asm/mach-types.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/mach/arch.h>
#include <asm/hardware.h>
extern void __init init_hw_h7202(void);
extern void __init h7202_init_irq (void);
extern void __init h7202_init_time(void);
extern void __init h720x_map_io(void);
static struct resource cirrus_resources[] = {
[0] = {
.start = ETH0_PHYS + 0x300,
.end = ETH0_PHYS + 0x300 + 0x10,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_CHAINED_GPIOB(8),
.end = IRQ_CHAINED_GPIOB(8),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device cirrus_device = {
.name = "cirrus-cs89x0",
.id = -1,
.num_resources = ARRAY_SIZE(cirrus_resources),
.resource = cirrus_resources,
};
static struct platform_device *devices[] __initdata = {
&cirrus_device,
};
/*
* Hardware init. This is called early in initcalls
* Place pin inits here. So you avoid adding ugly
* #ifdef stuff to common drivers.
* Use this only, if your bootloader is not able
* to initialize the pins proper.
*/
static void __init init_eval_h7202(void)
{
init_hw_h7202();
(void) platform_add_devices(devices, ARRAY_SIZE(devices));
/* Enable interrupt on portb bit 8 (ethernet) */
CPU_REG (GPIO_B_VIRT, GPIO_POL) &= ~(1 << 8);
CPU_REG (GPIO_B_VIRT, GPIO_EN) |= (1 << 8);
}
MACHINE_START(H7202, "Hynix HMS30C7202")
MAINTAINER("Robert Schwebel, Pengutronix")
BOOT_MEM(0x40000000, 0x80000000, 0xf0000000)
BOOT_PARAMS(0x40000100)
MAPIO(h720x_map_io)
INITIRQ(h7202_init_irq)
INITTIME(h7202_init_time)
INIT_MACHINE(init_eval_h7202)
MACHINE_END
arch/arm/mm/Kconfig
View file @ 89ec9a1d
...@@ -43,7 +43,7 @@ config CPU_ARM710 ...@@ -43,7 +43,7 @@ config CPU_ARM710
# ARM720T # ARM720T
config CPU_ARM720T config CPU_ARM720T
bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR bool "Support ARM720T processor" if !ARCH_CLPS711X && !ARCH_L7200 && !ARCH_CDB89712 && ARCH_INTEGRATOR
default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 default y if ARCH_CLPS711X || ARCH_L7200 || ARCH_CDB89712 || ARCH_H720X
select CPU_32v4 select CPU_32v4
select CPU_ABRT_LV4T select CPU_ABRT_LV4T
select CPU_CACHE_V4 select CPU_CACHE_V4
......
include/asm-arm/arch-h720x/boards.h 0 → 100644
View file @ 89ec9a1d
/*
* linux/include/asm-arm/arch-h720x/boards.h
*
* Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
*
* This file contains the board specific defines for various devices
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_HARDWARE_INCMACH_H
#error Do not include this file directly. Include asm/hardware.h instead !
#endif
/* Hynix H7202 developer board specific device defines */
#ifdef CONFIG_ARCH_H7202
/* FLASH */
#define FLASH_VIRT 0xd0000000
#define FLASH_PHYS 0x00000000
#define FLASH_SIZE 0x02000000
/* onboard LAN controller */
# define ETH0_PHYS 0x08000000
/* Touch screen defines */
/* GPIO Port */
#define PEN_GPIO GPIO_B_VIRT
/* Bitmask for pen down interrupt */
#define PEN_INT_BIT (1<<7)
/* Bitmask for pen up interrupt */
#define PEN_ENA_BIT (1<<6)
/* pen up interrupt */
#define IRQ_PEN IRQ_MUX_GPIOB(7)
#endif
/* Hynix H7201 developer board specific device defines */
#if defined (CONFIG_ARCH_H7201)
/* ROM DISK SPACE */
#define ROM_DISK_BASE 0xc1800000
#define ROM_DISK_START 0x41800000
#define ROM_DISK_SIZE 0x00700000
/* SRAM DISK SPACE */
#define SRAM_DISK_BASE 0xf1000000
#define SRAM_DISK_START 0x04000000
#define SRAM_DISK_SIZE 0x00400000
#endif
include/asm-arm/arch-h720x/dma.h 0 → 100644
View file @ 89ec9a1d
/*
* linux/include/asm-arm/arch-h720x/dma.h
*
* Architecture DMA routes
*
* Copyright (C) 1997.1998 Russell King
*/
#ifndef __ASM_ARCH_DMA_H
#define __ASM_ARCH_DMA_H
/*
* This is the maximum DMA address that can be DMAd to.
* There should not be more than (0xd0000000 - 0xc0000000)
* bytes of RAM.
*/
#define MAX_DMA_ADDRESS 0xd0000000
#if defined (CONFIG_CPU_H7201)
#define MAX_DMA_CHANNELS 3
#elif defined (CONFIG_CPU_H7202)
#define MAX_DMA_CHANNELS 4
#else
#error processor definition missmatch
#endif
#endif /* __ASM_ARCH_DMA_H */
include/asm-arm/arch-h720x/h7201-regs.h 0 → 100644
View file @ 89ec9a1d
/*
* linux/include/asm-arm/arch-h720x/h7201-regs.h
*
* Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
* (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* (C) 2004 Sascha Hauer <s.hauer@pengutronix.de>
*
* This file contains the hardware definitions of the h720x processors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Do not add implementations specific defines here. This files contains
* only defines of the onchip peripherals. Add those defines to boards.h,
* which is included by this file.
*/
#define SERIAL2_VIRT (IO_VIRT + 0x50100)
#define SERIAL3_VIRT (IO_VIRT + 0x50200)
/*
* PCMCIA
*/
#define PCMCIA0_ATT_BASE 0xe5000000
#define PCMCIA0_ATT_SIZE 0x00200000
#define PCMCIA0_ATT_START 0x20000000
#define PCMCIA0_MEM_BASE 0xe5200000
#define PCMCIA0_MEM_SIZE 0x00200000
#define PCMCIA0_MEM_START 0x24000000
#define PCMCIA0_IO_BASE 0xe5400000
#define PCMCIA0_IO_SIZE 0x00200000
#define PCMCIA0_IO_START 0x28000000
#define PCMCIA1_ATT_BASE 0xe5600000
#define PCMCIA1_ATT_SIZE 0x00200000
#define PCMCIA1_ATT_START 0x30000000
#define PCMCIA1_MEM_BASE 0xe5800000
#define PCMCIA1_MEM_SIZE 0x00200000
#define PCMCIA1_MEM_START 0x34000000
#define PCMCIA1_IO_BASE 0xe5a00000
#define PCMCIA1_IO_SIZE 0x00200000
#define PCMCIA1_IO_START 0x38000000
#define PRIME3C_BASE 0xf0050000
#define PRIME3C_SIZE 0x00001000
#define PRIME3C_START 0x10000000
/* VGA Controller */
#define VGA_RAMBASE 0x50
#define VGA_TIMING0 0x60
#define VGA_TIMING1 0x64
#define VGA_TIMING2 0x68
#define VGA_TIMING3 0x6c
#define LCD_CTRL_VGA_ENABLE 0x00000100
#define LCD_CTRL_VGA_BPP_MASK 0x00000600
#define LCD_CTRL_VGA_4BPP 0x00000000
#define LCD_CTRL_VGA_8BPP 0x00000200
#define LCD_CTRL_VGA_16BPP 0x00000300
#define LCD_CTRL_SHARE_DMA 0x00000800
#define LCD_CTRL_VDE 0x00100000
#define LCD_CTRL_LPE 0x00400000 /* LCD Power enable */
#define LCD_CTRL_BLE 0x00800000 /* LCD backlight enable */
#define VGA_PALETTE_BASE (IO_VIRT + 0x10800)
include/asm-arm/arch-h720x/h7202-regs.h 0 → 100644
View file @ 89ec9a1d
/*
* linux/include/asm-arm/arch-h720x/h7202-regs.h
*
* Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
* (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* (C) 2004 Sascha Hauer <s.hauer@pengutronix.de>
*
* This file contains the hardware definitions of the h720x processors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Do not add implementations specific defines here. This files contains
* only defines of the onchip peripherals. Add those defines to boards.h,
* which is included by this file.
*/
#define SERIAL2_VIRT (IO_VIRT + 0x2d000)
#define SERIAL3_VIRT (IO_VIRT + 0x2e000)
/* Matrix Keyboard Controller */
#define KBD_VIRT (IO_VIRT + 0x22000)
#define KBD_KBCR 0x00
#define KBD_KBSC 0x04
#define KBD_KBTR 0x08
#define KBD_KBVR0 0x0C
#define KBD_KBVR1 0x10
#define KBD_KBSR 0x18
#define KBD_KBCR_SCANENABLE (1 << 7)
#define KBD_KBCR_NPOWERDOWN (1 << 2)
#define KBD_KBCR_CLKSEL_MASK (3)
#define KBD_KBCR_CLKSEL_PCLK2 0x0
#define KBD_KBCR_CLKSEL_PCLK128 0x1
#define KBD_KBCR_CLKSEL_PCLK256 0x2
#define KBD_KBCR_CLKSEL_PCLK512 0x3
#define KBD_KBSR_INTR (1 << 0)
#define KBD_KBSR_WAKEUP (1 << 1)
/* USB device controller */
#define USBD_BASE (IO_VIRT + 0x12000)
#define USBD_LENGTH 0x3C
#define USBD_GCTRL 0x00
#define USBD_EPCTRL 0x04
#define USBD_INTMASK 0x08
#define USBD_INTSTAT 0x0C
#define USBD_PWR 0x10
#define USBD_DMARXTX 0x14
#define USBD_DEVID 0x18
#define USBD_DEVCLASS 0x1C
#define USBD_INTCLASS 0x20
#define USBD_SETUP0 0x24
#define USBD_SETUP1 0x28
#define USBD_ENDP0RD 0x2C
#define USBD_ENDP0WT 0x30
#define USBD_ENDP1RD 0x34
#define USBD_ENDP2WT 0x38
/* PS/2 port */
#define PSDATA 0x00
#define PSSTAT 0x04
#define PSSTAT_TXEMPTY (1<<0)
#define PSSTAT_TXBUSY (1<<1)
#define PSSTAT_RXFULL (1<<2)
#define PSSTAT_RXBUSY (1<<3)
#define PSSTAT_CLKIN (1<<4)
#define PSSTAT_DATAIN (1<<5)
#define PSSTAT_PARITY (1<<6)
#define PSCONF 0x08
#define PSCONF_ENABLE (1<<0)
#define PSCONF_TXINTEN (1<<2)
#define PSCONF_RXINTEN (1<<3)
#define PSCONF_FORCECLKLOW (1<<4)
#define PSCONF_FORCEDATLOW (1<<5)
#define PSCONF_LCE (1<<6)
#define PSINTR 0x0C
#define PSINTR_TXINT (1<<0)
#define PSINTR_RXINT (1<<1)
#define PSINTR_PAR (1<<2)
#define PSINTR_RXTO (1<<3)
#define PSINTR_TXTO (1<<4)
#define PSTDLO 0x10 /* clk low before start transmission */
#define PSTPRI 0x14 /* PRI clock */
#define PSTXMT 0x18 /* maximum transmission time */
#define PSTREC 0x20 /* maximum receive time */
#define PSPWDN 0x3c
/* ADC converter */
#define ADC_BASE (IO_VIRT + 0x29000)
#define ADC_CR 0x00
#define ADC_TSCTRL 0x04
#define ADC_BT_CTRL 0x08
#define ADC_MC_CTRL 0x0C
#define ADC_STATUS 0x10
/* ADC control register bits */
#define ADC_CR_PW_CTRL 0x80
#define ADC_CR_DIRECTC 0x04
#define ADC_CR_CONTIME_NO 0x00
#define ADC_CR_CONTIME_2 0x04
#define ADC_CR_CONTIME_4 0x08
#define ADC_CR_CONTIME_ADE 0x0c
#define ADC_CR_LONGCALTIME 0x01
/* ADC touch panel register bits */
#define ADC_TSCTRL_ENABLE 0x80
#define ADC_TSCTRL_INTR 0x40
#define ADC_TSCTRL_SWBYPSS 0x20
#define ADC_TSCTRL_SWINVT 0x10
#define ADC_TSCTRL_S400 0x03
#define ADC_TSCTRL_S200 0x02
#define ADC_TSCTRL_S100 0x01
#define ADC_TSCTRL_S50 0x00
/* ADC Interrupt Status Register bits */
#define ADC_STATUS_TS_BIT 0x80
#define ADC_STATUS_MBT_BIT 0x40
#define ADC_STATUS_BBT_BIT 0x20
#define ADC_STATUS_MIC_BIT 0x10
/* Touch data registers */
#define ADC_TS_X0X1 0x30
#define ADC_TS_X2X3 0x34
#define ADC_TS_Y0Y1 0x38
#define ADC_TS_Y2Y3 0x3c
#define ADC_TS_X4X5 0x40
#define ADC_TS_X6X7 0x44
#define ADC_TS_Y4Y5 0x48
#define ADC_TS_Y6Y7 0x50
/* battery data */
#define ADC_MB_DATA 0x54
#define ADC_BB_DATA 0x58
/* Sound data register */
#define ADC_SD_DAT0 0x60
#define ADC_SD_DAT1 0x64
#define ADC_SD_DAT2 0x68
#define ADC_SD_DAT3 0x6c
#define ADC_SD_DAT4 0x70
#define ADC_SD_DAT5 0x74
#define ADC_SD_DAT6 0x78
#define ADC_SD_DAT7 0x7c
include/asm-arm/arch-h720x/hardware.h 0 → 100644
View file @ 89ec9a1d
/*
* linux/include/asm-arm/arch-h720x/hardware.h
*
* Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
* (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
*
* This file contains the hardware definitions of the h720x processors
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Do not add implementations specific defines here. This files contains
* only defines of the onchip peripherals. Add those defines to boards.h,
* which is included by this file.
*/
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#define IOCLK (3686400L)
/* Onchip peripherals */
#define IO_VIRT 0xf0000000 /* IO peripherals */
#define IO_PHYS 0x80000000
#define IO_SIZE 0x00050000
#ifdef CONFIG_CPU_H7202
#include "h7202-regs.h"
#elif defined CONFIG_CPU_H7201
#include "h7201-regs.h"
#else
#error machine definition mismatch
#endif
/* Macro to access the CPU IO */
#define CPU_IO(x) (*(volatile u32*)(x))
/* Macro to access general purpose regs (base, offset) */
#define CPU_REG(x,y) CPU_IO(x+y)
/* Macro to access irq related regs */
#define IRQ_REG(x) CPU_REG(IRQC_VIRT,x)
/* CPU registers */
/* general purpose I/O */
#define GPIO_VIRT(x) (IO_VIRT + 0x23000 + ((x)<<5))
#define GPIO_A_VIRT (GPIO_VIRT(0))
#define GPIO_B_VIRT (GPIO_VIRT(1))
#define GPIO_C_VIRT (GPIO_VIRT(2))
#define GPIO_D_VIRT (GPIO_VIRT(3))
#define GPIO_E_VIRT (GPIO_VIRT(4))
#define GPIO_AMULSEL (GPIO_VIRT + 0xA4)
/* Register offsets general purpose I/O */
#define GPIO_DATA 0x00
#define GPIO_DIR 0x04
#define GPIO_MASK 0x08
#define GPIO_STAT 0x0C
#define GPIO_EDGE 0x10
#define GPIO_CLR 0x14
#define GPIO_POL 0x18
#define GPIO_EN 0x1C
/*interrupt controller */
#define IRQC_VIRT (IO_VIRT + 0x24000)
/* register offset interrupt controller */
#define IRQC_IER 0x00
#define IRQC_ISR 0x04
/* timer unit */
#define TIMER_VIRT (IO_VIRT + 0x25000)
/* Register offsets timer unit */
#define TM0_PERIOD 0x00
#define TM0_COUNT 0x08
#define TM0_CTRL 0x10
#define TM1_PERIOD 0x20
#define TM1_COUNT 0x28
#define TM1_CTRL 0x30
#define TM2_PERIOD 0x40
#define TM2_COUNT 0x48
#define TM2_CTRL 0x50
#define TIMER_TOPCTRL 0x60
#define TIMER_TOPSTAT 0x64
#define T64_COUNTL 0x80
#define T64_COUNTH 0x84
#define T64_CTRL 0x88
#define T64_BASEL 0x94
#define T64_BASEH 0x98
/* Bitmaks timer unit TOPSTAT reg */
#define TSTAT_T0INT 0x1
#define TSTAT_T1INT 0x2
#define TSTAT_T2INT 0x4
#define TSTAT_T3INT 0x8
/* Bit description of TMx_CTRL register */
#define TM_START 0x1
#define TM_REPEAT 0x2
#define TM_RESET 0x4
/* Bit description of TIMER_CTRL register */
#define ENABLE_TM0_INTR 0x1
#define ENABLE_TM1_INTR 0x2
#define ENABLE_TM2_INTR 0x4
#define TIMER_ENABLE_BIT 0x8
#define ENABLE_TIMER64 0x10
#define ENABLE_TIMER64_INT 0x20
/* PMU & PLL */
#define PMU_BASE (IO_VIRT + 0x1000)
#define PMU_MODE 0x00
#define PMU_STAT 0x20
#define PMU_PLL_CTRL 0x28
/* PMU Mode bits */
#define PMU_MODE_SLOW 0x00
#define PMU_MODE_RUN 0x01
#define PMU_MODE_IDLE 0x02
#define PMU_MODE_SLEEP 0x03
#define PMU_MODE_INIT 0x04
#define PMU_MODE_DEEPSLEEP 0x07
#define PMU_MODE_WAKEUP 0x08
/* PMU ... */
#define PLL_2_EN 0x8000
#define PLL_1_EN 0x4000
#define PLL_3_MUTE 0x0080
/* Control bits for PMU/ PLL */
#define PMU_WARMRESET 0x00010000
#define PLL_CTRL_MASK23 0x000080ff
/* LCD Controller */
#define LCD_BASE (IO_VIRT + 0x10000)
#define LCD_CTRL 0x00
#define LCD_STATUS 0x04
#define LCD_STATUS_M 0x08
#define LCD_INTERRUPT 0x0C
#define LCD_DBAR 0x10
#define LCD_DCAR 0x14
#define LCD_TIMING0 0x20
#define LCD_TIMING1 0x24
#define LCD_TIMING2 0x28
#define LCD_TEST 0x40
/* LCD Control Bits */
#define LCD_CTRL_LCD_ENABLE 0x00000001
/* Bits per pixel */
#define LCD_CTRL_LCD_BPP_MASK 0x00000006
#define LCD_CTRL_LCD_4BPP 0x00000000
#define LCD_CTRL_LCD_8BPP 0x00000002
#define LCD_CTRL_LCD_16BPP 0x00000004
#define LCD_CTRL_LCD_BW 0x00000008
#define LCD_CTRL_LCD_TFT 0x00000010
#define LCD_CTRL_BGR 0x00001000
#define LCD_CTRL_LCD_VCOMP 0x00080000
#define LCD_CTRL_LCD_MONO8 0x00200000
#define LCD_CTRL_LCD_PWR 0x00400000
#define LCD_CTRL_LCD_BLE 0x00800000
#define LCD_CTRL_LDBUSEN 0x01000000
/* Palette */
#define LCD_PALETTE_BASE (IO_VIRT + 0x10400)
/* Serial ports */
#define SERIAL0_VIRT (IO_VIRT + 0x20000)
#define SERIAL1_VIRT (IO_VIRT + 0x21000)
#define SERIAL0_BASE SERIAL0_VIRT
#define SERIAL1_BASE SERIAL1_VIRT
#define SERIAL2_BASE SERIAL2_VIRT
#define SERIAL3_BASE SERIAL3_VIRT
/* General defines to pacify gcc */
#define PCIO_BASE (0) /* for inb, outb and friends */
#define PCIO_VIRT PCIO_BASE
#define __ASM_ARCH_HARDWARE_INCMACH_H
#include "boards.h"
#undef __ASM_ARCH_HARDWARE_INCMACH_H
#endif /* __ASM_ARCH_HARDWARE_H */
include/asm-arm/arch-h720x/io.h 0 → 100644
View file @ 89ec9a1d
/*
* linux/include/asm-arm/arch-h720x/io.h
*
* Copyright (C) 2000 Steve Hill (sjhill@cotw.com)
*
* Changelog:
*
* 09-19-2001 JJKIM
* Created from linux/include/asm-arm/arch-l7200/io.h
*
* 03-27-2003 Robert Schwebel <r.schwebel@pengutronix.de>:
* re-unified header files for h720x
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#include <asm/arch/hardware.h>
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) (a)
#define __mem_pci(a) (a)
#endif
include/asm-arm/arch-h720x/irq.h 0 → 100644
View file @ 89ec9a1d
/*
* include/asm-arm/arch-h720x/irq.h
*
* Copyright (C) 2000-2002 Jungjun Kim
* (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* (C) 2003 Thomas Gleixner <tglx@linutronix.de>
*/
#ifndef __ASM_ARCH_IRQ_H
#define __ASM_ARCH_IRQ_H
extern void __init h720x_init_irq (void);
#endif /* __ASM_ARCH_IRQ_H */
include/asm-arm/arch-h720x/irqs.h 0 → 100644
View file @ 89ec9a1d
/*
* linux/include/asm-arm/arch-h720x/irqs.h
*
* Copyright (C) 2000 Jungjun Kim
* (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
* (C) 2003 Thomas Gleixner <tglx@linutronix.de>
*
*/
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#if defined (CONFIG_CPU_H7201)
#define IRQ_PMU 0 /* 0x000001 */
#define IRQ_DMA 1 /* 0x000002 */
#define IRQ_LCD 2 /* 0x000004 */
#define IRQ_VGA 3 /* 0x000008 */
#define IRQ_PCMCIA1 4 /* 0x000010 */
#define IRQ_PCMCIA2 5 /* 0x000020 */
#define IRQ_AFE 6 /* 0x000040 */
#define IRQ_AIC 7 /* 0x000080 */
#define IRQ_KEYBOARD 8 /* 0x000100 */
#define IRQ_TIMER0 9 /* 0x000200 */
#define IRQ_RTC 10 /* 0x000400 */
#define IRQ_SOUND 11 /* 0x000800 */
#define IRQ_USB 12 /* 0x001000 */
#define IRQ_IrDA 13 /* 0x002000 */
#define IRQ_UART0 14 /* 0x004000 */
#define IRQ_UART1 15 /* 0x008000 */
#define IRQ_SPI 16 /* 0x010000 */
#define IRQ_GPIOA 17 /* 0x020000 */
#define IRQ_GPIOB 18 /* 0x040000 */
#define IRQ_GPIOC 19 /* 0x080000 */
#define IRQ_GPIOD 20 /* 0x100000 */
#define IRQ_CommRX 21 /* 0x200000 */
#define IRQ_CommTX 22 /* 0x400000 */
#define IRQ_Soft 23 /* 0x800000 */
#define NR_GLBL_IRQS 24
#define IRQ_CHAINED_GPIOA(x) (NR_GLBL_IRQS + x)
#define IRQ_CHAINED_GPIOB(x) (IRQ_CHAINED_GPIOA(32) + x)
#define IRQ_CHAINED_GPIOC(x) (IRQ_CHAINED_GPIOB(32) + x)
#define IRQ_CHAINED_GPIOD(x) (IRQ_CHAINED_GPIOC(32) + x)
#define NR_IRQS IRQ_CHAINED_GPIOD(32)
/* Enable mask for multiplexed interrupts */
#define IRQ_ENA_MUX (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) \
| (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD)
#elif defined (CONFIG_CPU_H7202)
#define IRQ_PMU 0 /* 0x00000001 */
#define IRQ_DMA 1 /* 0x00000002 */
#define IRQ_LCD 2 /* 0x00000004 */
#define IRQ_SOUND 3 /* 0x00000008 */
#define IRQ_I2S 4 /* 0x00000010 */
#define IRQ_USB 5 /* 0x00000020 */
#define IRQ_MMC 6 /* 0x00000040 */
#define IRQ_RTC 7 /* 0x00000080 */
#define IRQ_UART0 8 /* 0x00000100 */
#define IRQ_UART1 9 /* 0x00000200 */
#define IRQ_UART2 10 /* 0x00000400 */
#define IRQ_UART3 11 /* 0x00000800 */
#define IRQ_KBD 12 /* 0x00001000 */
#define IRQ_PS2 13 /* 0x00002000 */
#define IRQ_AIC 14 /* 0x00004000 */
#define IRQ_TIMER0 15 /* 0x00008000 */
#define IRQ_TIMERX 16 /* 0x00010000 */
#define IRQ_WDT 17 /* 0x00020000 */
#define IRQ_CAN0 18 /* 0x00040000 */
#define IRQ_CAN1 19 /* 0x00080000 */
#define IRQ_EXT0 20 /* 0x00100000 */
#define IRQ_EXT1 21 /* 0x00200000 */
#define IRQ_GPIOA 22 /* 0x00400000 */
#define IRQ_GPIOB 23 /* 0x00800000 */
#define IRQ_GPIOC 24 /* 0x01000000 */
#define IRQ_GPIOD 25 /* 0x02000000 */
#define IRQ_GPIOE 26 /* 0x04000000 */
#define IRQ_COMMRX 27 /* 0x08000000 */
#define IRQ_COMMTX 28 /* 0x10000000 */
#define IRQ_SMC 29 /* 0x20000000 */
#define IRQ_Soft 30 /* 0x40000000 */
#define IRQ_RESERVED1 31 /* 0x80000000 */
#define NR_GLBL_IRQS 32
#define NR_TIMERX_IRQS 3
#define IRQ_CHAINED_GPIOA(x) (NR_GLBL_IRQS + x)
#define IRQ_CHAINED_GPIOB(x) (IRQ_CHAINED_GPIOA(32) + x)
#define IRQ_CHAINED_GPIOC(x) (IRQ_CHAINED_GPIOB(32) + x)
#define IRQ_CHAINED_GPIOD(x) (IRQ_CHAINED_GPIOC(32) + x)
#define IRQ_CHAINED_GPIOE(x) (IRQ_CHAINED_GPIOD(32) + x)
#define IRQ_CHAINED_TIMERX(x) (IRQ_CHAINED_GPIOE(32) + x)
#define IRQ_TIMER1 (IRQ_CHAINED_TIMERX(0))
#define IRQ_TIMER2 (IRQ_CHAINED_TIMERX(1))
#define IRQ_TIMER64B (IRQ_CHAINED_TIMERX(2))
#define NR_IRQS (IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS))
/* Enable mask for multiplexed interrupts */
#define IRQ_ENA_MUX (1<<IRQ_TIMERX) | (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) | \
(1<<IRQ_GPIOC) | (1<<IRQ_GPIOD) | (1<<IRQ_GPIOE) | \
(1<<IRQ_TIMERX)
#else
#error cpu definition mismatch
#endif
/* decode irq number to register number */
#define IRQ_TO_REGNO(irq) ((irq - NR_GLBL_IRQS) >> 5)
#define IRQ_TO_BIT(irq) (1 << ((irq - NR_GLBL_IRQS) % 32))
#endif
include/asm-arm/arch-h720x/memory.h 0 → 100644
View file @ 89ec9a1d
/*
* linux/include/asm-arm/arch-h720x/memory.h
*
* Copyright (c) 2000 Jungjun Kim
*
*/
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
/*
* Page offset:
* ( 0xc0000000UL )
*/
#define PHYS_OFFSET (0x40000000UL)
/*
* Virtual view <-> DMA view memory address translations
* virt_to_bus: Used to translate the virtual address to an
* address suitable to be passed to set_dma_addr
* bus_to_virt: Used to convert an address for DMA operations
* to an address that the kernel can use.
*
* There is something to do here later !, Mar 2000, Jungjun Kim
*/
#define __virt_to_bus__is_a_macro
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt__is_a_macro
#define __bus_to_virt(x) __phys_to_virt(x)
#endif
include/asm-arm/arch-h720x/param.h 0 → 100644
View file @ 89ec9a1d
/*
* linux/include/asm-arm/arch-h720x/param.h
*
* Copyright (C) 2000 Jungjun Kim
*/
#ifndef __ASM_ARCH_PARAM_H
#define __ASM_ARCH_PARAM_H
#endif
include/asm-arm/arch-h720x/serial.h 0 → 100644
View file @ 89ec9a1d
/*
* linux/include/asm-arm/arch-h72x/serial.h
*
* Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
* 2003 Robert Schwebel <r.schwebel@pengutronix.de>
*
* Serial port setup for Hynix boards
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __ASM_ARCH_SERIAL_H
#define __ASM_ARCH_SERIAL_H
#include <asm/arch/irqs.h>
/*
* Standard COM flags
*/
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
#define RS_TABLE_SIZE
/* Base clock is 3.6864 MHz */
#define BASE_BAUD (115200*2)
#define EXTRA_SERIAL_PORT_DEFNS
/*
* Board dependend defines
*/
#if defined (CONFIG_CPU_H7201)
#define BASE_BAUD_P3C (115200)
#define STD_SERIAL_PORT_DEFNS \
{ \
.baud_base = BASE_BAUD, \
.port = SERIAL0_BASE, \
.iomem_base = (u8*)SERIAL0_BASE, \
.io_type = UPIO_MEM, \
.irq = IRQ_UART0, \
.flags = STD_COM_FLAGS, \
.iomem_reg_shift = 2,\
}, \
{ \
.baud_base = BASE_BAUD, \
.port = SERIAL1_BASE, \
.iomem_base = (u8*)SERIAL1_BASE, \
.io_type = UPIO_MEM, \
.irq = IRQ_UART1, \
.flags = STD_COM_FLAGS, \
.iomem_reg_shift = 2,\
}
#elif defined (CONFIG_CPU_H7202)
#define STD_SERIAL_PORT_DEFNS \
{ \
.baud_base = BASE_BAUD, \
.port = SERIAL0_BASE, \
.iomem_base = (u8*)SERIAL0_BASE, \
.io_type = UPIO_MEM, \
.irq = IRQ_UART0, \
.flags = STD_COM_FLAGS, \
.iomem_reg_shift = 2,\
}, \
{ \
.baud_base = BASE_BAUD, \
.port = SERIAL1_BASE, \
.iomem_base = (u8*)SERIAL1_BASE, \
.io_type = UPIO_MEM, \
.irq = IRQ_UART1, \
.flags = STD_COM_FLAGS, \
.iomem_reg_shift = 2,\
}, \
{ \
.baud_base = BASE_BAUD, \
.port = SERIAL2_BASE, \
.iomem_base = (u8*)SERIAL2_BASE, \
.io_type = UPIO_MEM, \
.irq = IRQ_UART2, \
.flags = STD_COM_FLAGS, \
.iomem_reg_shift = 2,\
}, \
{ \
.baud_base = BASE_BAUD, \
.port = SERIAL3_BASE, \
.iomem_base = (u8*)SERIAL3_BASE, \
.io_type = UPIO_MEM, \
.irq = IRQ_UART3, \
.flags = STD_COM_FLAGS, \
.iomem_reg_shift = 2,\
}
#else
#error machine definition mismatch
#endif
/* __ASM_ARCH_SERIAL_H */
#endif
include/asm-arm/arch-h720x/system.h 0 → 100644
View file @ 89ec9a1d
/*
* linux/arch/arm/mach-h720x/system.h
*
* Copyright (C) 2001-2002 Jungjun Kim, Hynix Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
* linux/include/asm-arm/arch-h720x/system.h
*
*/
#ifndef __ASM_ARCH_SYSTEM_H
#define __ASM_ARCH_SYSTEM_H
#include <asm/hardware.h>
static void arch_idle(void)
{
CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
__asm__ __volatile__(
"mov r0, r0\n\t"
"mov r0, r0");
}
static __inline__ void arch_reset(char mode)
{
CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
}
#endif
include/asm-arm/arch-h720x/timex.h 0 → 100644
View file @ 89ec9a1d
/*
* linux/include/asm-arm/arch-h720x/timex.h
* Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_TIMEX
#define __ASM_ARCH_TIMEX
#define CLOCK_TICK_RATE 3686400
#endif
include/asm-arm/arch-h720x/uncompress.h 0 → 100644
View file @ 89ec9a1d
/*
* linux/include/asm-arm/arch-h720x/uncompress.h
*
* Copyright (C) 2001-2002 Jungjun Kim
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H
#include <asm/arch/hardware.h>
#define LSR 0x14
#define TEMPTY 0x40
static void putstr(const char *s)
{
char c;
volatile unsigned char *p = (volatile unsigned char *)(IO_PHYS+0x20000);
while ( (c = *s++) != '\0') {
/* wait until transmit buffer is empty */
while((p[LSR] & TEMPTY) == 0x0);
/* write next character */
*p = c;
if(c == '\n') {
while((p[LSR] & TEMPTY) == 0x0);
*p = '\r';
}
}
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()
#endif
include/asm-arm/arch-h720x/vmalloc.h 0 → 100644
View file @ 89ec9a1d
/*
* linux/include/asm-arm/arch-h720x/vmalloc.h
*/
#ifndef __ARCH_ARM_VMALLOC_H
#define __ARCH_ARM_VMALLOC_H
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
#endif
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