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Commit 8ae112a5 authored by Cristian Ciocaltea's avatar Cristian Ciocaltea Committed by Heiko Stuebner
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arm64: dts: rockchip: Add rk3588s I2S nodes 

There are five I2S/PCM/TDM controllers and two I2S/PCM controllers
embedded in the RK3588 and RK3588S SoCs.

Add the DT nodes corresponding to the above mentioned Rockchip
controllers.

Also note RK3588 SoC contains four additional I2S/PCM/TDM controllers,
which are handled via a separate patch.
Signed-off-by: default avatarCristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20230402095054.384739-4-cristian.ciocaltea@collabora.comSigned-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent b46a22de
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arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View file @ 8ae112a5
......@@ -812,6 +812,57 @@ power-domain@RK3588_PD_SDMMC {
};
};
i2s4_8ch: i2s@fddc0000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddc0000 0x0 0x1000>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 0>;
dma-names = "tx";
power-domains = <&power RK3588_PD_VO0>;
resets = <&cru SRST_M_I2S4_8CH_TX>;
reset-names = "tx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
i2s5_8ch: i2s@fddf0000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddf0000 0x0 0x1000>;
interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 2>;
dma-names = "tx";
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_M_I2S5_8CH_TX>;
reset-names = "tx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
i2s9_8ch: i2s@fddfc000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfddfc000 0x0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac2 23>;
dma-names = "rx";
power-domains = <&power RK3588_PD_VO1>;
resets = <&cru SRST_M_I2S9_8CH_RX>;
reset-names = "rx-m";
#sound-dai-cells = <0>;
status = "disabled";
};
qos_gpu_m0: qos@fdf35000 {
compatible = "rockchip,rk3588-qos", "syscon";
reg = <0x0 0xfdf35000 0x0 0x20>;
......@@ -1134,6 +1185,103 @@ sdhci: mmc@fe2e0000 {
status = "disabled";
};
i2s0_8ch: i2s@fe470000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfe470000 0x0 0x1000>;
interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
dmas = <&dmac0 0>, <&dmac0 1>;
dma-names = "tx", "rx";
power-domains = <&power RK3588_PD_AUDIO>;
resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
reset-names = "tx-m", "rx-m";
rockchip,trcm-sync-tx-only;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_lrck
&i2s0_sclk
&i2s0_sdi0
&i2s0_sdi1
&i2s0_sdi2
&i2s0_sdi3
&i2s0_sdo0
&i2s0_sdo1
&i2s0_sdo2
&i2s0_sdo3>;
#sound-dai-cells = <0>;
status = "disabled";
};
i2s1_8ch: i2s@fe480000 {
compatible = "rockchip,rk3588-i2s-tdm";
reg = <0x0 0xfe480000 0x0 0x1000>;
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
clock-names = "mclk_tx", "mclk_rx", "hclk";
dmas = <&dmac0 2>, <&dmac0 3>;
dma-names = "tx", "rx";
resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
reset-names = "tx-m", "rx-m";
rockchip,trcm-sync-tx-only;
pinctrl-names = "default";
pinctrl-0 = <&i2s1m0_lrck
&i2s1m0_sclk
&i2s1m0_sdi0
&i2s1m0_sdi1
&i2s1m0_sdi2
&i2s1m0_sdi3
&i2s1m0_sdo0
&i2s1m0_sdo1
&i2s1m0_sdo2
&i2s1m0_sdo3>;
#sound-dai-cells = <0>;
status = "disabled";
};
i2s2_2ch: i2s@fe490000 {
compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xfe490000 0x0 0x1000>;
interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
clock-names = "i2s_clk", "i2s_hclk";
assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac1 0>, <&dmac1 1>;
dma-names = "tx", "rx";
power-domains = <&power RK3588_PD_AUDIO>;
rockchip,trcm-sync-tx-only;
pinctrl-names = "default";
pinctrl-0 = <&i2s2m1_lrck
&i2s2m1_sclk
&i2s2m1_sdi
&i2s2m1_sdo>;
#sound-dai-cells = <0>;
status = "disabled";
};
i2s3_2ch: i2s@fe4a0000 {
compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
reg = <0x0 0xfe4a0000 0x0 0x1000>;
interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
clock-names = "i2s_clk", "i2s_hclk";
assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
assigned-clock-parents = <&cru PLL_AUPLL>;
dmas = <&dmac1 2>, <&dmac1 3>;
dma-names = "tx", "rx";
power-domains = <&power RK3588_PD_AUDIO>;
rockchip,trcm-sync-tx-only;
pinctrl-names = "default";
pinctrl-0 = <&i2s3_lrck
&i2s3_sclk
&i2s3_sdi
&i2s3_sdo>;
#sound-dai-cells = <0>;
status = "disabled";
};
gic: interrupt-controller@fe600000 {
compatible = "arm,gic-v3";
reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
......
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