Commit 8c1ee96a authored by Shunli Wang's avatar Shunli Wang Committed by Stephen Boyd

reset: mediatek: Add MT2701 reset driver

In infrasys and perifsys, there are many reset
control bits for kinds of modules. These bits are
used as actual reset controllers to be registered
into kernel's generic reset controller framework.
Signed-off-by: default avatarShunli Wang <shunli.wang@mediatek.com>
Signed-off-by: default avatarJames Liao <jamesjj.liao@mediatek.com>
Signed-off-by: default avatarErin Lo <erin.lo@mediatek.com>
Tested-by: default avatarJohn Crispin <blogic@openwrt.org>
Acked-by: default avatarPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent e9862118
...@@ -58,12 +58,16 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev) ...@@ -58,12 +58,16 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev)
clk_data); clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r) if (r) {
dev_err(&pdev->dev, dev_err(&pdev->dev,
"could not register clock provider: %s: %d\n", "could not register clock provider: %s: %d\n",
pdev->name, r); pdev->name, r);
return r;
}
mtk_register_reset_controller(node, 1, 0x34);
return r; return 0;
} }
static struct platform_driver clk_mt2701_hif_drv = { static struct platform_driver clk_mt2701_hif_drv = {
......
...@@ -787,8 +787,12 @@ static int mtk_infrasys_init(struct platform_device *pdev) ...@@ -787,8 +787,12 @@ static int mtk_infrasys_init(struct platform_device *pdev)
infra_clk_data); infra_clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
if (r)
return r;
return r; mtk_register_reset_controller(node, 2, 0x30);
return 0;
} }
static const struct mtk_gate_regs peri0_cg_regs = { static const struct mtk_gate_regs peri0_cg_regs = {
...@@ -906,8 +910,12 @@ static int mtk_pericfg_init(struct platform_device *pdev) ...@@ -906,8 +910,12 @@ static int mtk_pericfg_init(struct platform_device *pdev)
&mt2701_clk_lock, clk_data); &mt2701_clk_lock, clk_data);
r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data); r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
if (r)
return r;
return r; mtk_register_reset_controller(node, 2, 0x0);
return 0;
} }
#define MT8590_PLL_FMAX (2000 * MHZ) #define MT8590_PLL_FMAX (2000 * MHZ)
......
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