Commit 8cd6d3c2 authored by Balbir Singh's avatar Balbir Singh Committed by Michael Ellerman

powerpc/mm: Fix .long's in tlb-radix.c to more meaningful

The .longs with the shifts are harder to read, use more meaningful names
for the opcodes. PPC_TLBIE_5 is introduced for the 5 opcode variation of
the instruction due to an existing op-code for the 2 opcode variant.
Signed-off-by: default avatarBalbir Singh <bsingharora@gmail.com>
Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 9a1a70ae
...@@ -190,6 +190,7 @@ ...@@ -190,6 +190,7 @@
#define PPC_INST_STSWX 0x7c00052a #define PPC_INST_STSWX 0x7c00052a
#define PPC_INST_STXVD2X 0x7c000798 #define PPC_INST_STXVD2X 0x7c000798
#define PPC_INST_TLBIE 0x7c000264 #define PPC_INST_TLBIE 0x7c000264
#define PPC_INST_TLBIEL 0x7c000224
#define PPC_INST_TLBILX 0x7c000024 #define PPC_INST_TLBILX 0x7c000024
#define PPC_INST_WAIT 0x7c00007c #define PPC_INST_WAIT 0x7c00007c
#define PPC_INST_TLBIVAX 0x7c000624 #define PPC_INST_TLBIVAX 0x7c000624
...@@ -281,6 +282,9 @@ ...@@ -281,6 +282,9 @@
#define ___PPC_RB(b) (((b) & 0x1f) << 11) #define ___PPC_RB(b) (((b) & 0x1f) << 11)
#define ___PPC_RS(s) (((s) & 0x1f) << 21) #define ___PPC_RS(s) (((s) & 0x1f) << 21)
#define ___PPC_RT(t) ___PPC_RS(t) #define ___PPC_RT(t) ___PPC_RS(t)
#define ___PPC_R(r) (((r) & 0x1) << 16)
#define ___PPC_PRS(prs) (((prs) & 0x1) << 17)
#define ___PPC_RIC(ric) (((ric) & 0x3) << 18)
#define __PPC_RA(a) ___PPC_RA(__REG_##a) #define __PPC_RA(a) ___PPC_RA(__REG_##a)
#define __PPC_RA0(a) ___PPC_RA(__REGA0_##a) #define __PPC_RA0(a) ___PPC_RA(__REGA0_##a)
#define __PPC_RB(b) ___PPC_RB(__REG_##b) #define __PPC_RB(b) ___PPC_RB(__REG_##b)
...@@ -347,6 +351,16 @@ ...@@ -347,6 +351,16 @@
__PPC_WC(w)) __PPC_WC(w))
#define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \ #define PPC_TLBIE(lp,a) stringify_in_c(.long PPC_INST_TLBIE | \
___PPC_RB(a) | ___PPC_RS(lp)) ___PPC_RB(a) | ___PPC_RS(lp))
#define PPC_TLBIE_5(rb,rs,ric,prs,r) \
stringify_in_c(.long PPC_INST_TLBIE | \
___PPC_RB(rb) | ___PPC_RS(rs) | \
___PPC_RIC(ric) | ___PPC_PRS(prs) | \
___PPC_R(r))
#define PPC_TLBIEL(rb,rs,ric,prs,r) \
stringify_in_c(.long PPC_INST_TLBIEL | \
___PPC_RB(rb) | ___PPC_RS(rs) | \
___PPC_RIC(ric) | ___PPC_PRS(prs) | \
___PPC_R(r))
#define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \ #define PPC_TLBSRX_DOT(a,b) stringify_in_c(.long PPC_INST_TLBSRX_DOT | \
__PPC_RA0(a) | __PPC_RB(b)) __PPC_RA0(a) | __PPC_RB(b))
#define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \ #define PPC_TLBIVAX(a,b) stringify_in_c(.long PPC_INST_TLBIVAX | \
......
...@@ -12,6 +12,7 @@ ...@@ -12,6 +12,7 @@
#include <linux/mm.h> #include <linux/mm.h>
#include <linux/hugetlb.h> #include <linux/hugetlb.h>
#include <linux/memblock.h> #include <linux/memblock.h>
#include <asm/ppc-opcode.h>
#include <asm/tlb.h> #include <asm/tlb.h>
#include <asm/tlbflush.h> #include <asm/tlbflush.h>
...@@ -34,8 +35,7 @@ static inline void __tlbiel_pid(unsigned long pid, int set, ...@@ -34,8 +35,7 @@ static inline void __tlbiel_pid(unsigned long pid, int set,
r = 1; /* raidx format */ r = 1; /* raidx format */
asm volatile("ptesync": : :"memory"); asm volatile("ptesync": : :"memory");
asm volatile(".long 0x7c000224 | (%0 << 11) | (%1 << 16) |" asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
"(%2 << 17) | (%3 << 18) | (%4 << 21)"
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory"); : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
asm volatile("ptesync": : :"memory"); asm volatile("ptesync": : :"memory");
} }
...@@ -63,8 +63,7 @@ static inline void _tlbie_pid(unsigned long pid, unsigned long ric) ...@@ -63,8 +63,7 @@ static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
r = 1; /* raidx format */ r = 1; /* raidx format */
asm volatile("ptesync": : :"memory"); asm volatile("ptesync": : :"memory");
asm volatile(".long 0x7c000264 | (%0 << 11) | (%1 << 16) |" asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
"(%2 << 17) | (%3 << 18) | (%4 << 21)"
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory"); : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
asm volatile("eieio; tlbsync; ptesync": : :"memory"); asm volatile("eieio; tlbsync; ptesync": : :"memory");
} }
...@@ -81,8 +80,7 @@ static inline void _tlbiel_va(unsigned long va, unsigned long pid, ...@@ -81,8 +80,7 @@ static inline void _tlbiel_va(unsigned long va, unsigned long pid,
r = 1; /* raidx format */ r = 1; /* raidx format */
asm volatile("ptesync": : :"memory"); asm volatile("ptesync": : :"memory");
asm volatile(".long 0x7c000224 | (%0 << 11) | (%1 << 16) |" asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
"(%2 << 17) | (%3 << 18) | (%4 << 21)"
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory"); : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
asm volatile("ptesync": : :"memory"); asm volatile("ptesync": : :"memory");
} }
...@@ -99,8 +97,7 @@ static inline void _tlbie_va(unsigned long va, unsigned long pid, ...@@ -99,8 +97,7 @@ static inline void _tlbie_va(unsigned long va, unsigned long pid,
r = 1; /* raidx format */ r = 1; /* raidx format */
asm volatile("ptesync": : :"memory"); asm volatile("ptesync": : :"memory");
asm volatile(".long 0x7c000264 | (%0 << 11) | (%1 << 16) |" asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
"(%2 << 17) | (%3 << 18) | (%4 << 21)"
: : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory"); : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
asm volatile("eieio; tlbsync; ptesync": : :"memory"); asm volatile("eieio; tlbsync; ptesync": : :"memory");
} }
......
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