Commit 8d6a5230 authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu/gmc9: get vram width from atom for Raven

Get it from the system info table.
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 21f6bcb6
...@@ -23,6 +23,7 @@ ...@@ -23,6 +23,7 @@
#include <linux/firmware.h> #include <linux/firmware.h>
#include "amdgpu.h" #include "amdgpu.h"
#include "gmc_v9_0.h" #include "gmc_v9_0.h"
#include "amdgpu_atomfirmware.h"
#include "vega10/soc15ip.h" #include "vega10/soc15ip.h"
#include "vega10/HDP/hdp_4_0_offset.h" #include "vega10/HDP/hdp_4_0_offset.h"
...@@ -442,43 +443,46 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev) ...@@ -442,43 +443,46 @@ static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
u32 tmp; u32 tmp;
int chansize, numchan; int chansize, numchan;
/* hbm memory channel size */ adev->mc.vram_width = amdgpu_atomfirmware_get_vram_width(adev);
chansize = 128; if (!adev->mc.vram_width) {
/* hbm memory channel size */
tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0); chansize = 128;
tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT; tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
switch (tmp) { tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
case 0: tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
default: switch (tmp) {
numchan = 1; case 0:
break; default:
case 1: numchan = 1;
numchan = 2; break;
break; case 1:
case 2: numchan = 2;
numchan = 0; break;
break; case 2:
case 3: numchan = 0;
numchan = 4; break;
break; case 3:
case 4: numchan = 4;
numchan = 0; break;
break; case 4:
case 5: numchan = 0;
numchan = 8; break;
break; case 5:
case 6: numchan = 8;
numchan = 0; break;
break; case 6:
case 7: numchan = 0;
numchan = 16; break;
break; case 7:
case 8: numchan = 16;
numchan = 2; break;
break; case 8:
numchan = 2;
break;
}
adev->mc.vram_width = numchan * chansize;
} }
adev->mc.vram_width = numchan * chansize;
/* Could aper size report 0 ? */ /* Could aper size report 0 ? */
adev->mc.aper_base = pci_resource_start(adev->pdev, 0); adev->mc.aper_base = pci_resource_start(adev->pdev, 0);
......
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