Commit 8d6b458c authored by Johan Hovold's avatar Johan Hovold Committed by Bjorn Andersson

arm64: dts: qcom: sc8280xp: fix ufs_card_phy ref clock

The GCC_UFS_REF_CLKREF_CLK must be enabled or the second UFS controller
fails to enumerate on sa8295p-adp.

Note that the vendor kernel enables both GCC_UFS_REF_CLKREF_CLK and
GCC_UFS_1_CARD_CLKREF_CLK and it is possible that the former should be
modelled as a parent of the latter. The clock driver also has a
GCC_UFS_CARD_CLKREF_CLK clock which the firmware appears to enable on
the ADP.

The usual lack of documentation for Qualcomm SoCs makes this a highly
annoying guessing game, but as the second controller works on the ADP
without either card reference clock enabled, only enable
GCC_UFS_REF_CLKREF_CLK for now.

Fixes: 152d1faf ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: default avatarJohan Hovold <johan+linaro@kernel.org>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: default avatarBrian Masney <bmasney@redhat.com>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221005143305.388-1-johan+linaro@kernel.org
parent 1ce8aaf6
...@@ -959,7 +959,7 @@ ufs_card_phy: phy@1da7000 { ...@@ -959,7 +959,7 @@ ufs_card_phy: phy@1da7000 {
ranges; ranges;
clock-names = "ref", clock-names = "ref",
"ref_aux"; "ref_aux";
clocks = <&gcc GCC_UFS_1_CARD_CLKREF_CLK>, clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>,
<&gcc GCC_UFS_CARD_PHY_AUX_CLK>; <&gcc GCC_UFS_CARD_PHY_AUX_CLK>;
resets = <&ufs_card_hc 0>; resets = <&ufs_card_hc 0>;
......
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