Skip to content

L
linux
Commit 8e3a3249 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Options

Merge tag 'char-misc-5.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc 

Pull char/misc driver updates from Greg KH:
 "Here is the big set of various smaller driver subsystem updates for
  5.13-rc1.

  Major bits in here are:

   - habanalabs driver updates

   - hwtracing driver updates

   - interconnect driver updates

   - mhi driver updates

   - extcon driver updates

   - fpga driver updates

   - new binder features added

   - nvmem driver updates

   - phy driver updates

   - soundwire driver updates

   - smaller misc and char driver fixes and updates.

   - bluetooth driver bugfix that maintainer wanted to go through this
     tree.

  All of these have been in linux-next with no reported issues"

* tag 'char-misc-5.13-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (330 commits)
  bluetooth: eliminate the potential race condition when removing the HCI controller
  coresight: etm-perf: Fix define build issue when built as module
  phy: Revert "phy: ti: j721e-wiz: add missing of_node_put"
  phy: ti: j721e-wiz: Add missing include linux/slab.h
  phy: phy-twl4030-usb: Fix possible use-after-free in twl4030_usb_remove()
  stm class: Use correct UUID APIs
  intel_th: pci: Add Alder Lake-M support
  intel_th: pci: Add Rocket Lake CPU support
  intel_th: Consistency and off-by-one fix
  intel_th: Constify attribute_group structs
  intel_th: Constify all drvdata references
  stm class: Remove an unused function
  habanalabs/gaudi: Fix uninitialized return code rc when read size is zero
  greybus: es2: fix kernel-doc warnings
  mei: me: add Alder Lake P device id.
  dw-xdata-pcie: Update outdated info and improve text format
  dw-xdata-pcie: Fix documentation build warns
  fbdev: zero-fill colormap in fbcmap.c
  firmware: qcom-scm: Fix QCOM_SCM configuration
  speakup: i18n: Switch to kmemdup_nul() in spk_msg_set()
  ...
parents 90035c28 e2cb6b89
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 16281 additions and 1981 deletions
Documentation/ABI/testing/debugfs-driver-habanalabs
View file @ 8e3a3249
......@@ -82,6 +82,24 @@ Description: Allows the root user to read or write 64 bit data directly
If the IOMMU is disabled, it also allows the root user to read
or write from the host a device VA of a host mapped memory
What: /sys/kernel/debug/habanalabs/hl<n>/data_dma
Date: Apr 2021
KernelVersion: 5.13
Contact: ogabbay@kernel.org
Description: Allows the root user to read from the device's internal
memory (DRAM/SRAM) through a DMA engine.
This property is a binary blob that contains the result of the
DMA transfer.
This custom interface is needed (instead of using the generic
Linux user-space PCI mapping) because the amount of internal
memory is huge (>32GB) and reading it via the PCI bar will take
a very long time.
This interface doesn't support concurrency in the same device.
In GAUDI and GOYA, this action can cause undefined behavior
in case the it is done while the device is executing user
workloads.
Only supported on GAUDI at this stage.
What: /sys/kernel/debug/habanalabs/hl<n>/device
Date: Jan 2019
KernelVersion: 5.1
......@@ -90,6 +108,24 @@ Description: Enables the root user to set the device to specific state.
Valid values are "disable", "enable", "suspend", "resume".
User can read this property to see the valid values
What: /sys/kernel/debug/habanalabs/hl<n>/dma_size
Date: Apr 2021
KernelVersion: 5.13
Contact: ogabbay@kernel.org
Description: Specify the size of the DMA transaction when using DMA to read
from the device's internal memory. The value can not be larger
than 128MB. Writing to this value initiates the DMA transfer.
When the write is finished, the user can read the "data_dma"
blob
What: /sys/kernel/debug/habanalabs/hl<n>/dump_security_violations
Date: Jan 2021
KernelVersion: 5.12
Contact: ogabbay@kernel.org
Description: Dumps all security violations to dmesg. This will also ack
all security violations meanings those violations will not be
dumped next time user calls this API
What: /sys/kernel/debug/habanalabs/hl<n>/engines
Date: Jul 2019
KernelVersion: 5.3
......@@ -154,6 +190,16 @@ Description: Displays the hop values and physical address for a given ASID
e.g. to display info about VA 0x1000 for ASID 1 you need to do:
echo "1 0x1000" > /sys/kernel/debug/habanalabs/hl0/mmu
What: /sys/kernel/debug/habanalabs/hl<n>/mmu_error
Date: Mar 2021
KernelVersion: 5.12
Contact: fkassabri@habana.ai
Description: Check and display page fault or access violation mmu errors for
all MMUs specified in mmu_cap_mask.
e.g. to display error info for MMU hw cap bit 9, you need to do:
echo "0x200" > /sys/kernel/debug/habanalabs/hl0/mmu_error
cat /sys/kernel/debug/habanalabs/hl0/mmu_error
What: /sys/kernel/debug/habanalabs/hl<n>/set_power_state
Date: Jan 2019
KernelVersion: 5.1
......@@ -161,6 +207,13 @@ Contact: ogabbay@kernel.org
Description: Sets the PCI power state. Valid values are "1" for D0 and "2"
for D3Hot
What: /sys/kernel/debug/habanalabs/hl<n>/stop_on_err
Date: Mar 2020
KernelVersion: 5.6
Contact: ogabbay@kernel.org
Description: Sets the stop-on_error option for the device engines. Value of
"0" is for disable, otherwise enable.
What: /sys/kernel/debug/habanalabs/hl<n>/userptr
Date: Jan 2019
KernelVersion: 5.1
......@@ -174,19 +227,4 @@ Date: Jan 2019
KernelVersion: 5.1
Contact: ogabbay@kernel.org
Description: Displays a list with information about all the active virtual
address mappings per ASID
What: /sys/kernel/debug/habanalabs/hl<n>/stop_on_err
Date: Mar 2020
KernelVersion: 5.6
Contact: ogabbay@kernel.org
Description: Sets the stop-on_error option for the device engines. Value of
"0" is for disable, otherwise enable.
What: /sys/kernel/debug/habanalabs/hl<n>/dump_security_violations
Date: Jan 2021
KernelVersion: 5.12
Contact: ogabbay@kernel.org
Description: Dumps all security violations to dmesg. This will also ack
all security violations meanings those violations will not be
dumped next time user calls this API
address mappings per ASID and all user mappings of HW blocks
Documentation/ABI/testing/sysfs-bus-pci-devices-pvpanic
View file @ 8e3a3249
What: /sys/devices/pci0000:00/*/QEMU0001:00/capability
What: /sys/devices/pci0000:00/*/QEMU0001:00/capability for MMIO
/sys/bus/pci/drivers/pvpanic-pci/0000:00:0*.0/capability for PCI
Date: Jan 2021
Contact: zhenwei pi <pizhenwei@bytedance.com>
Description:
......@@ -12,6 +13,7 @@ Description:
https://git.qemu.org/?p=qemu.git;a=blob_plain;f=docs/specs/pvpanic.txt
What: /sys/devices/pci0000:00/*/QEMU0001:00/events
/sys/bus/pci/drivers/pvpanic-pci/0000:00:0*.0/events for PCI
Date: Jan 2021
Contact: zhenwei pi <pizhenwei@bytedance.com>
Description:
......
Documentation/ABI/testing/sysfs-driver-xdata 0 → 100644
View file @ 8e3a3249
What: /sys/class/misc/drivers/dw-xdata-pcie.<device>/write
Date: April 2021
KernelVersion: 5.13
Contact: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Description: Allows the user to enable the PCIe traffic generator which
will create write TLPs frames - from the Root Complex to the
Endpoint direction or to disable the PCIe traffic generator
in all directions.
Write y/1/on to enable, n/0/off to disable
Usage e.g.
echo 1 > /sys/class/misc/dw-xdata-pcie.<device>/write
or
echo 0 > /sys/class/misc/dw-xdata-pcie.<device>/write
The user can read the current PCIe link throughput generated
through this generator in MB/s.
Usage e.g.
cat /sys/class/misc/dw-xdata-pcie.<device>/write
204
The file is read and write.
What: /sys/class/misc/dw-xdata-pcie.<device>/read
Date: April 2021
KernelVersion: 5.13
Contact: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Description: Allows the user to enable the PCIe traffic generator which
will create read TLPs frames - from the Endpoint to the Root
Complex direction or to disable the PCIe traffic generator
in all directions.
Write y/1/on to enable, n/0/off to disable
Usage e.g.
echo 1 > /sys/class/misc/dw-xdata-pcie.<device>/read
or
echo 0 > /sys/class/misc/dw-xdata-pcie.<device>/read
The user can read the current PCIe link throughput generated
through this generator in MB/s.
Usage e.g.
cat /sys/class/misc/dw-xdata-pcie.<device>/read
199
The file is read and write.
Documentation/devicetree/bindings/extcon/qcom,pm8941-misc.txt deleted 100644 → 0
View file @ 90035c28
Qualcomm's PM8941 USB ID Extcon device
Some Qualcomm PMICs have a "misc" module that can be used to detect when
the USB ID pin has been pulled low or high.
PROPERTIES
- compatible:
Usage: required
Value type: <string>
Definition: Should contain "qcom,pm8941-misc";
- reg:
Usage: required
Value type: <u32>
Definition: Should contain the offset to the misc address space
- interrupts:
Usage: required
Value type: <prop-encoded-array>
Definition: Should contain the usb id interrupt
- interrupt-names:
Usage: required
Value type: <stringlist>
Definition: Should contain the string "usb_id" for the usb id interrupt
Example:
pmic {
usb_id: misc@900 {
compatible = "qcom,pm8941-misc";
reg = <0x900>;
interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "usb_id";
};
}
usb-controller {
extcon = <&usb_id>;
};
Documentation/devicetree/bindings/extcon/qcom,pm8941-misc.yaml 0 → 100644
View file @ 8e3a3249
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/extcon/qcom,pm8941-misc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. PM8941 USB ID Extcon device
maintainers:
- Guru Das Srinagesh <gurus@codeaurora.org>
description: |
Some Qualcomm PMICs have a "misc" module that can be used to detect when
the USB ID pin has been pulled low or high.
properties:
compatible:
items:
- const: qcom,pm8941-misc
reg:
maxItems: 1
interrupts:
minItems: 1
maxItems: 2
interrupt-names:
minItems: 1
items:
- const: usb_id
- const: usb_vbus
required:
- compatible
- reg
- interrupts
- interrupt-names
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
pmic {
#address-cells = <1>;
#size-cells = <0>;
interrupt-controller;
#interrupt-cells = <4>;
usb_id: misc@900 {
compatible = "qcom,pm8941-misc";
reg = <0x900>;
interrupts = <0x0 0x9 0 IRQ_TYPE_EDGE_BOTH>;
interrupt-names = "usb_id";
};
};
usb-controller {
extcon = <&usb_id>;
};
Documentation/devicetree/bindings/fpga/fpga-region.txt
View file @ 8e3a3249
......@@ -245,36 +245,31 @@ Base tree contains:
Overlay contains:
/dts-v1/ /plugin/;
/ {
fragment@0 {
target = <&fpga_region0>;
#address-cells = <1>;
#size-cells = <1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <1>;
firmware-name = "soc_system.rbf";
fpga-bridges = <&fpga_bridge1>;
ranges = <0x20000 0xff200000 0x100000>,
<0x0 0xc0000000 0x20000000>;
gpio@10040 {
compatible = "altr,pio-1.0";
reg = <0x10040 0x20>;
altr,ngpio = <4>;
#gpio-cells = <2>;
clocks = <2>;
gpio-controller;
};
onchip-memory {
device_type = "memory";
compatible = "altr,onchipmem-15.1";
reg = <0x0 0x10000>;
};
};
/dts-v1/;
/plugin/;
&fpga_region0 {
#address-cells = <1>;
#size-cells = <1>;
firmware-name = "soc_system.rbf";
fpga-bridges = <&fpga_bridge1>;
ranges = <0x20000 0xff200000 0x100000>,
<0x0 0xc0000000 0x20000000>;
gpio@10040 {
compatible = "altr,pio-1.0";
reg = <0x10040 0x20>;
altr,ngpio = <4>;
#gpio-cells = <2>;
clocks = <2>;
gpio-controller;
};
onchip-memory {
device_type = "memory";
compatible = "altr,onchipmem-15.1";
reg = <0x0 0x10000>;
};
};
......@@ -371,25 +366,22 @@ Live Device Tree contains:
};
DT Overlay contains:
/dts-v1/ /plugin/;
/ {
fragment@0 {
target = <&fpga_region0>;
/dts-v1/;
/plugin/;
&fpga_region0 {
#address-cells = <1>;
#size-cells = <1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <1>;
firmware-name = "zynq-gpio.bin";
firmware-name = "zynq-gpio.bin";
gpio1: gpio@40000000 {
compatible = "xlnx,xps-gpio-1.00.a";
reg = <0x40000000 0x10000>;
gpio-controller;
#gpio-cells = <0x2>;
xlnx,gpio-width= <0x6>;
};
gpio1: gpio@40000000 {
compatible = "xlnx,xps-gpio-1.00.a";
reg = <0x40000000 0x10000>;
gpio-controller;
#gpio-cells = <0x2>;
xlnx,gpio-width= <0x6>;
};
};
......@@ -402,41 +394,37 @@ This example programs the FPGA to have two regions that can later be partially
configured. Each region has its own bridge in the FPGA fabric.
DT Overlay contains:
/dts-v1/ /plugin/;
/ {
fragment@0 {
target = <&fpga_region0>;
#address-cells = <1>;
#size-cells = <1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <1>;
firmware-name = "base.rbf";
fpga-bridge@4400 {
compatible = "altr,freeze-bridge-controller";
reg = <0x4400 0x10>;
fpga_region1: fpga-region1 {
compatible = "fpga-region";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
};
fpga-bridge@4420 {
compatible = "altr,freeze-bridge-controller";
reg = <0x4420 0x10>;
fpga_region2: fpga-region2 {
compatible = "fpga-region";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
};
/dts-v1/;
/plugin/;
&fpga_region0 {
#address-cells = <1>;
#size-cells = <1>;
firmware-name = "base.rbf";
fpga-bridge@4400 {
compatible = "altr,freeze-bridge-controller";
reg = <0x4400 0x10>;
fpga_region1: fpga-region1 {
compatible = "fpga-region";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
};
fpga-bridge@4420 {
compatible = "altr,freeze-bridge-controller";
reg = <0x4420 0x10>;
fpga_region2: fpga-region2 {
compatible = "fpga-region";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
};
};
......@@ -451,28 +439,23 @@ differences are that the FPGA is partially reconfigured due to the
"partial-fpga-config" boolean and the only bridge that is controlled during
programming is the FPGA based bridge of fpga_region1.
/dts-v1/ /plugin/;
/ {
fragment@0 {
target = <&fpga_region1>;
#address-cells = <1>;
#size-cells = <1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <1>;
firmware-name = "soc_image2.rbf";
partial-fpga-config;
gpio@10040 {
compatible = "altr,pio-1.0";
reg = <0x10040 0x20>;
clocks = <0x2>;
altr,ngpio = <0x4>;
#gpio-cells = <0x2>;
gpio-controller;
};
};
/dts-v1/;
/plugin/;
&fpga_region1 {
#address-cells = <1>;
#size-cells = <1>;
firmware-name = "soc_image2.rbf";
partial-fpga-config;
gpio@10040 {
compatible = "altr,pio-1.0";
reg = <0x10040 0x20>;
clocks = <0x2>;
altr,ngpio = <0x4>;
#gpio-cells = <0x2>;
gpio-controller;
};
};
......
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
View file @ 8e3a3249
......@@ -7,13 +7,24 @@ changes from passing through the bridge. The controller can also
couple / enable the bridges which allows traffic to pass through the
bridge normally.
Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager
Softcore is compatible with the Xilinx LogiCORE pr-decoupler.
The Dynamic Function eXchange AXI shutdown manager prevents AXI traffic
from passing through the bridge. The controller safely handles AXI4MM
and AXI4-Lite interfaces on a Reconfigurable Partition when it is
undergoing dynamic reconfiguration, preventing the system deadlock
that can occur if AXI transactions are interrupted by DFX
The Driver supports only MMIO handling. A PR region can have multiple
PR Decouplers which can be handled independently or chained via decouple/
decouple_status signals.
Required properties:
- compatible : Should contain "xlnx,pr-decoupler-1.00" followed by
"xlnx,pr-decoupler"
"xlnx,pr-decoupler" or
"xlnx,dfx-axi-shutdown-manager-1.00" followed by
"xlnx,dfx-axi-shutdown-manager"
- regs : base address and size for decoupler module
- clocks : input clock to IP
- clock-names : should contain "aclk"
......@@ -22,6 +33,7 @@ See Documentation/devicetree/bindings/fpga/fpga-region.txt and
Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
Example:
Partial Reconfig Decoupler:
fpga-bridge@100000450 {
compatible = "xlnx,pr-decoupler-1.00",
"xlnx-pr-decoupler";
......@@ -30,3 +42,13 @@ Example:
clock-names = "aclk";
bridge-enable = <0>;
};
Dynamic Function eXchange AXI shutdown manager:
fpga-bridge@100000450 {
compatible = "xlnx,dfx-axi-shutdown-manager-1.00",
"xlnx,dfx-axi-shutdown-manager";
regs = <0x10000045 0x10>;
clocks = <&clkc 15>;
clock-names = "aclk";
bridge-enable = <0>;
};
Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
View file @ 8e3a3249
......@@ -71,6 +71,16 @@ properties:
- qcom,sm8250-mmss-noc
- qcom,sm8250-npu-noc
- qcom,sm8250-system-noc
- qcom,sm8350-aggre1-noc
- qcom,sm8350-aggre2-noc
- qcom,sm8350-config-noc
- qcom,sm8350-dc-noc
- qcom,sm8350-gem-noc
- qcom,sm8350-lpass-ag-noc
- qcom,sm8350-mc-virt
- qcom,sm8350-mmss-noc
- qcom,sm8350-compute-noc
- qcom,sm8350-system-noc
'#interconnect-cells':
enum: [ 1, 2 ]
......
Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml 0 → 100644
View file @ 8e3a3249
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/interconnect/qcom,sdm660.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SDM660 Network-On-Chip interconnect
maintainers:
- AngeloGioacchino Del Regno <kholk11@gmail.com>
description: |
The Qualcomm SDM660 interconnect providers support adjusting the
bandwidth requirements between the various NoC fabrics.
properties:
reg:
maxItems: 1
compatible:
enum:
- qcom,sdm660-a2noc
- qcom,sdm660-bimc
- qcom,sdm660-cnoc
- qcom,sdm660-gnoc
- qcom,sdm660-mnoc
- qcom,sdm660-snoc
'#interconnect-cells':
const: 1
clocks:
minItems: 1
maxItems: 3
clock-names:
minItems: 1
maxItems: 3
required:
- compatible
- reg
- '#interconnect-cells'
- clock-names
- clocks
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm660-mnoc
then:
properties:
clocks:
items:
- description: Bus Clock.
- description: Bus A Clock.
- description: CPU-NoC High-performance Bus Clock.
clock-names:
items:
- const: bus
- const: bus_a
- const: iface
- if:
properties:
compatible:
contains:
enum:
- qcom,sdm660-a2noc
- qcom,sdm660-bimc
- qcom,sdm660-cnoc
- qcom,sdm660-gnoc
- qcom,sdm660-snoc
then:
properties:
clocks:
items:
- description: Bus Clock.
- description: Bus A Clock.
clock-names:
items:
- const: bus
- const: bus_a
examples:
- |
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,mmcc-sdm660.h>
bimc: interconnect@1008000 {
compatible = "qcom,sdm660-bimc";
reg = <0x01008000 0x78000>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_BIMC_CLK>,
<&rpmcc RPM_SMD_BIMC_A_CLK>;
};
cnoc: interconnect@1500000 {
compatible = "qcom,sdm660-cnoc";
reg = <0x01500000 0x10000>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_CNOC_CLK>,
<&rpmcc RPM_SMD_CNOC_A_CLK>;
};
snoc: interconnect@1626000 {
compatible = "qcom,sdm660-snoc";
reg = <0x01626000 0x7090>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_SNOC_CLK>,
<&rpmcc RPM_SMD_SNOC_A_CLK>;
};
a2noc: interconnect@1704000 {
compatible = "qcom,sdm660-a2noc";
reg = <0x01704000 0xc100>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&rpmcc RPM_SMD_AGGR2_NOC_CLK>,
<&rpmcc RPM_SMD_AGGR2_NOC_A_CLK>;
};
mnoc: interconnect@1745000 {
compatible = "qcom,sdm660-mnoc";
reg = <0x01745000 0xa010>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a", "iface";
clocks = <&rpmcc RPM_SMD_MMSSNOC_AXI_CLK>,
<&rpmcc RPM_SMD_MMSSNOC_AXI_CLK_A>,
<&mmcc AHB_CLK_SRC>;
};
gnoc: interconnect@17900000 {
compatible = "qcom,sdm660-gnoc";
reg = <0x17900000 0xe000>;
#interconnect-cells = <1>;
clock-names = "bus", "bus_a";
clocks = <&xo_board>, <&xo_board>;
};
Documentation/devicetree/bindings/nvmem/brcm,nvram.yaml 0 → 100644
View file @ 8e3a3249
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/nvmem/brcm,nvram.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom's NVRAM
description: |
Broadcom's NVRAM is a structure containing device specific environment
variables. It is used for storing device configuration, booting parameters
and calibration data.
NVRAM can be accessed on Broadcom BCM47xx MIPS and Northstar ARM Cortex-A9
devices usiong I/O mapped memory.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
allOf:
- $ref: "nvmem.yaml#"
properties:
compatible:
const: brcm,nvram
unevaluatedProperties: false
examples:
- |
nvram@1eff0000 {
compatible = "brcm,nvram";
reg = <0x1eff0000 0x10000>;
};
Documentation/devicetree/bindings/nvmem/mtk-efuse.txt
View file @ 8e3a3249
......@@ -8,6 +8,7 @@ Required properties:
"mediatek,mt7623-efuse", "mediatek,efuse": for MT7623
"mediatek,mt8173-efuse" or "mediatek,efuse": for MT8173
"mediatek,mt8516-efuse", "mediatek,efuse": for MT8516
"mediatek,mt8192-efuse", "mediatek,efuse": for MT8192
- reg: Should contain registers location and length
= Data cells =
......
Documentation/devicetree/bindings/nvmem/qcom,qfprom.yaml
View file @ 8e3a3249
......@@ -24,6 +24,7 @@ properties:
- qcom,msm8998-qfprom
- qcom,qcs404-qfprom
- qcom,sc7180-qfprom
- qcom,sc7280-qfprom
- qcom,sdm845-qfprom
- const: qcom,qfprom
......
Documentation/devicetree/bindings/phy/bcm-ns-usb2-phy.txt deleted 100644 → 0
View file @ 90035c28
Driver for Broadcom Northstar USB 2.0 PHY
Required properties:
- compatible: brcm,ns-usb2-phy
- reg: iomem address range of DMU (Device Management Unit)
- reg-names: "dmu", the only needed & supported reg right now
- clocks: USB PHY reference clock
- clock-names: "phy-ref-clk", the only needed & supported clock right now
To initialize USB 2.0 PHY driver needs to setup PLL correctly. To do this it
requires passing phandle to the USB PHY reference clock.
Example:
usb2-phy {
compatible = "brcm,ns-usb2-phy";
reg = <0x1800c000 0x1000>;
reg-names = "dmu";
#phy-cells = <0>;
clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
clock-names = "phy-ref-clk";
};
Documentation/devicetree/bindings/phy/bcm-ns-usb2-phy.yaml 0 → 100644
View file @ 8e3a3249
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/bcm-ns-usb2-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Northstar USB 2.0 PHY
description: >
To initialize USB 2.0 PHY driver needs to setup PLL correctly.
To do this it requires passing phandle to the USB PHY reference clock.
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
compatible:
const: brcm,ns-usb2-phy
reg:
items:
- description: iomem address range of DMU (Device Management Unit)
reg-names:
items:
- const: dmu
clocks:
items:
- description: USB PHY reference clock
clock-names:
items:
- const: phy-ref-clk
"#phy-cells":
const: 0
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- "#phy-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/bcm-nsp.h>
phy@1800c000 {
compatible = "brcm,ns-usb2-phy";
reg = <0x1800c000 0x1000>;
reg-names = "dmu";
clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
clock-names = "phy-ref-clk";
#phy-cells = <0>;
};
Documentation/devicetree/bindings/phy/bcm-ns-usb3-phy.txt deleted 100644 → 0
View file @ 90035c28
Driver for Broadcom Northstar USB 3.0 PHY
Required properties:
- compatible: one of: "brcm,ns-ax-usb3-phy", "brcm,ns-bx-usb3-phy".
- reg: address of MDIO bus device
- usb3-dmp-syscon: phandle to syscon with DMP (Device Management Plugin)
registers
- #phy-cells: must be 0
Initialization of USB 3.0 PHY depends on Northstar version. There are currently
three known series: Ax, Bx and Cx.
Known A0: BCM4707 rev 0
Known B0: BCM4707 rev 4, BCM53573 rev 2
Known B1: BCM4707 rev 6
Known C0: BCM47094 rev 0
Example:
mdio: mdio@0 {
reg = <0x0>;
#size-cells = <1>;
#address-cells = <0>;
usb3-phy@10 {
compatible = "brcm,ns-ax-usb3-phy";
reg = <0x10>;
usb3-dmp-syscon = <&usb3_dmp>;
#phy-cells = <0>;
};
};
usb3_dmp: syscon@18105000 {
reg = <0x18105000 0x1000>;
};
Documentation/devicetree/bindings/phy/bcm-ns-usb3-phy.yaml 0 → 100644
View file @ 8e3a3249
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/bcm-ns-usb3-phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom Northstar USB 3.0 PHY
description: |
Initialization of USB 3.0 PHY depends on Northstar version. There are currently
three known series: Ax, Bx and Cx.
Known A0: BCM4707 rev 0
Known B0: BCM4707 rev 4, BCM53573 rev 2
Known B1: BCM4707 rev 6
Known C0: BCM47094 rev 0
maintainers:
- Rafał Miłecki <rafal@milecki.pl>
properties:
compatible:
enum:
- brcm,ns-ax-usb3-phy
- brcm,ns-bx-usb3-phy
reg:
description: address of MDIO bus device
maxItems: 1
usb3-dmp-syscon:
$ref: /schemas/types.yaml#/definitions/phandle
description:
Phandle to the DMP (Device Management Plugin) syscon
"#phy-cells":
const: 0
required:
- compatible
- reg
- usb3-dmp-syscon
- "#phy-cells"
additionalProperties: false
examples:
- |
mdio {
#address-cells = <1>;
#size-cells = <0>;
usb3-phy@10 {
compatible = "brcm,ns-ax-usb3-phy";
reg = <0x10>;
usb3-dmp-syscon = <&usb3_dmp>;
#phy-cells = <0>;
};
};
usb3_dmp: syscon@18105000 {
reg = <0x18105000 0x1000>;
};
Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml
View file @ 8e3a3249
......@@ -42,6 +42,9 @@ properties:
- const: usb_mdio
- const: bdc_ec
power-domains:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
......
Documentation/devicetree/bindings/phy/marvell,armada-3700-utmi-phy.yaml 0 → 100644
View file @ 8e3a3249
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/marvell,armada-3700-utmi-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Marvell Armada UTMI/UTMI+ PHY
maintainers:
- Miquel Raynal <miquel.raynal@bootlin.com>
description:
On Armada 3700, there are two USB controllers, one is compatible with
the USB2 and USB3 specifications and supports OTG. The other one is USB2
compliant and only supports host mode. Both of these controllers come with
a slightly different UTMI PHY.
properties:
compatible:
enum:
- marvell,a3700-utmi-host-phy
- marvell,a3700-utmi-otg-phy
reg:
maxItems: 1
"#phy-cells":
const: 0
marvell,usb-misc-reg:
description:
Phandle on the "USB miscellaneous registers" shared region
covering registers related to both the host controller and
the PHY.
$ref: /schemas/types.yaml#/definitions/phandle
required:
- compatible
- reg
- "#phy-cells"
- marvell,usb-misc-reg
additionalProperties: false
examples:
- |
usb2_utmi_host_phy: phy@5f000 {
compatible = "marvell,armada-3700-utmi-host-phy";
reg = <0x5f000 0x800>;
marvell,usb-misc-reg = <&usb2_syscon>;
#phy-cells = <0>;
};
usb2_syscon: system-controller@5f800 {
compatible = "marvell,armada-3700-usb2-host-misc", "syscon";
reg = <0x5f800 0x800>;
};
Documentation/devicetree/bindings/phy/marvell,armada-cp110-utmi-phy.yaml 0 → 100644
View file @ 8e3a3249
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Marvell Armada CP110/CP115 UTMI PHY
maintainers:
- Konstantin Porotchkin <kostap@marvell.com>
description:
On Armada 7k/8k and CN913x, there are two host and one device USB controllers.
Each of two exiting UTMI PHYs could be connected to either USB host or USB device
controller.
The USB device controller can only be connected to a single UTMI PHY port
0.H----- USB HOST0
UTMI PHY0 --------/
0.D-----0
\------ USB DEVICE
1.D-----1
UTMI PHY1 --------\
1.H----- USB HOST1
properties:
compatible:
const: marvell,cp110-utmi-phy
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
marvell,system-controller:
description:
Phandle to the system controller node
$ref: /schemas/types.yaml#/definitions/phandle
#Required child nodes:
patternProperties:
"^usb-phy@[0|1]$":
type: object
description:
Each UTMI PHY port must be represented as a sub-node.
properties:
reg:
description: phy port index.
maxItems: 1
"#phy-cells":
const: 0
required:
- reg
- "#phy-cells"
additionalProperties: false
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- marvell,system-controller
additionalProperties: false
examples:
- |
cp0_utmi: utmi@580000 {
compatible = "marvell,cp110-utmi-phy";
reg = <0x580000 0x2000>;
marvell,system-controller = <&cp0_syscon0>;
#address-cells = <1>;
#size-cells = <0>;
cp0_utmi0: usb-phy@0 {
reg = <0>;
#phy-cells = <0>;
};
cp0_utmi1: usb-phy@1 {
reg = <1>;
#phy-cells = <0>;
};
};
cp0_usb3_0 {
usb-phy = <&cp0_usb3_0_phy0>;
phys = <&cp0_utmi0>;
phy-names = "utmi";
/* UTMI0 is connected to USB host controller (default mode) */
dr_mode = "host";
};
cp0_usb3_1 {
usb-phy = <&cp0_usb3_0_phy1>;
phys = <&cp0_utmi1>;
phy-names = "utmi";
/* UTMI1 is connected to USB device controller */
dr_mode = "peripheral";
};
Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
View file @ 8e3a3249
......@@ -19,11 +19,14 @@ properties:
pattern: "^dsi-phy@[0-9a-f]+$"
compatible:
enum:
- mediatek,mt2701-mipi-tx
- mediatek,mt7623-mipi-tx
- mediatek,mt8173-mipi-tx
- mediatek,mt8183-mipi-tx
oneOf:
- items:
- enum:
- mediatek,mt7623-mipi-tx
- const: mediatek,mt2701-mipi-tx
- const: mediatek,mt2701-mipi-tx
- const: mediatek,mt8173-mipi-tx
- const: mediatek,mt8183-mipi-tx
reg:
maxItems: 1
......
Documentation/devicetree/bindings/phy/mediatek,hdmi-phy.yaml
View file @ 8e3a3249
......@@ -21,10 +21,13 @@ properties:
pattern: "^hdmi-phy@[0-9a-f]+$"
compatible:
enum:
- mediatek,mt2701-hdmi-phy
- mediatek,mt7623-hdmi-phy
- mediatek,mt8173-hdmi-phy
oneOf:
- items:
- enum:
- mediatek,mt7623-hdmi-phy
- const: mediatek,mt2701-hdmi-phy
- const: mediatek,mt2701-hdmi-phy
- const: mediatek,mt8173-hdmi-phy
reg:
maxItems: 1
......
Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
View file @ 8e3a3249
......@@ -79,6 +79,7 @@ properties:
- mediatek,mt2712-tphy
- mediatek,mt7629-tphy
- mediatek,mt8183-tphy
- mediatek,mt8195-tphy
- const: mediatek,generic-tphy-v2
- const: mediatek,mt2701-u3phy
deprecated: true
......@@ -117,7 +118,7 @@ properties:
# Required child node:
patternProperties:
"^usb-phy@[0-9a-f]+$":
"^(usb|pcie|sata)-phy@[0-9a-f]+$":
type: object
description:
A sub-node is required for each port the controller provides.
......
Documentation/devicetree/bindings/phy/mediatek,ufs-phy.yaml
View file @ 8e3a3249
......@@ -22,7 +22,12 @@ properties:
pattern: "^ufs-phy@[0-9a-f]+$"
compatible:
const: mediatek,mt8183-ufsphy
oneOf:
- items:
- enum:
- mediatek,mt8195-ufsphy
- const: mediatek,mt8183-ufsphy
- const: mediatek,mt8183-ufsphy
reg:
maxItems: 1
......
Documentation/devicetree/bindings/phy/microchip,sparx5-serdes.yaml 0 → 100644
View file @ 8e3a3249
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip Sparx5 Serdes controller
maintainers:
- Steen Hegelund <steen.hegelund@microchip.com>
description: |
The Sparx5 SERDES interfaces share the same basic functionality, but
support different operating modes and line rates.
The following list lists the SERDES features:
* RX Adaptive Decision Feedback Equalizer (DFE)
* Programmable continuous time linear equalizer (CTLE)
* Rx variable gain control
* Rx built-in fault detector (loss-of-lock/loss-of-signal)
* Adjustable tx de-emphasis (FFE)
* Tx output amplitude control
* Supports rx eye monitor
* Multiple loopback modes
* Prbs generator and checker
* Polarity inversion control
SERDES6G:
The SERDES6G is a high-speed SERDES interface, which can operate at
the following data rates:
* 100 Mbps (100BASE-FX)
* 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
* 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
* 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
SERDES10G
The SERDES10G is a high-speed SERDES interface, which can operate at
the following data rates:
* 100 Mbps (100BASE-FX)
* 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
* 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
* 5 Gbps (QSGMII/USGMII)
* 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
* 10 Gbps (10G-USGMII)
* 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
SERDES25G
The SERDES25G is a high-speed SERDES interface, which can operate at
the following data rates:
* 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
* 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
* 5 Gbps (QSGMII/USGMII)
* 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
* 10 Gbps (10G-USGMII)
* 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
* 25.78125 Gbps (25GBASE-KR/25GBASE-CR/25GBASE-SR/25GBASE-LR/25GBASE-ER)
properties:
$nodename:
pattern: "^serdes@[0-9a-f]+$"
compatible:
const: microchip,sparx5-serdes
reg:
minItems: 1
'#phy-cells':
const: 1
description: |
- The main serdes input port
clocks:
maxItems: 1
required:
- compatible
- reg
- '#phy-cells'
- clocks
additionalProperties: false
examples:
- |
serdes: serdes@10808000 {
compatible = "microchip,sparx5-serdes";
#phy-cells = <1>;
clocks = <&sys_clk>;
reg = <0x10808000 0x5d0000>;
};
...
Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
View file @ 8e3a3249
......@@ -26,6 +26,9 @@ properties:
'#size-cells':
const: 0
'#clock-cells':
const: 1
resets:
minItems: 1
maxItems: 2
......@@ -49,12 +52,24 @@ properties:
const: serdes
clocks:
maxItems: 2
minItems: 2
maxItems: 4
clock-names:
minItems: 2
items:
- const: cmn_refclk_dig_div
- const: cmn_refclk1_dig_div
- const: pll0_refclk
- const: pll1_refclk
assigned-clocks:
minItems: 1
maxItems: 2
assigned-clock-parents:
minItems: 1
maxItems: 2
cdns,autoconf:
type: boolean
......
Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
View file @ 8e3a3249
......@@ -28,13 +28,27 @@ properties:
'#size-cells':
const: 0
'#clock-cells':
const: 1
clocks:
maxItems: 1
minItems: 1
maxItems: 2
description:
PHY reference clock. Must contain an entry in clock-names.
PHY reference clock for 1 item. Must contain an entry in clock-names.
Optional Parent to enable output reference clock.
clock-names:
const: refclk
minItems: 1
items:
- const: refclk
- const: phy_en_refclk
assigned-clocks:
maxItems: 3
assigned-clock-parents:
maxItems: 3
reg:
minItems: 1
......@@ -170,7 +184,7 @@ examples:
};
- |
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/phy/phy-cadence-torrent.h>
#include <dt-bindings/phy/phy-cadence.h>
bus {
#address-cells = <2>;
......
Documentation/devicetree/bindings/phy/phy-mvebu-utmi.txt deleted 100644 → 0
View file @ 90035c28
MVEBU A3700 UTMI PHY
--------------------
USB2 UTMI+ PHY controllers can be found on the following Marvell MVEBU SoCs:
* Armada 3700
On Armada 3700, there are two USB controllers, one is compatible with the USB2
and USB3 specifications and supports OTG. The other one is USB2 compliant and
only supports host mode. Both of these controllers come with a slightly
different UTMI PHY.
Required Properties:
- compatible: Should be one of:
* "marvell,a3700-utmi-host-phy" for the PHY connected to
the USB2 host-only controller.
* "marvell,a3700-utmi-otg-phy" for the PHY connected to
the USB3 and USB2 OTG capable controller.
- reg: PHY IP register range.
- marvell,usb-misc-reg: handle on the "USB miscellaneous registers" shared
region covering registers related to both the host
controller and the PHY.
- #phy-cells: Standard property (Documentation: phy-bindings.txt) Should be 0.
Example:
usb2_utmi_host_phy: phy@5f000 {
compatible = "marvell,armada-3700-utmi-host-phy";
reg = <0x5f000 0x800>;
marvell,usb-misc-reg = <&usb2_syscon>;
#phy-cells = <0>;
};
usb2_syscon: system-controller@5f800 {
compatible = "marvell,armada-3700-usb2-host-misc", "syscon";
reg = <0x5f800 0x800>;
};
Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml
View file @ 8e3a3249
......@@ -51,6 +51,10 @@ properties:
vdda1v8-supply:
description: regulator providing 1V8 power supply to the PLL block
'#clock-cells':
description: number of clock cells for ck_usbo_48m consumer
const: 0
#Required child nodes:
patternProperties:
......@@ -120,6 +124,7 @@ examples:
vdda1v8-supply = <&reg18>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <0>;
usbphyc_port0: usb-phy@0 {
reg = <0>;
......
Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
View file @ 8e3a3249
......@@ -25,11 +25,13 @@ properties:
- qcom,msm8998-qmp-pcie-phy
- qcom,msm8998-qmp-ufs-phy
- qcom,msm8998-qmp-usb3-phy
- qcom,sc7180-qmp-usb3-phy
- qcom,sc8180x-qmp-ufs-phy
- qcom,sc8180x-qmp-usb3-phy
- qcom,sdm845-qhp-pcie-phy
- qcom,sdm845-qmp-pcie-phy
- qcom,sdm845-qmp-ufs-phy
- qcom,sdm845-qmp-usb3-phy
- qcom,sdm845-qmp-usb3-uni-phy
- qcom,sm8150-qmp-ufs-phy
- qcom,sm8150-qmp-usb3-phy
......
Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
View file @ 8e3a3249
......@@ -14,9 +14,8 @@ properties:
compatible:
enum:
- qcom,sc7180-qmp-usb3-dp-phy
- qcom,sc7180-qmp-usb3-phy
- qcom,sdm845-qmp-usb3-dp-phy
- qcom,sdm845-qmp-usb3-phy
- qcom,sm8250-qmp-usb3-dp-phy
reg:
items:
- description: Address and length of PHY's USB serdes block.
......
Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml
View file @ 8e3a3249
......@@ -16,6 +16,7 @@ properties:
compatible:
enum:
- qcom,usb-snps-hs-7nm-phy
- qcom,sc7280-usb-hs-phy
- qcom,sm8150-usb-hs-phy
- qcom,sm8250-usb-hs-phy
- qcom,sm8350-usb-hs-phy
......
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
View file @ 8e3a3249
......@@ -15,6 +15,7 @@ properties:
enum:
- ti,j721e-wiz-16g
- ti,j721e-wiz-10g
- ti,am64-wiz-10g
power-domains:
maxItems: 1
......@@ -42,6 +43,9 @@ properties:
"#reset-cells":
const: 1
"#clock-cells":
const: 1
ranges: true
assigned-clocks:
......
Documentation/devicetree/bindings/soundwire/qcom,sdw.txt
View file @ 8e3a3249
......@@ -54,6 +54,8 @@ board specific bus parameters.
Value type: <prop-encoded-array>
Definition: should specify payload transport window offset1 of each
data port. Out ports followed by In ports.
Value of 0xFF indicates that this option is not implemented
or applicable for the respective data port.
More info in MIPI Alliance SoundWire 1.0 Specifications.
- qcom,ports-offset2:
......@@ -61,6 +63,8 @@ board specific bus parameters.
Value type: <prop-encoded-array>
Definition: should specify payload transport window offset2 of each
data port. Out ports followed by In ports.
Value of 0xFF indicates that this option is not implemented
or applicable for the respective data port.
More info in MIPI Alliance SoundWire 1.0 Specifications.
- qcom,ports-sinterval-low:
......@@ -69,12 +73,16 @@ board specific bus parameters.
Definition: should be sample interval low of each data port.
Out ports followed by In ports. Used for Sample Interval
calculation.
Value of 0xFF indicates that this option is not implemented
or applicable for the respective data port.
More info in MIPI Alliance SoundWire 1.0 Specifications.
- qcom,ports-word-length:
Usage: optional
Value type: <prop-encoded-array>
Definition: should be size of payload channel sample.
Value of 0xFF indicates that this option is not implemented
or applicable for the respective data port.
More info in MIPI Alliance SoundWire 1.0 Specifications.
- qcom,ports-block-pack-mode:
......@@ -84,6 +92,8 @@ board specific bus parameters.
0 to indicate Blocks are per Channel
1 to indicate Blocks are per Port.
Out ports followed by In ports.
Value of 0xFF indicates that this option is not implemented
or applicable for the respective data port.
More info in MIPI Alliance SoundWire 1.0 Specifications.
- qcom,ports-block-group-count:
......@@ -92,6 +102,8 @@ board specific bus parameters.
Definition: should be in range 1 to 4 to indicate how many sample
intervals are combined into a payload.
Out ports followed by In ports.
Value of 0xFF indicates that this option is not implemented
or applicable for the respective data port.
More info in MIPI Alliance SoundWire 1.0 Specifications.
- qcom,ports-lane-control:
......@@ -100,6 +112,8 @@ board specific bus parameters.
Definition: should be in range 0 to 7 to identify which data lane
the data port uses.
Out ports followed by In ports.
Value of 0xFF indicates that this option is not implemented
or applicable for the respective data port.
More info in MIPI Alliance SoundWire 1.0 Specifications.
- qcom,ports-hstart:
......@@ -109,6 +123,8 @@ board specific bus parameters.
SoundWire Frame, i.e. left edge of the Transport sub-frame
for each port. Values between 0 and 15 are valid.
Out ports followed by In ports.
Value of 0xFF indicates that this option is not implemented
or applicable for the respective data port.
More info in MIPI Alliance SoundWire 1.0 Specifications.
- qcom,ports-hstop:
......@@ -118,6 +134,8 @@ board specific bus parameters.
SoundWire Frame, i.e. the right edge of the Transport
sub-frame for each port. Values between 0 and 15 are valid.
Out ports followed by In ports.
Value of 0xFF indicates that this option is not implemented
or applicable for the respective data port.
More info in MIPI Alliance SoundWire 1.0 Specifications.
- qcom,dports-type:
......@@ -128,6 +146,8 @@ board specific bus parameters.
1 for simple ports
2 for full port
Out ports followed by In ports.
Value of 0xFF indicates that this option is not implemented
or applicable for the respective data port.
More info in MIPI Alliance SoundWire 1.0 Specifications.
Note:
......
Documentation/fpga/dfl.rst
View file @ 8e3a3249
......@@ -7,6 +7,7 @@ Authors:
- Enno Luebbers <enno.luebbers@intel.com>
- Xiao Guangrong <guangrong.xiao@linux.intel.com>
- Wu Hao <hao.wu@intel.com>
- Xu Yilun <yilun.xu@intel.com>
The Device Feature List (DFL) FPGA framework (and drivers according to
this framework) hides the very details of low layer hardwares and provides
......@@ -530,6 +531,31 @@ Being able to specify more than one DFL per BAR has been considered, but it
was determined the use case did not provide value. Specifying a single DFL
per BAR simplifies the implementation and allows for extra error checking.
Userspace driver support for DFL devices
========================================
The purpose of an FPGA is to be reprogrammed with newly developed hardware
components. New hardware can instantiate a new private feature in the DFL, and
then present a DFL device in the system. In some cases users may need a
userspace driver for the DFL device:
* Users may need to run some diagnostic test for their hardware.
* Users may prototype the kernel driver in user space.
* Some hardware is designed for specific purposes and does not fit into one of
the standard kernel subsystems.
This requires direct access to MMIO space and interrupt handling from
userspace. The uio_dfl module exposes the UIO device interfaces for this
purpose.
Currently the uio_dfl driver only supports the Ether Group sub feature, which
has no irq in hardware. So the interrupt handling is not added in this driver.
UIO_DFL should be selected to enable the uio_dfl module driver. To support a
new DFL feature via UIO direct access, its feature id should be added to the
driver's id_table.
Open discussion
===============
FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration
......
Documentation/misc-devices/dw-xdata-pcie.rst 0 → 100644
View file @ 8e3a3249
.. SPDX-License-Identifier: GPL-2.0
===========================================================================
Driver for Synopsys DesignWare PCIe traffic generator (also known as xData)
===========================================================================
Supported chips:
Synopsys DesignWare PCIe prototype solution
Datasheet:
Not freely available
Author:
Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Description
-----------
This driver should be used as a host-side (Root Complex) driver and Synopsys
DesignWare prototype that includes this IP.
The dw-xdata-pcie driver can be used to enable/disable PCIe traffic
generator in either direction (mutual exclusion) besides allowing the
PCIe link performance analysis.
The interaction with this driver is done through the module parameter and
can be changed in runtime. The driver outputs the requested command state
information to ``/var/log/kern.log`` or dmesg.
Example
-------
Write TLPs traffic generation - Root Complex to Endpoint direction
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Generate traffic::
# echo 1 > /sys/class/misc/dw-xdata-pcie.0/write
Get link throughput in MB/s::
# cat /sys/class/misc/dw-xdata-pcie.0/write
204
Stop traffic in any direction::
# echo 0 > /sys/class/misc/dw-xdata-pcie.0/write
Read TLPs traffic generation - Endpoint to Root Complex direction
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Generate traffic::
# echo 1 > /sys/class/misc/dw-xdata-pcie.0/read
Get link throughput in MB/s::
# cat /sys/class/misc/dw-xdata-pcie.0/read
199
Stop traffic in any direction::
# echo 0 > /sys/class/misc/dw-xdata-pcie.0/read
Documentation/misc-devices/index.rst
View file @ 8e3a3249
......@@ -19,6 +19,7 @@ fit into other categories.
bh1770glc
eeprom
c2port
dw-xdata-pcie
ibmvmc
ics932s401
isl29003
......
MAINTAINERS
View file @ 8e3a3249
......@@ -1777,6 +1777,7 @@ F: Documentation/devicetree/bindings/arm/coresight.txt
F: Documentation/trace/coresight/*
F: drivers/hwtracing/coresight/*
F: include/dt-bindings/arm/coresight-cti-dt.h
F: include/linux/coresight*
F: tools/perf/arch/arm/util/auxtrace.c
F: tools/perf/arch/arm/util/cs-etm.c
F: tools/perf/arch/arm/util/cs-etm.h
......@@ -5119,6 +5120,13 @@ S: Maintained
F: drivers/dma/dw-edma/
F: include/linux/dma/edma.h
DESIGNWARE XDATA IP DRIVER
M: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
L: linux-pci@vger.kernel.org
S: Maintained
F: Documentation/misc-devices/dw-xdata-pcie.rst
F: drivers/misc/dw-xdata-pcie.c
DESIGNWARE USB2 DRD IP DRIVER
M: Minas Harutyunyan <hminas@synopsys.com>
L: linux-usb@vger.kernel.org
......@@ -7010,6 +7018,7 @@ S: Maintained
F: Documentation/ABI/testing/sysfs-bus-dfl*
F: Documentation/fpga/dfl.rst
F: drivers/fpga/dfl*
F: drivers/uio/uio_dfl.c
F: include/linux/dfl.h
F: include/uapi/linux/fpga-dfl.h
......@@ -7917,6 +7926,11 @@ W: https://linuxtv.org
T: git git://linuxtv.org/media_tree.git
F: drivers/media/usb/hdpvr/
HEWLETT PACKARD ENTERPRISE ILO CHIF DRIVER
M: Matt Hsiao <matt.hsiao@hpe.com>
S: Supported
F: drivers/misc/hpilo.[ch]
HEWLETT PACKARD ENTERPRISE ILO NMI WATCHDOG DRIVER
M: Jerry Hoemann <jerry.hoemann@hpe.com>
S: Supported
......@@ -8571,7 +8585,8 @@ S: Supported
F: drivers/scsi/ibmvscsi/ibmvfc*
IBM Power Virtual Management Channel Driver
M: Steven Royer <seroyer@linux.ibm.com>
M: Brad Warrum <bwarrum@linux.ibm.com>
M: Ritu Agarwal <rituagar@linux.ibm.com>
S: Supported
F: drivers/misc/ibmvmc.*
......@@ -9309,6 +9324,7 @@ INTERCONNECT API
M: Georgi Djakov <djakov@kernel.org>
L: linux-pm@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc.git
F: Documentation/devicetree/bindings/interconnect/
F: Documentation/driver-api/interconnect.rst
F: drivers/interconnect/
......
drivers/accessibility/speakup/i18n.c
View file @ 8e3a3249
......@@ -548,12 +548,10 @@ ssize_t spk_msg_set(enum msg_index_t index, char *text, size_t length)
if ((index < MSG_FIRST_INDEX) || (index >= MSG_LAST_INDEX))
return -EINVAL;
newstr = kmalloc(length + 1, GFP_KERNEL);
newstr = kmemdup_nul(text, length, GFP_KERNEL);
if (!newstr)
return -ENOMEM;
memcpy(newstr, text, length);
newstr[length] = '\0';
if (index >= MSG_FORMATTED_START &&
index <= MSG_FORMATTED_END &&
!fmt_validate(speakup_default_msgs[index], newstr)) {
......
drivers/android/binder.c
View file @ 8e3a3249
This diff is collapsed.
drivers/android/binder_alloc.c
View file @ 8e3a3249
......@@ -338,7 +338,7 @@ static inline struct vm_area_struct *binder_alloc_get_vma(
return vma;
}
static void debug_low_async_space_locked(struct binder_alloc *alloc, int pid)
static bool debug_low_async_space_locked(struct binder_alloc *alloc, int pid)
{
/*
* Find the amount and size of buffers allocated by the current caller;
......@@ -366,13 +366,19 @@ static void debug_low_async_space_locked(struct binder_alloc *alloc, int pid)
/*
* Warn if this pid has more than 50 transactions, or more than 50% of
* async space (which is 25% of total buffer size).
* async space (which is 25% of total buffer size). Oneway spam is only
* detected when the threshold is exceeded.
*/
if (num_buffers > 50 || total_alloc_size > alloc->buffer_size / 4) {
binder_alloc_debug(BINDER_DEBUG_USER_ERROR,
"%d: pid %d spamming oneway? %zd buffers allocated for a total size of %zd\n",
alloc->pid, pid, num_buffers, total_alloc_size);
if (!alloc->oneway_spam_detected) {
alloc->oneway_spam_detected = true;
return true;
}
}
return false;
}
static struct binder_buffer *binder_alloc_new_buf_locked(
......@@ -525,6 +531,7 @@ static struct binder_buffer *binder_alloc_new_buf_locked(
buffer->async_transaction = is_async;
buffer->extra_buffers_size = extra_buffers_size;
buffer->pid = pid;
buffer->oneway_spam_suspect = false;
if (is_async) {
alloc->free_async_space -= size + sizeof(struct binder_buffer);
binder_alloc_debug(BINDER_DEBUG_BUFFER_ALLOC_ASYNC,
......@@ -536,7 +543,9 @@ static struct binder_buffer *binder_alloc_new_buf_locked(
* of async space left (which is less than 10% of total
* buffer size).
*/
debug_low_async_space_locked(alloc, pid);
buffer->oneway_spam_suspect = debug_low_async_space_locked(alloc, pid);
} else {
alloc->oneway_spam_detected = false;
}
}
return buffer;
......
drivers/android/binder_alloc.h
View file @ 8e3a3249
......@@ -26,6 +26,8 @@ struct binder_transaction;
* @clear_on_free: %true if buffer must be zeroed after use
* @allow_user_free: %true if user is allowed to free buffer
* @async_transaction: %true if buffer is in use for an async txn
* @oneway_spam_suspect: %true if total async allocate size just exceed
* spamming detect threshold
* @debug_id: unique ID for debugging
* @transaction: pointer to associated struct binder_transaction
* @target_node: struct binder_node associated with this buffer
......@@ -45,7 +47,8 @@ struct binder_buffer {
unsigned clear_on_free:1;
unsigned allow_user_free:1;
unsigned async_transaction:1;
unsigned debug_id:28;
unsigned oneway_spam_suspect:1;
unsigned debug_id:27;
struct binder_transaction *transaction;
......@@ -87,6 +90,8 @@ struct binder_lru_page {
* @buffer_size: size of address space specified via mmap
* @pid: pid for associated binder_proc (invariant after init)
* @pages_high: high watermark of offset in @pages
* @oneway_spam_detected: %true if oneway spam detection fired, clear that
* flag once the async buffer has returned to a healthy state
*
* Bookkeeping structure for per-proc address space management for binder
* buffers. It is normally initialized during binder_init() and binder_mmap()
......@@ -107,6 +112,7 @@ struct binder_alloc {
uint32_t buffer_free;
int pid;
size_t pages_high;
bool oneway_spam_detected;
};
#ifdef CONFIG_ANDROID_BINDER_IPC_SELFTEST
......
drivers/android/binder_internal.h
View file @ 8e3a3249
......@@ -155,7 +155,7 @@ enum binder_stat_types {
};
struct binder_stats {
atomic_t br[_IOC_NR(BR_FAILED_REPLY) + 1];
atomic_t br[_IOC_NR(BR_ONEWAY_SPAM_SUSPECT) + 1];
atomic_t bc[_IOC_NR(BC_REPLY_SG) + 1];
atomic_t obj_created[BINDER_STAT_COUNT];
atomic_t obj_deleted[BINDER_STAT_COUNT];
......@@ -174,6 +174,7 @@ struct binder_work {
enum binder_work_type {
BINDER_WORK_TRANSACTION = 1,
BINDER_WORK_TRANSACTION_COMPLETE,
BINDER_WORK_TRANSACTION_ONEWAY_SPAM_SUSPECT,
BINDER_WORK_RETURN_ERROR,
BINDER_WORK_NODE,
BINDER_WORK_DEAD_BINDER,
......@@ -367,9 +368,22 @@ struct binder_ref {
* (protected by binder_deferred_lock)
* @deferred_work: bitmap of deferred work to perform
* (protected by binder_deferred_lock)
* @outstanding_txns: number of transactions to be transmitted before
* processes in freeze_wait are woken up
* (protected by @inner_lock)
* @is_dead: process is dead and awaiting free
* when outstanding transactions are cleaned up
* (protected by @inner_lock)
* @is_frozen: process is frozen and unable to service
* binder transactions
* (protected by @inner_lock)
* @sync_recv: process received sync transactions since last frozen
* (protected by @inner_lock)
* @async_recv: process received async transactions since last frozen
* (protected by @inner_lock)
* @freeze_wait: waitqueue of processes waiting for all outstanding
* transactions to be processed
* (protected by @inner_lock)
* @todo: list of work for this process
* (protected by @inner_lock)
* @stats: per-process binder statistics
......@@ -396,6 +410,8 @@ struct binder_ref {
* @outer_lock: no nesting under innor or node lock
* Lock order: 1) outer, 2) node, 3) inner
* @binderfs_entry: process-specific binderfs log file
* @oneway_spam_detection_enabled: process enabled oneway spam detection
* or not
*
* Bookkeeping structure for binder processes
*/
......@@ -410,7 +426,12 @@ struct binder_proc {
struct task_struct *tsk;
struct hlist_node deferred_work_node;
int deferred_work;
int outstanding_txns;
bool is_dead;
bool is_frozen;
bool sync_recv;
bool async_recv;
wait_queue_head_t freeze_wait;
struct list_head todo;
struct binder_stats stats;
......@@ -426,6 +447,7 @@ struct binder_proc {
spinlock_t inner_lock;
spinlock_t outer_lock;
struct dentry *binderfs_entry;
bool oneway_spam_detection_enabled;
};
/**
......
drivers/bus/mhi/core/boot.c
View file @ 8e3a3249
......@@ -389,7 +389,6 @@ static void mhi_firmware_copy(struct mhi_controller *mhi_cntrl,
void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl)
{
const struct firmware *firmware = NULL;
struct image_info *image_info;
struct device *dev = &mhi_cntrl->mhi_dev->dev;
const char *fw_name;
void *buf;
......@@ -417,9 +416,9 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl)
}
}
/* If device is in pass through, do reset to ready state transition */
if (mhi_cntrl->ee == MHI_EE_PTHRU)
goto fw_load_ee_pthru;
/* wait for ready on pass through or any other execution environment */
if (mhi_cntrl->ee != MHI_EE_EDL && mhi_cntrl->ee != MHI_EE_PBL)
goto fw_load_ready_state;
fw_name = (mhi_cntrl->ee == MHI_EE_EDL) ?
mhi_cntrl->edl_image : mhi_cntrl->fw_image;
......@@ -461,9 +460,10 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl)
goto error_fw_load;
}
if (mhi_cntrl->ee == MHI_EE_EDL) {
/* Wait for ready since EDL image was loaded */
if (fw_name == mhi_cntrl->edl_image) {
release_firmware(firmware);
return;
goto fw_load_ready_state;
}
write_lock_irq(&mhi_cntrl->pm_lock);
......@@ -488,47 +488,45 @@ void mhi_fw_load_handler(struct mhi_controller *mhi_cntrl)
release_firmware(firmware);
fw_load_ee_pthru:
fw_load_ready_state:
/* Transitioning into MHI RESET->READY state */
ret = mhi_ready_state_transition(mhi_cntrl);
if (!mhi_cntrl->fbc_download)
return;
if (ret) {
dev_err(dev, "MHI did not enter READY state\n");
goto error_ready_state;
}
/* Wait for the SBL event */
ret = wait_event_timeout(mhi_cntrl->state_event,
mhi_cntrl->ee == MHI_EE_SBL ||
MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
msecs_to_jiffies(mhi_cntrl->timeout_ms));
dev_info(dev, "Wait for device to enter SBL or Mission mode\n");
return;
if (!ret || MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state)) {
dev_err(dev, "MHI did not enter SBL\n");
goto error_ready_state;
error_ready_state:
if (mhi_cntrl->fbc_download) {
mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image);
mhi_cntrl->fbc_image = NULL;
}
/* Start full firmware image download */
image_info = mhi_cntrl->fbc_image;
error_fw_load:
mhi_cntrl->pm_state = MHI_PM_FW_DL_ERR;
wake_up_all(&mhi_cntrl->state_event);
}
int mhi_download_amss_image(struct mhi_controller *mhi_cntrl)
{
struct image_info *image_info = mhi_cntrl->fbc_image;
struct device *dev = &mhi_cntrl->mhi_dev->dev;
int ret;
if (!image_info)
return -EIO;
ret = mhi_fw_load_bhie(mhi_cntrl,
/* Vector table is the last entry */
&image_info->mhi_buf[image_info->entries - 1]);
if (ret) {
dev_err(dev, "MHI did not load image over BHIe, ret: %d\n",
ret);
goto error_fw_load;
dev_err(dev, "MHI did not load AMSS, ret:%d\n", ret);
mhi_cntrl->pm_state = MHI_PM_FW_DL_ERR;
wake_up_all(&mhi_cntrl->state_event);
}
return;
error_ready_state:
mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image);
mhi_cntrl->fbc_image = NULL;
error_fw_load:
mhi_cntrl->pm_state = MHI_PM_FW_DL_ERR;
wake_up_all(&mhi_cntrl->state_event);
return ret;
}
drivers/bus/mhi/core/debugfs.c
View file @ 8e3a3249
......@@ -377,7 +377,7 @@ static struct dentry *mhi_debugfs_root;
void mhi_create_debugfs(struct mhi_controller *mhi_cntrl)
{
mhi_cntrl->debugfs_dentry =
debugfs_create_dir(dev_name(mhi_cntrl->cntrl_dev),
debugfs_create_dir(dev_name(&mhi_cntrl->mhi_dev->dev),
mhi_debugfs_root);
debugfs_create_file("states", 0444, mhi_cntrl->debugfs_dentry,
......
drivers/bus/mhi/core/init.c
View file @ 8e3a3249
......@@ -22,13 +22,14 @@
static DEFINE_IDA(mhi_controller_ida);
const char * const mhi_ee_str[MHI_EE_MAX] = {
[MHI_EE_PBL] = "PBL",
[MHI_EE_SBL] = "SBL",
[MHI_EE_AMSS] = "AMSS",
[MHI_EE_RDDM] = "RDDM",
[MHI_EE_WFW] = "WFW",
[MHI_EE_PTHRU] = "PASS THRU",
[MHI_EE_EDL] = "EDL",
[MHI_EE_PBL] = "PRIMARY BOOTLOADER",
[MHI_EE_SBL] = "SECONDARY BOOTLOADER",
[MHI_EE_AMSS] = "MISSION MODE",
[MHI_EE_RDDM] = "RAMDUMP DOWNLOAD MODE",
[MHI_EE_WFW] = "WLAN FIRMWARE",
[MHI_EE_PTHRU] = "PASS THROUGH",
[MHI_EE_EDL] = "EMERGENCY DOWNLOAD",
[MHI_EE_FP] = "FLASH PROGRAMMER",
[MHI_EE_DISABLE_TRANSITION] = "DISABLE",
[MHI_EE_NOT_SUPPORTED] = "NOT SUPPORTED",
};
......@@ -37,8 +38,9 @@ const char * const dev_state_tran_str[DEV_ST_TRANSITION_MAX] = {
[DEV_ST_TRANSITION_PBL] = "PBL",
[DEV_ST_TRANSITION_READY] = "READY",
[DEV_ST_TRANSITION_SBL] = "SBL",
[DEV_ST_TRANSITION_MISSION_MODE] = "MISSION_MODE",
[DEV_ST_TRANSITION_SYS_ERR] = "SYS_ERR",
[DEV_ST_TRANSITION_MISSION_MODE] = "MISSION MODE",
[DEV_ST_TRANSITION_FP] = "FLASH PROGRAMMER",
[DEV_ST_TRANSITION_SYS_ERR] = "SYS ERROR",
[DEV_ST_TRANSITION_DISABLE] = "DISABLE",
};
......@@ -49,24 +51,30 @@ const char * const mhi_state_str[MHI_STATE_MAX] = {
[MHI_STATE_M1] = "M1",
[MHI_STATE_M2] = "M2",
[MHI_STATE_M3] = "M3",
[MHI_STATE_M3_FAST] = "M3_FAST",
[MHI_STATE_M3_FAST] = "M3 FAST",
[MHI_STATE_BHI] = "BHI",
[MHI_STATE_SYS_ERR] = "SYS_ERR",
[MHI_STATE_SYS_ERR] = "SYS ERROR",
};
const char * const mhi_ch_state_type_str[MHI_CH_STATE_TYPE_MAX] = {
[MHI_CH_STATE_TYPE_RESET] = "RESET",
[MHI_CH_STATE_TYPE_STOP] = "STOP",
[MHI_CH_STATE_TYPE_START] = "START",
};
static const char * const mhi_pm_state_str[] = {
[MHI_PM_STATE_DISABLE] = "DISABLE",
[MHI_PM_STATE_POR] = "POR",
[MHI_PM_STATE_POR] = "POWER ON RESET",
[MHI_PM_STATE_M0] = "M0",
[MHI_PM_STATE_M2] = "M2",
[MHI_PM_STATE_M3_ENTER] = "M?->M3",
[MHI_PM_STATE_M3] = "M3",
[MHI_PM_STATE_M3_EXIT] = "M3->M0",
[MHI_PM_STATE_FW_DL_ERR] = "FW DL Error",
[MHI_PM_STATE_SYS_ERR_DETECT] = "SYS_ERR Detect",
[MHI_PM_STATE_SYS_ERR_PROCESS] = "SYS_ERR Process",
[MHI_PM_STATE_FW_DL_ERR] = "Firmware Download Error",
[MHI_PM_STATE_SYS_ERR_DETECT] = "SYS ERROR Detect",
[MHI_PM_STATE_SYS_ERR_PROCESS] = "SYS ERROR Process",
[MHI_PM_STATE_SHUTDOWN_PROCESS] = "SHUTDOWN Process",
[MHI_PM_STATE_LD_ERR_FATAL_DETECT] = "LD or Error Fatal Detect",
[MHI_PM_STATE_LD_ERR_FATAL_DETECT] = "Linkdown or Error Fatal Detect",
};
const char *to_mhi_pm_state_str(enum mhi_pm_state state)
......@@ -508,8 +516,6 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl)
/* Setup wake db */
mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB);
mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 4, 0);
mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 0, 0);
mhi_cntrl->wake_set = false;
/* Setup channel db address for each channel in tre_ring */
......@@ -552,6 +558,7 @@ void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl,
struct mhi_ring *buf_ring;
struct mhi_ring *tre_ring;
struct mhi_chan_ctxt *chan_ctxt;
u32 tmp;
buf_ring = &mhi_chan->buf_ring;
tre_ring = &mhi_chan->tre_ring;
......@@ -565,7 +572,19 @@ void mhi_deinit_chan_ctxt(struct mhi_controller *mhi_cntrl,
vfree(buf_ring->base);
buf_ring->base = tre_ring->base = NULL;
tre_ring->ctxt_wp = NULL;
chan_ctxt->rbase = 0;
chan_ctxt->rlen = 0;
chan_ctxt->rp = 0;
chan_ctxt->wp = 0;
tmp = chan_ctxt->chcfg;
tmp &= ~CHAN_CTX_CHSTATE_MASK;
tmp |= (MHI_CH_STATE_DISABLED << CHAN_CTX_CHSTATE_SHIFT);
chan_ctxt->chcfg = tmp;
/* Update to all cores */
smp_wmb();
}
int mhi_init_chan_ctxt(struct mhi_controller *mhi_cntrl,
......@@ -863,12 +882,10 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl,
u32 soc_info;
int ret, i;
if (!mhi_cntrl)
return -EINVAL;
if (!mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put ||
if (!mhi_cntrl || !mhi_cntrl->cntrl_dev || !mhi_cntrl->regs ||
!mhi_cntrl->runtime_get || !mhi_cntrl->runtime_put ||
!mhi_cntrl->status_cb || !mhi_cntrl->read_reg ||
!mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs)
!mhi_cntrl->write_reg || !mhi_cntrl->nr_irqs || !mhi_cntrl->irq)
return -EINVAL;
ret = parse_config(mhi_cntrl, config);
......@@ -890,8 +907,7 @@ int mhi_register_controller(struct mhi_controller *mhi_cntrl,
INIT_WORK(&mhi_cntrl->st_worker, mhi_pm_st_worker);
init_waitqueue_head(&mhi_cntrl->state_event);
mhi_cntrl->hiprio_wq = alloc_ordered_workqueue
("mhi_hiprio_wq", WQ_MEM_RECLAIM | WQ_HIGHPRI);
mhi_cntrl->hiprio_wq = alloc_ordered_workqueue("mhi_hiprio_wq", WQ_HIGHPRI);
if (!mhi_cntrl->hiprio_wq) {
dev_err(mhi_cntrl->cntrl_dev, "Failed to allocate workqueue\n");
ret = -ENOMEM;
......@@ -1083,8 +1099,6 @@ int mhi_prepare_for_power_up(struct mhi_controller *mhi_cntrl)
mhi_rddm_prepare(mhi_cntrl, mhi_cntrl->rddm_image);
}
mhi_cntrl->pre_init = true;
mutex_unlock(&mhi_cntrl->pm_mutex);
return 0;
......@@ -1115,7 +1129,6 @@ void mhi_unprepare_after_power_down(struct mhi_controller *mhi_cntrl)
}
mhi_deinit_dev_ctxt(mhi_cntrl);
mhi_cntrl->pre_init = false;
}
EXPORT_SYMBOL_GPL(mhi_unprepare_after_power_down);
......@@ -1296,7 +1309,8 @@ static int mhi_driver_remove(struct device *dev)
mutex_lock(&mhi_chan->mutex);
if (ch_state[dir] == MHI_CH_STATE_ENABLED &&
if ((ch_state[dir] == MHI_CH_STATE_ENABLED ||
ch_state[dir] == MHI_CH_STATE_STOP) &&
!mhi_chan->offload_ch)
mhi_deinit_chan_ctxt(mhi_cntrl, mhi_chan);
......
drivers/bus/mhi/core/internal.h
View file @ 8e3a3249
......@@ -369,6 +369,18 @@ enum mhi_ch_state {
MHI_CH_STATE_ERROR = 0x5,
};
enum mhi_ch_state_type {
MHI_CH_STATE_TYPE_RESET,
MHI_CH_STATE_TYPE_STOP,
MHI_CH_STATE_TYPE_START,
MHI_CH_STATE_TYPE_MAX,
};
extern const char * const mhi_ch_state_type_str[MHI_CH_STATE_TYPE_MAX];
#define TO_CH_STATE_TYPE_STR(state) (((state) >= MHI_CH_STATE_TYPE_MAX) ? \
"INVALID_STATE" : \
mhi_ch_state_type_str[(state)])
#define MHI_INVALID_BRSTMODE(mode) (mode != MHI_DB_BRST_DISABLE && \
mode != MHI_DB_BRST_ENABLE)
......@@ -379,13 +391,15 @@ extern const char * const mhi_ee_str[MHI_EE_MAX];
#define MHI_IN_PBL(ee) (ee == MHI_EE_PBL || ee == MHI_EE_PTHRU || \
ee == MHI_EE_EDL)
#define MHI_IN_MISSION_MODE(ee) (ee == MHI_EE_AMSS || ee == MHI_EE_WFW)
#define MHI_IN_MISSION_MODE(ee) (ee == MHI_EE_AMSS || ee == MHI_EE_WFW || \
ee == MHI_EE_FP)
enum dev_st_transition {
DEV_ST_TRANSITION_PBL,
DEV_ST_TRANSITION_READY,
DEV_ST_TRANSITION_SBL,
DEV_ST_TRANSITION_MISSION_MODE,
DEV_ST_TRANSITION_FP,
DEV_ST_TRANSITION_SYS_ERR,
DEV_ST_TRANSITION_DISABLE,
DEV_ST_TRANSITION_MAX,
......@@ -619,6 +633,7 @@ int mhi_pm_m3_transition(struct mhi_controller *mhi_cntrl);
int __mhi_device_get_sync(struct mhi_controller *mhi_cntrl);
int mhi_send_cmd(struct mhi_controller *mhi_cntrl, struct mhi_chan *mhi_chan,
enum mhi_cmd_type cmd);
int mhi_download_amss_image(struct mhi_controller *mhi_cntrl);
static inline bool mhi_is_active(struct mhi_controller *mhi_cntrl)
{
return (mhi_cntrl->dev_state >= MHI_STATE_M0 &&
......@@ -643,6 +658,9 @@ int __must_check mhi_read_reg(struct mhi_controller *mhi_cntrl,
int __must_check mhi_read_reg_field(struct mhi_controller *mhi_cntrl,
void __iomem *base, u32 offset, u32 mask,
u32 shift, u32 *out);
int __must_check mhi_poll_reg_field(struct mhi_controller *mhi_cntrl,
void __iomem *base, u32 offset, u32 mask,
u32 shift, u32 val, u32 delayus);
void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base,
u32 offset, u32 val);
void mhi_write_reg_field(struct mhi_controller *mhi_cntrl, void __iomem *base,
......
drivers/bus/mhi/core/main.c
View file @ 8e3a3249
This diff is collapsed.
drivers/bus/mhi/core/pm.c
View file @ 8e3a3249
......@@ -153,35 +153,33 @@ static void mhi_toggle_dev_wake(struct mhi_controller *mhi_cntrl)
/* Handle device ready state transition */
int mhi_ready_state_transition(struct mhi_controller *mhi_cntrl)
{
void __iomem *base = mhi_cntrl->regs;
struct mhi_event *mhi_event;
enum mhi_pm_state cur_state;
struct device *dev = &mhi_cntrl->mhi_dev->dev;
u32 reset = 1, ready = 0;
u32 interval_us = 25000; /* poll register field every 25 milliseconds */
int ret, i;
/* Wait for RESET to be cleared and READY bit to be set by the device */
wait_event_timeout(mhi_cntrl->state_event,
MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state) ||
mhi_read_reg_field(mhi_cntrl, base, MHICTRL,
MHICTRL_RESET_MASK,
MHICTRL_RESET_SHIFT, &reset) ||
mhi_read_reg_field(mhi_cntrl, base, MHISTATUS,
MHISTATUS_READY_MASK,
MHISTATUS_READY_SHIFT, &ready) ||
(!reset && ready),
msecs_to_jiffies(mhi_cntrl->timeout_ms));
/* Check if device entered error state */
if (MHI_PM_IN_FATAL_STATE(mhi_cntrl->pm_state)) {
dev_err(dev, "Device link is not accessible\n");
return -EIO;
}
/* Timeout if device did not transition to ready state */
if (reset || !ready) {
dev_err(dev, "Device Ready timeout\n");
return -ETIMEDOUT;
/* Wait for RESET to be cleared and READY bit to be set by the device */
ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
MHICTRL_RESET_MASK, MHICTRL_RESET_SHIFT, 0,
interval_us);
if (ret) {
dev_err(dev, "Device failed to clear MHI Reset\n");
return ret;
}
ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHISTATUS,
MHISTATUS_READY_MASK, MHISTATUS_READY_SHIFT, 1,
interval_us);
if (ret) {
dev_err(dev, "Device failed to enter MHI Ready\n");
return ret;
}
dev_dbg(dev, "Device in READY State\n");
......@@ -377,24 +375,28 @@ static int mhi_pm_mission_mode_transition(struct mhi_controller *mhi_cntrl)
{
struct mhi_event *mhi_event;
struct device *dev = &mhi_cntrl->mhi_dev->dev;
enum mhi_ee_type ee = MHI_EE_MAX, current_ee = mhi_cntrl->ee;
int i, ret;
dev_dbg(dev, "Processing Mission Mode transition\n");
write_lock_irq(&mhi_cntrl->pm_lock);
if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state))
mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl);
ee = mhi_get_exec_env(mhi_cntrl);
if (!MHI_IN_MISSION_MODE(mhi_cntrl->ee)) {
if (!MHI_IN_MISSION_MODE(ee)) {
mhi_cntrl->pm_state = MHI_PM_LD_ERR_FATAL_DETECT;
write_unlock_irq(&mhi_cntrl->pm_lock);
wake_up_all(&mhi_cntrl->state_event);
return -EIO;
}
mhi_cntrl->ee = ee;
write_unlock_irq(&mhi_cntrl->pm_lock);
wake_up_all(&mhi_cntrl->state_event);
device_for_each_child(&mhi_cntrl->mhi_dev->dev, &current_ee,
mhi_destroy_device);
mhi_cntrl->status_cb(mhi_cntrl, MHI_CB_EE_MISSION_MODE);
/* Force MHI to be in M0 state before continuing */
......@@ -560,6 +562,7 @@ static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl)
static void mhi_pm_sys_error_transition(struct mhi_controller *mhi_cntrl)
{
enum mhi_pm_state cur_state, prev_state;
enum dev_st_transition next_state;
struct mhi_event *mhi_event;
struct mhi_cmd_ctxt *cmd_ctxt;
struct mhi_cmd *mhi_cmd;
......@@ -673,7 +676,23 @@ static void mhi_pm_sys_error_transition(struct mhi_controller *mhi_cntrl)
er_ctxt->wp = er_ctxt->rbase;
}
mhi_ready_state_transition(mhi_cntrl);
/* Transition to next state */
if (MHI_IN_PBL(mhi_get_exec_env(mhi_cntrl))) {
write_lock_irq(&mhi_cntrl->pm_lock);
cur_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_POR);
write_unlock_irq(&mhi_cntrl->pm_lock);
if (cur_state != MHI_PM_POR) {
dev_err(dev, "Error moving to state %s from %s\n",
to_mhi_pm_state_str(MHI_PM_POR),
to_mhi_pm_state_str(cur_state));
goto exit_sys_error_transition;
}
next_state = DEV_ST_TRANSITION_PBL;
} else {
next_state = DEV_ST_TRANSITION_READY;
}
mhi_queue_state_transition(mhi_cntrl, next_state);
exit_sys_error_transition:
dev_dbg(dev, "Exiting with PM state: %s, MHI state: %s\n",
......@@ -742,8 +761,7 @@ void mhi_pm_st_worker(struct work_struct *work)
if (MHI_REG_ACCESS_VALID(mhi_cntrl->pm_state))
mhi_cntrl->ee = mhi_get_exec_env(mhi_cntrl);
write_unlock_irq(&mhi_cntrl->pm_lock);
if (MHI_IN_PBL(mhi_cntrl->ee))
mhi_fw_load_handler(mhi_cntrl);
mhi_fw_load_handler(mhi_cntrl);
break;
case DEV_ST_TRANSITION_SBL:
write_lock_irq(&mhi_cntrl->pm_lock);
......@@ -755,10 +773,18 @@ void mhi_pm_st_worker(struct work_struct *work)
* either SBL or AMSS states
*/
mhi_create_devices(mhi_cntrl);
if (mhi_cntrl->fbc_download)
mhi_download_amss_image(mhi_cntrl);
break;
case DEV_ST_TRANSITION_MISSION_MODE:
mhi_pm_mission_mode_transition(mhi_cntrl);
break;
case DEV_ST_TRANSITION_FP:
write_lock_irq(&mhi_cntrl->pm_lock);
mhi_cntrl->ee = MHI_EE_FP;
write_unlock_irq(&mhi_cntrl->pm_lock);
mhi_create_devices(mhi_cntrl);
break;
case DEV_ST_TRANSITION_READY:
mhi_ready_state_transition(mhi_cntrl);
break;
......@@ -822,7 +848,7 @@ int mhi_pm_suspend(struct mhi_controller *mhi_cntrl)
return -EBUSY;
}
dev_info(dev, "Allowing M3 transition\n");
dev_dbg(dev, "Allowing M3 transition\n");
new_state = mhi_tryset_pm_state(mhi_cntrl, MHI_PM_M3_ENTER);
if (new_state != MHI_PM_M3_ENTER) {
write_unlock_irq(&mhi_cntrl->pm_lock);
......@@ -836,7 +862,7 @@ int mhi_pm_suspend(struct mhi_controller *mhi_cntrl)
/* Set MHI to M3 and wait for completion */
mhi_set_mhi_state(mhi_cntrl, MHI_STATE_M3);
write_unlock_irq(&mhi_cntrl->pm_lock);
dev_info(dev, "Wait for M3 completion\n");
dev_dbg(dev, "Waiting for M3 completion\n");
ret = wait_event_timeout(mhi_cntrl->state_event,
mhi_cntrl->dev_state == MHI_STATE_M3 ||
......@@ -870,9 +896,9 @@ int mhi_pm_resume(struct mhi_controller *mhi_cntrl)
enum mhi_pm_state cur_state;
int ret;
dev_info(dev, "Entered with PM state: %s, MHI state: %s\n",
to_mhi_pm_state_str(mhi_cntrl->pm_state),
TO_MHI_STATE_STR(mhi_cntrl->dev_state));
dev_dbg(dev, "Entered with PM state: %s, MHI state: %s\n",
to_mhi_pm_state_str(mhi_cntrl->pm_state),
TO_MHI_STATE_STR(mhi_cntrl->dev_state));
if (mhi_cntrl->pm_state == MHI_PM_DISABLE)
return 0;
......@@ -880,6 +906,9 @@ int mhi_pm_resume(struct mhi_controller *mhi_cntrl)
if (MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state))
return -EIO;
if (mhi_get_mhi_state(mhi_cntrl) != MHI_STATE_M3)
return -EINVAL;
/* Notify clients about exiting LPM */
list_for_each_entry_safe(itr, tmp, &mhi_cntrl->lpm_chans, node) {
mutex_lock(&itr->mutex);
......@@ -1033,13 +1062,6 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
mutex_lock(&mhi_cntrl->pm_mutex);
mhi_cntrl->pm_state = MHI_PM_DISABLE;
if (!mhi_cntrl->pre_init) {
/* Setup device context */
ret = mhi_init_dev_ctxt(mhi_cntrl);
if (ret)
goto error_dev_ctxt;
}
ret = mhi_init_irq_setup(mhi_cntrl);
if (ret)
goto error_setup_irq;
......@@ -1092,7 +1114,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
&val) ||
!val,
msecs_to_jiffies(mhi_cntrl->timeout_ms));
if (ret) {
if (!ret) {
ret = -EIO;
dev_info(dev, "Failed to reset MHI due to syserr state\n");
goto error_bhi_offset;
......@@ -1121,10 +1143,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl)
mhi_deinit_free_irq(mhi_cntrl);
error_setup_irq:
if (!mhi_cntrl->pre_init)
mhi_deinit_dev_ctxt(mhi_cntrl);
error_dev_ctxt:
mhi_cntrl->pm_state = MHI_PM_DISABLE;
mutex_unlock(&mhi_cntrl->pm_mutex);
return ret;
......@@ -1136,12 +1155,19 @@ void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful)
enum mhi_pm_state cur_state, transition_state;
struct device *dev = &mhi_cntrl->mhi_dev->dev;
mutex_lock(&mhi_cntrl->pm_mutex);
write_lock_irq(&mhi_cntrl->pm_lock);
cur_state = mhi_cntrl->pm_state;
if (cur_state == MHI_PM_DISABLE) {
write_unlock_irq(&mhi_cntrl->pm_lock);
mutex_unlock(&mhi_cntrl->pm_mutex);
return; /* Already powered down */
}
/* If it's not a graceful shutdown, force MHI to linkdown state */
transition_state = (graceful) ? MHI_PM_SHUTDOWN_PROCESS :
MHI_PM_LD_ERR_FATAL_DETECT;
mutex_lock(&mhi_cntrl->pm_mutex);
write_lock_irq(&mhi_cntrl->pm_lock);
cur_state = mhi_tryset_pm_state(mhi_cntrl, transition_state);
if (cur_state != transition_state) {
dev_err(dev, "Failed to move to state: %s from: %s\n",
......@@ -1166,15 +1192,6 @@ void mhi_power_down(struct mhi_controller *mhi_cntrl, bool graceful)
flush_work(&mhi_cntrl->st_worker);
free_irq(mhi_cntrl->irq[0], mhi_cntrl);
if (!mhi_cntrl->pre_init) {
/* Free all allocated resources */
if (mhi_cntrl->fbc_image) {
mhi_free_bhie_table(mhi_cntrl, mhi_cntrl->fbc_image);
mhi_cntrl->fbc_image = NULL;
}
mhi_deinit_dev_ctxt(mhi_cntrl);
}
}
EXPORT_SYMBOL_GPL(mhi_power_down);
......
drivers/bus/mhi/pci_generic.c
View file @ 8e3a3249
This diff is collapsed.
drivers/char/applicom.c
View file @ 8e3a3249
......@@ -836,7 +836,7 @@ static long ac_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
Dummy = readb(apbs[IndexCard].RamIO + VERS);
kfree(adgl);
mutex_unlock(&ac_mutex);
return 0;
return ret;
err:
if (warncount) {
......
drivers/char/lp.c
View file @ 8e3a3249
......@@ -546,7 +546,7 @@ static int lp_open(struct inode *inode, struct file *file)
}
/* Determine if the peripheral supports ECP mode */
lp_claim_parport_or_block(&lp_table[minor]);
if ( (lp_table[minor].dev->port->modes & PARPORT_MODE_ECP) &&
if ((lp_table[minor].dev->port->modes & PARPORT_MODE_ECP) &&
!parport_negotiate(lp_table[minor].dev->port,
IEEE1284_MODE_ECP)) {
printk(KERN_INFO "lp%d: ECP mode\n", minor);
......@@ -590,7 +590,7 @@ static int lp_do_ioctl(unsigned int minor, unsigned int cmd,
return -ENODEV;
if ((LP_F(minor) & LP_EXIST) == 0)
return -ENODEV;
switch ( cmd ) {
switch (cmd) {
case LPTIME:
if (arg > UINT_MAX / HZ)
return -EINVAL;
......
drivers/char/mwave/tp3780i.c
View file @ 8e3a3249
......@@ -177,14 +177,10 @@ int tp3780I_InitializeBoardData(THINKPAD_BD_DATA * pBDData)
return retval;
}
int tp3780I_Cleanup(THINKPAD_BD_DATA * pBDData)
void tp3780I_Cleanup(THINKPAD_BD_DATA *pBDData)
{
int retval = 0;
PRINTK_2(TRACE_TP3780I,
"tp3780i::tp3780I_Cleanup entry and exit pBDData %p\n", pBDData);
return retval;
}
int tp3780I_CalcResources(THINKPAD_BD_DATA * pBDData)
......
drivers/char/mwave/tp3780i.h
View file @ 8e3a3249
......@@ -91,7 +91,7 @@ int tp3780I_DisableDSP(THINKPAD_BD_DATA * pBDData);
int tp3780I_ResetDSP(THINKPAD_BD_DATA * pBDData);
int tp3780I_StartDSP(THINKPAD_BD_DATA * pBDData);
int tp3780I_QueryAbilities(THINKPAD_BD_DATA * pBDData, MW_ABILITIES * pAbilities);
int tp3780I_Cleanup(THINKPAD_BD_DATA * pBDData);
void tp3780I_Cleanup(THINKPAD_BD_DATA *pBDData);
int tp3780I_ReadWriteDspDStore(THINKPAD_BD_DATA * pBDData, unsigned int uOpcode,
void __user *pvBuffer, unsigned int uCount,
unsigned long ulDSPAddr);
......
drivers/char/virtio_console.c
View file @ 8e3a3249
......@@ -1456,18 +1456,15 @@ static int add_port(struct ports_device *portdev, u32 id)
*/
send_control_msg(port, VIRTIO_CONSOLE_PORT_READY, 1);
if (pdrvdata.debugfs_dir) {
/*
* Finally, create the debugfs file that we can use to
* inspect a port's state at any time
*/
snprintf(debugfs_name, sizeof(debugfs_name), "vport%up%u",
port->portdev->vdev->index, id);
port->debugfs_file = debugfs_create_file(debugfs_name, 0444,
pdrvdata.debugfs_dir,
port,
&port_debugfs_fops);
}
/*
* Finally, create the debugfs file that we can use to
* inspect a port's state at any time
*/
snprintf(debugfs_name, sizeof(debugfs_name), "vport%up%u",
port->portdev->vdev->index, id);
port->debugfs_file = debugfs_create_file(debugfs_name, 0444,
pdrvdata.debugfs_dir,
port, &port_debugfs_fops);
return 0;
free_inbufs:
......@@ -2244,8 +2241,6 @@ static int __init init(void)
}
pdrvdata.debugfs_dir = debugfs_create_dir("virtio-ports", NULL);
if (!pdrvdata.debugfs_dir)
pr_warn("Error creating debugfs dir for virtio-ports\n");
INIT_LIST_HEAD(&pdrvdata.consoles);
INIT_LIST_HEAD(&pdrvdata.portdevs);
......
drivers/extcon/extcon-max8997.c
View file @ 8e3a3249
......@@ -44,6 +44,8 @@ static struct max8997_muic_irq muic_irqs[] = {
{ MAX8997_MUICIRQ_ChgDetRun, "muic-CHGDETRUN" },
{ MAX8997_MUICIRQ_ChgTyp, "muic-CHGTYP" },
{ MAX8997_MUICIRQ_OVP, "muic-OVP" },
{ MAX8997_PMICIRQ_CHGINS, "pmic-CHGINS" },
{ MAX8997_PMICIRQ_CHGRM, "pmic-CHGRM" },
};
/* Define supported cable type */
......@@ -538,6 +540,8 @@ static void max8997_muic_irq_work(struct work_struct *work)
case MAX8997_MUICIRQ_DCDTmr:
case MAX8997_MUICIRQ_ChgDetRun:
case MAX8997_MUICIRQ_ChgTyp:
case MAX8997_PMICIRQ_CHGINS:
case MAX8997_PMICIRQ_CHGRM:
/* Handle charger cable */
ret = max8997_muic_chg_handler(info);
break;
......
drivers/extcon/extcon-qcom-spmi-misc.c
View file @ 8e3a3249
// SPDX-License-Identifier: GPL-2.0-only
/**
* extcon-qcom-spmi-misc.c - Qualcomm USB extcon driver to support USB ID
* detection based on extcon-usb-gpio.c.
* and VBUS detection based on extcon-usb-gpio.c.
*
* Copyright (C) 2016 Linaro, Ltd.
* Stephen Boyd <stephen.boyd@linaro.org>
......@@ -21,30 +21,56 @@
struct qcom_usb_extcon_info {
struct extcon_dev *edev;
int irq;
int id_irq;
int vbus_irq;
struct delayed_work wq_detcable;
unsigned long debounce_jiffies;
};
static const unsigned int qcom_usb_extcon_cable[] = {
EXTCON_USB,
EXTCON_USB_HOST,
EXTCON_NONE,
};
static void qcom_usb_extcon_detect_cable(struct work_struct *work)
{
bool id;
bool state = false;
int ret;
union extcon_property_value val;
struct qcom_usb_extcon_info *info = container_of(to_delayed_work(work),
struct qcom_usb_extcon_info,
wq_detcable);
/* check ID and update cable state */
ret = irq_get_irqchip_state(info->irq, IRQCHIP_STATE_LINE_LEVEL, &id);
if (ret)
return;
if (info->id_irq > 0) {
/* check ID and update cable state */
ret = irq_get_irqchip_state(info->id_irq,
IRQCHIP_STATE_LINE_LEVEL, &state);
if (ret)
return;
if (!state) {
val.intval = true;
extcon_set_property(info->edev, EXTCON_USB_HOST,
EXTCON_PROP_USB_SS, val);
}
extcon_set_state_sync(info->edev, EXTCON_USB_HOST, !state);
}
extcon_set_state_sync(info->edev, EXTCON_USB_HOST, !id);
if (info->vbus_irq > 0) {
/* check VBUS and update cable state */
ret = irq_get_irqchip_state(info->vbus_irq,
IRQCHIP_STATE_LINE_LEVEL, &state);
if (ret)
return;
if (state) {
val.intval = true;
extcon_set_property(info->edev, EXTCON_USB,
EXTCON_PROP_USB_SS, val);
}
extcon_set_state_sync(info->edev, EXTCON_USB, state);
}
}
static irqreturn_t qcom_usb_irq_handler(int irq, void *dev_id)
......@@ -79,21 +105,48 @@ static int qcom_usb_extcon_probe(struct platform_device *pdev)
return ret;
}
ret = extcon_set_property_capability(info->edev,
EXTCON_USB, EXTCON_PROP_USB_SS);
ret |= extcon_set_property_capability(info->edev,
EXTCON_USB_HOST, EXTCON_PROP_USB_SS);
if (ret) {
dev_err(dev, "failed to register extcon props rc=%d\n",
ret);
return ret;
}
info->debounce_jiffies = msecs_to_jiffies(USB_ID_DEBOUNCE_MS);
INIT_DELAYED_WORK(&info->wq_detcable, qcom_usb_extcon_detect_cable);
info->irq = platform_get_irq_byname(pdev, "usb_id");
if (info->irq < 0)
return info->irq;
info->id_irq = platform_get_irq_byname(pdev, "usb_id");
if (info->id_irq > 0) {
ret = devm_request_threaded_irq(dev, info->id_irq, NULL,
qcom_usb_irq_handler,
IRQF_TRIGGER_RISING |
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
pdev->name, info);
if (ret < 0) {
dev_err(dev, "failed to request handler for ID IRQ\n");
return ret;
}
}
ret = devm_request_threaded_irq(dev, info->irq, NULL,
info->vbus_irq = platform_get_irq_byname(pdev, "usb_vbus");
if (info->vbus_irq > 0) {
ret = devm_request_threaded_irq(dev, info->vbus_irq, NULL,
qcom_usb_irq_handler,
IRQF_TRIGGER_RISING |
IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
pdev->name, info);
if (ret < 0) {
dev_err(dev, "failed to request handler for ID IRQ\n");
return ret;
if (ret < 0) {
dev_err(dev, "failed to request handler for VBUS IRQ\n");
return ret;
}
}
if (info->id_irq < 0 && info->vbus_irq < 0) {
dev_err(dev, "ID and VBUS IRQ not found\n");
return -EINVAL;
}
platform_set_drvdata(pdev, info);
......@@ -120,8 +173,12 @@ static int qcom_usb_extcon_suspend(struct device *dev)
struct qcom_usb_extcon_info *info = dev_get_drvdata(dev);
int ret = 0;
if (device_may_wakeup(dev))
ret = enable_irq_wake(info->irq);
if (device_may_wakeup(dev)) {
if (info->id_irq > 0)
ret = enable_irq_wake(info->id_irq);
if (info->vbus_irq > 0)
ret = enable_irq_wake(info->vbus_irq);
}
return ret;
}
......@@ -131,8 +188,12 @@ static int qcom_usb_extcon_resume(struct device *dev)
struct qcom_usb_extcon_info *info = dev_get_drvdata(dev);
int ret = 0;
if (device_may_wakeup(dev))
ret = disable_irq_wake(info->irq);
if (device_may_wakeup(dev)) {
if (info->id_irq > 0)
ret = disable_irq_wake(info->id_irq);
if (info->vbus_irq > 0)
ret = disable_irq_wake(info->vbus_irq);
}
return ret;
}
......
drivers/extcon/extcon-sm5502.c
View file @ 8e3a3249
......@@ -144,6 +144,7 @@ enum sm5502_muic_acc_type {
SM5502_MUIC_ADC_AUDIO_TYPE1_FULL_REMOTE = 0x3e, /* | 001|11110| */
SM5502_MUIC_ADC_AUDIO_TYPE1_SEND_END = 0x5e, /* | 010|11110| */
/* |Dev Type1|--ADC| */
SM5502_MUIC_ADC_GROUND_USB_OTG = 0x80, /* | 100|00000| */
SM5502_MUIC_ADC_OPEN_USB = 0x5f, /* | 010|11111| */
SM5502_MUIC_ADC_OPEN_TA = 0xdf, /* | 110|11111| */
SM5502_MUIC_ADC_OPEN_USB_OTG = 0xff, /* | 111|11111| */
......@@ -291,11 +292,27 @@ static unsigned int sm5502_muic_get_cable_type(struct sm5502_muic_info *info)
* connected with to MUIC device.
*/
cable_type = adc & SM5502_REG_ADC_MASK;
if (cable_type == SM5502_MUIC_ADC_GROUND)
return SM5502_MUIC_ADC_GROUND;
switch (cable_type) {
case SM5502_MUIC_ADC_GROUND:
ret = regmap_read(info->regmap, SM5502_REG_DEV_TYPE1,
&dev_type1);
if (ret) {
dev_err(info->dev, "failed to read DEV_TYPE1 reg\n");
return ret;
}
switch (dev_type1) {
case SM5502_REG_DEV_TYPE1_USB_OTG_MASK:
cable_type = SM5502_MUIC_ADC_GROUND_USB_OTG;
break;
default:
dev_dbg(info->dev,
"cannot identify the cable type: adc(0x%x), dev_type1(0x%x)\n",
adc, dev_type1);
return -EINVAL;
}
break;
case SM5502_MUIC_ADC_SEND_END_BUTTON:
case SM5502_MUIC_ADC_REMOTE_S1_BUTTON:
case SM5502_MUIC_ADC_REMOTE_S2_BUTTON:
......@@ -396,6 +413,7 @@ static int sm5502_muic_cable_handler(struct sm5502_muic_info *info,
con_sw = DM_DP_SWITCH_OPEN;
vbus_sw = VBUSIN_SWITCH_VBUSOUT;
break;
case SM5502_MUIC_ADC_GROUND_USB_OTG:
case SM5502_MUIC_ADC_OPEN_USB_OTG:
id = EXTCON_USB_HOST;
con_sw = DM_DP_SWITCH_USB;
......
drivers/firmware/Kconfig
View file @ 8e3a3249
......@@ -237,6 +237,7 @@ config INTEL_STRATIX10_RSU
config QCOM_SCM
bool
depends on ARM || ARM64
depends on HAVE_ARM_SMCCC
select RESET_CONTROLLER
config QCOM_SCM_DOWNLOAD_MODE_DEFAULT
......
drivers/firmware/google/gsmi.c
View file @ 8e3a3249
......@@ -136,12 +136,16 @@ MODULE_PARM_DESC(spincount,
"The number of loop iterations to use when using the spin handshake.");
/*
* Platforms might not support S0ix logging in their GSMI handlers. In order to
* avoid any side-effects of generating an SMI for S0ix logging, use the S0ix
* related GSMI commands only for those platforms that explicitly enable this
* option.
* Some older platforms with Apollo Lake chipsets do not support S0ix logging
* in their GSMI handlers, and behaved poorly when resuming via power button
* press if the logging was attempted. Updated firmware with proper behavior
* has long since shipped, removing the need for this opt-in parameter. It
* now exists as an opt-out parameter for folks defiantly running old
* firmware, or unforeseen circumstances. After the change from opt-in to
* opt-out has baked sufficiently, this parameter should probably be removed
* entirely.
*/
static bool s0ix_logging_enable;
static bool s0ix_logging_enable = true;
module_param(s0ix_logging_enable, bool, 0600);
static struct gsmi_buf *gsmi_buf_alloc(void)
......
drivers/fpga/Kconfig
View file @ 8e3a3249
......@@ -118,10 +118,17 @@ config XILINX_PR_DECOUPLER
depends on FPGA_BRIDGE
depends on HAS_IOMEM
help
Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
Say Y to enable drivers for Xilinx LogiCORE PR Decoupler
or Xilinx Dynamic Function eXchnage AIX Shutdown Manager.
The PR Decoupler exists in the FPGA fabric to isolate one
region of the FPGA from the busses while that region is
being reprogrammed during partial reconfig.
The Dynamic Function eXchange AXI shutdown manager prevents
AXI traffic from passing through the bridge. The controller
safely handles AXI4MM and AXI4-Lite interfaces on a
Reconfigurable Partition when it is undergoing dynamic
reconfiguration, preventing the system deadlock that can
occur if AXI transactions are interrupted by DFX.
config FPGA_REGION
tristate "FPGA Region"
......
drivers/fpga/dfl-afu-error.c
View file @ 8e3a3249
......@@ -52,7 +52,7 @@ static int afu_port_err_clear(struct device *dev, u64 err)
struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
struct platform_device *pdev = to_platform_device(dev);
void __iomem *base_err, *base_hdr;
int ret = -EBUSY;
int enable_ret = 0, ret = -EBUSY;
u64 v;
base_err = dfl_get_feature_ioaddr_by_id(dev, PORT_FEATURE_ID_ERROR);
......@@ -96,18 +96,20 @@ static int afu_port_err_clear(struct device *dev, u64 err)
v = readq(base_err + PORT_FIRST_ERROR);
writeq(v, base_err + PORT_FIRST_ERROR);
} else {
dev_warn(dev, "%s: received 0x%llx, expected 0x%llx\n",
__func__, v, err);
ret = -EINVAL;
}
/* Clear mask */
__afu_port_err_mask(dev, false);
/* Enable the Port by clear the reset */
__afu_port_enable(pdev);
/* Enable the Port by clearing the reset */
enable_ret = __afu_port_enable(pdev);
done:
mutex_unlock(&pdata->lock);
return ret;
return enable_ret ? enable_ret : ret;
}
static ssize_t errors_show(struct device *dev, struct device_attribute *attr,
......
drivers/fpga/dfl-afu-main.c
View file @ 8e3a3249
......@@ -21,6 +21,9 @@
#include "dfl-afu.h"
#define RST_POLL_INVL 10 /* us */
#define RST_POLL_TIMEOUT 1000 /* us */
/**
* __afu_port_enable - enable a port by clear reset
* @pdev: port platform device.
......@@ -32,7 +35,7 @@
*
* The caller needs to hold lock for protection.
*/
void __afu_port_enable(struct platform_device *pdev)
int __afu_port_enable(struct platform_device *pdev)
{
struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
void __iomem *base;
......@@ -41,7 +44,7 @@ void __afu_port_enable(struct platform_device *pdev)
WARN_ON(!pdata->disable_count);
if (--pdata->disable_count != 0)
return;
return 0;
base = dfl_get_feature_ioaddr_by_id(&pdev->dev, PORT_FEATURE_ID_HEADER);
......@@ -49,10 +52,20 @@ void __afu_port_enable(struct platform_device *pdev)
v = readq(base + PORT_HDR_CTRL);
v &= ~PORT_CTRL_SFTRST;
writeq(v, base + PORT_HDR_CTRL);
}
#define RST_POLL_INVL 10 /* us */
#define RST_POLL_TIMEOUT 1000 /* us */
/*
* HW clears the ack bit to indicate that the port is fully out
* of reset.
*/
if (readq_poll_timeout(base + PORT_HDR_CTRL, v,
!(v & PORT_CTRL_SFTRST_ACK),
RST_POLL_INVL, RST_POLL_TIMEOUT)) {
dev_err(&pdev->dev, "timeout, failure to enable device\n");
return -ETIMEDOUT;
}
return 0;
}
/**
* __afu_port_disable - disable a port by hold reset
......@@ -86,7 +99,7 @@ int __afu_port_disable(struct platform_device *pdev)
if (readq_poll_timeout(base + PORT_HDR_CTRL, v,
v & PORT_CTRL_SFTRST_ACK,
RST_POLL_INVL, RST_POLL_TIMEOUT)) {
dev_err(&pdev->dev, "timeout, fail to reset device\n");
dev_err(&pdev->dev, "timeout, failure to disable device\n");
return -ETIMEDOUT;
}
......@@ -110,10 +123,10 @@ static int __port_reset(struct platform_device *pdev)
int ret;
ret = __afu_port_disable(pdev);
if (!ret)
__afu_port_enable(pdev);
if (ret)
return ret;
return ret;
return __afu_port_enable(pdev);
}
static int port_reset(struct platform_device *pdev)
......@@ -872,11 +885,11 @@ static int afu_dev_destroy(struct platform_device *pdev)
static int port_enable_set(struct platform_device *pdev, bool enable)
{
struct dfl_feature_platform_data *pdata = dev_get_platdata(&pdev->dev);
int ret = 0;
int ret;
mutex_lock(&pdata->lock);
if (enable)
__afu_port_enable(pdev);
ret = __afu_port_enable(pdev);
else
ret = __afu_port_disable(pdev);
mutex_unlock(&pdata->lock);
......
drivers/fpga/dfl-afu.h
View file @ 8e3a3249
......@@ -80,7 +80,7 @@ struct dfl_afu {
};
/* hold pdata->lock when call __afu_port_enable/disable */
void __afu_port_enable(struct platform_device *pdev);
int __afu_port_enable(struct platform_device *pdev);
int __afu_port_disable(struct platform_device *pdev);
void afu_mmio_region_init(struct dfl_feature_platform_data *pdata);
......
drivers/fpga/dfl-pci.c
View file @ 8e3a3249
......@@ -69,14 +69,16 @@ static void cci_pci_free_irq(struct pci_dev *pcidev)
}
/* PCI Device ID */
#define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
#define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
#define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
#define PCIE_DEVICE_ID_INTEL_PAC_N3000 0x0B30
#define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
#define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
#define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
#define PCIE_DEVICE_ID_INTEL_PAC_N3000 0x0B30
#define PCIE_DEVICE_ID_INTEL_PAC_D5005 0x0B2B
/* VF Device */
#define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
#define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
#define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
#define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
#define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
#define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
#define PCIE_DEVICE_ID_INTEL_PAC_D5005_VF 0x0B2C
static struct pci_device_id cci_pcie_id_tbl[] = {
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),},
......@@ -86,6 +88,8 @@ static struct pci_device_id cci_pcie_id_tbl[] = {
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_N3000),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005),},
{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005_VF),},
{0,}
};
MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
......
drivers/fpga/xilinx-pr-decoupler.c
View file @ 8e3a3249
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2017, National Instruments Corp.
* Copyright (c) 2017, Xilix Inc
* Copyright (c) 2017, Xilinx Inc
*
* FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration
* Decoupler IP Core.
......@@ -18,7 +18,12 @@
#define CTRL_CMD_COUPLE 0
#define CTRL_OFFSET 0
struct xlnx_config_data {
const char *name;
};
struct xlnx_pr_decoupler_data {
const struct xlnx_config_data *ipconfig;
void __iomem *io_base;
struct clk *clk;
};
......@@ -76,15 +81,28 @@ static const struct fpga_bridge_ops xlnx_pr_decoupler_br_ops = {
.enable_show = xlnx_pr_decoupler_enable_show,
};
static const struct xlnx_config_data decoupler_config = {
.name = "Xilinx PR Decoupler",
};
static const struct xlnx_config_data shutdown_config = {
.name = "Xilinx DFX AXI Shutdown Manager",
};
static const struct of_device_id xlnx_pr_decoupler_of_match[] = {
{ .compatible = "xlnx,pr-decoupler-1.00", },
{ .compatible = "xlnx,pr-decoupler", },
{ .compatible = "xlnx,pr-decoupler-1.00", .data = &decoupler_config },
{ .compatible = "xlnx,pr-decoupler", .data = &decoupler_config },
{ .compatible = "xlnx,dfx-axi-shutdown-manager-1.00",
.data = &shutdown_config },
{ .compatible = "xlnx,dfx-axi-shutdown-manager",
.data = &shutdown_config },
{},
};
MODULE_DEVICE_TABLE(of, xlnx_pr_decoupler_of_match);
static int xlnx_pr_decoupler_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct xlnx_pr_decoupler_data *priv;
struct fpga_bridge *br;
int err;
......@@ -94,17 +112,23 @@ static int xlnx_pr_decoupler_probe(struct platform_device *pdev)
if (!priv)
return -ENOMEM;
if (np) {
const struct of_device_id *match;
match = of_match_node(xlnx_pr_decoupler_of_match, np);
if (match && match->data)
priv->ipconfig = match->data;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
priv->io_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(priv->io_base))
return PTR_ERR(priv->io_base);
priv->clk = devm_clk_get(&pdev->dev, "aclk");
if (IS_ERR(priv->clk)) {
if (PTR_ERR(priv->clk) != -EPROBE_DEFER)
dev_err(&pdev->dev, "input clock not found\n");
return PTR_ERR(priv->clk);
}
if (IS_ERR(priv->clk))
return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk),
"input clock not found\n");
err = clk_prepare_enable(priv->clk);
if (err) {
......@@ -114,7 +138,7 @@ static int xlnx_pr_decoupler_probe(struct platform_device *pdev)
clk_disable(priv->clk);
br = devm_fpga_bridge_create(&pdev->dev, "Xilinx PR Decoupler",
br = devm_fpga_bridge_create(&pdev->dev, priv->ipconfig->name,
&xlnx_pr_decoupler_br_ops, priv);
if (!br) {
err = -ENOMEM;
......@@ -125,7 +149,8 @@ static int xlnx_pr_decoupler_probe(struct platform_device *pdev)
err = fpga_bridge_register(br);
if (err) {
dev_err(&pdev->dev, "unable to register Xilinx PR Decoupler");
dev_err(&pdev->dev, "unable to register %s",
priv->ipconfig->name);
goto err_clk;
}
......
drivers/fpga/xilinx-spi.c
View file @ 8e3a3249
......@@ -233,25 +233,19 @@ static int xilinx_spi_probe(struct spi_device *spi)
/* PROGRAM_B is active low */
conf->prog_b = devm_gpiod_get(&spi->dev, "prog_b", GPIOD_OUT_LOW);
if (IS_ERR(conf->prog_b)) {
dev_err(&spi->dev, "Failed to get PROGRAM_B gpio: %ld\n",
PTR_ERR(conf->prog_b));
return PTR_ERR(conf->prog_b);
}
if (IS_ERR(conf->prog_b))
return dev_err_probe(&spi->dev, PTR_ERR(conf->prog_b),
"Failed to get PROGRAM_B gpio\n");
conf->init_b = devm_gpiod_get_optional(&spi->dev, "init-b", GPIOD_IN);
if (IS_ERR(conf->init_b)) {
dev_err(&spi->dev, "Failed to get INIT_B gpio: %ld\n",
PTR_ERR(conf->init_b));
return PTR_ERR(conf->init_b);
}
if (IS_ERR(conf->init_b))
return dev_err_probe(&spi->dev, PTR_ERR(conf->init_b),
"Failed to get INIT_B gpio\n");
conf->done = devm_gpiod_get(&spi->dev, "done", GPIOD_IN);
if (IS_ERR(conf->done)) {
dev_err(&spi->dev, "Failed to get DONE gpio: %ld\n",
PTR_ERR(conf->done));
return PTR_ERR(conf->done);
}
if (IS_ERR(conf->done))
return dev_err_probe(&spi->dev, PTR_ERR(conf->done),
"Failed to get DONE gpio\n");
mgr = devm_fpga_mgr_create(&spi->dev,
"Xilinx Slave Serial FPGA Manager",
......
drivers/greybus/es2.c
View file @ 8e3a3249
......@@ -72,11 +72,11 @@ struct es2_cport_in {
};
/**
* es2_ap_dev - ES2 USB Bridge to AP structure
* struct es2_ap_dev - ES2 USB Bridge to AP structure
* @usb_dev: pointer to the USB device we are.
* @usb_intf: pointer to the USB interface we are bound to.
* @hd: pointer to our gb_host_device structure
*
* @cport_in: endpoint, urbs and buffer for cport in messages
* @cport_out_endpoint: endpoint for for cport out messages
* @cport_out_urb: array of urbs for the CPort out messages
......@@ -85,7 +85,7 @@ struct es2_cport_in {
* @cport_out_urb_cancelled: array of flags indicating whether the
* corresponding @cport_out_urb is being cancelled
* @cport_out_urb_lock: locks the @cport_out_urb_busy "list"
*
* @cdsi1_in_use: true if cport CDSI1 is in use
* @apb_log_task: task pointer for logging thread
* @apb_log_dentry: file system entry for the log file interface
* @apb_log_enable_dentry: file system entry for enabling logging
......@@ -1171,7 +1171,7 @@ static ssize_t apb_log_enable_read(struct file *f, char __user *buf,
char tmp_buf[3];
sprintf(tmp_buf, "%d\n", enable);
return simple_read_from_buffer(buf, count, ppos, tmp_buf, 3);
return simple_read_from_buffer(buf, count, ppos, tmp_buf, 2);
}
static ssize_t apb_log_enable_write(struct file *f, const char __user *buf,
......
drivers/hwtracing/coresight/coresight-core.c
View file @ 8e3a3249
......@@ -86,7 +86,7 @@ static int coresight_id_match(struct device *dev, void *data)
i_csdev->type != CORESIGHT_DEV_TYPE_SOURCE)
return 0;
/* Get the source ID for both compoment */
/* Get the source ID for both components */
trace_id = source_ops(csdev)->trace_id(csdev);
i_trace_id = source_ops(i_csdev)->trace_id(i_csdev);
......
drivers/hwtracing/coresight/coresight-etm-perf.c
View file @ 8e3a3249
......@@ -52,13 +52,13 @@ static ssize_t format_attr_contextid_show(struct device *dev,
{
int pid_fmt = ETM_OPT_CTXTID;
#if defined(CONFIG_CORESIGHT_SOURCE_ETM4X)
#if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM4X)
pid_fmt = is_kernel_in_hyp_mode() ? ETM_OPT_CTXTID2 : ETM_OPT_CTXTID;
#endif
return sprintf(page, "config:%d\n", pid_fmt);
}
struct device_attribute format_attr_contextid =
static struct device_attribute format_attr_contextid =
__ATTR(contextid, 0444, format_attr_contextid_show, NULL);
static struct attribute *etm_config_formats_attr[] = {
......
drivers/hwtracing/coresight/coresight-etm4x-core.c
View file @ 8e3a3249
......@@ -1951,6 +1951,7 @@ static const struct amba_id etm4_ids[] = {
CS_AMBA_UCI_ID(0x000bbd05, uci_id_etm4),/* Cortex-A55 */
CS_AMBA_UCI_ID(0x000bbd0a, uci_id_etm4),/* Cortex-A75 */
CS_AMBA_UCI_ID(0x000bbd0c, uci_id_etm4),/* Neoverse N1 */
CS_AMBA_UCI_ID(0x000bbd41, uci_id_etm4),/* Cortex-A78 */
CS_AMBA_UCI_ID(0x000f0205, uci_id_etm4),/* Qualcomm Kryo */
CS_AMBA_UCI_ID(0x000f0211, uci_id_etm4),/* Qualcomm Kryo */
CS_AMBA_UCI_ID(0x000bb802, uci_id_etm4),/* Qualcomm Kryo 385 Cortex-A55 */
......
drivers/hwtracing/intel_th/core.c
View file @ 8e3a3249
......@@ -844,7 +844,7 @@ static irqreturn_t intel_th_irq(int irq, void *data)
* @irq: irq number
*/
struct intel_th *
intel_th_alloc(struct device *dev, struct intel_th_drvdata *drvdata,
intel_th_alloc(struct device *dev, const struct intel_th_drvdata *drvdata,
struct resource *devres, unsigned int ndevres)
{
int err, r, nr_mmios = 0;
......
drivers/hwtracing/intel_th/gth.c
View file @ 8e3a3249
......@@ -543,7 +543,7 @@ static void intel_th_gth_disable(struct intel_th_device *thdev,
output->active = false;
for_each_set_bit(master, gth->output[output->port].master,
TH_CONFIGURABLE_MASTERS) {
TH_CONFIGURABLE_MASTERS + 1) {
gth_master_set(gth, master, -1);
}
spin_unlock(&gth->gth_lock);
......@@ -697,7 +697,7 @@ static void intel_th_gth_unassign(struct intel_th_device *thdev,
othdev->output.port = -1;
othdev->output.active = false;
gth->output[port].output = NULL;
for (master = 0; master <= TH_CONFIGURABLE_MASTERS; master++)
for (master = 0; master < TH_CONFIGURABLE_MASTERS + 1; master++)
if (gth->master[master] == port)
gth->master[master] = -1;
spin_unlock(&gth->gth_lock);
......
drivers/hwtracing/intel_th/intel_th.h
View file @ 8e3a3249
......@@ -74,7 +74,7 @@ struct intel_th_drvdata {
*/
struct intel_th_device {
struct device dev;
struct intel_th_drvdata *drvdata;
const struct intel_th_drvdata *drvdata;
struct resource *resource;
unsigned int num_resources;
unsigned int type;
......@@ -178,7 +178,7 @@ struct intel_th_driver {
/* file_operations for those who want a device node */
const struct file_operations *fops;
/* optional attributes */
struct attribute_group *attr_group;
const struct attribute_group *attr_group;
/* source ops */
int (*set_output)(struct intel_th_device *thdev,
......@@ -224,7 +224,7 @@ static inline struct intel_th *to_intel_th(struct intel_th_device *thdev)
}
struct intel_th *
intel_th_alloc(struct device *dev, struct intel_th_drvdata *drvdata,
intel_th_alloc(struct device *dev, const struct intel_th_drvdata *drvdata,
struct resource *devres, unsigned int ndevres);
void intel_th_free(struct intel_th *th);
......@@ -272,7 +272,7 @@ struct intel_th {
struct intel_th_device *thdev[TH_SUBDEVICE_MAX];
struct intel_th_device *hub;
struct intel_th_drvdata *drvdata;
const struct intel_th_drvdata *drvdata;
struct resource resource[TH_MMIO_END];
int (*activate)(struct intel_th *);
......
drivers/hwtracing/intel_th/msu.c
View file @ 8e3a3249
......@@ -2095,7 +2095,7 @@ static struct attribute *msc_output_attrs[] = {
NULL,
};
static struct attribute_group msc_output_group = {
static const struct attribute_group msc_output_group = {
.attrs = msc_output_attrs,
};
......
drivers/hwtracing/intel_th/pci.c
View file @ 8e3a3249
......@@ -71,7 +71,7 @@ static void intel_th_pci_deactivate(struct intel_th *th)
static int intel_th_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
struct intel_th_drvdata *drvdata = (void *)id->driver_data;
const struct intel_th_drvdata *drvdata = (void *)id->driver_data;
struct resource resource[TH_MMIO_END + TH_NVEC_MAX] = {
[TH_MMIO_CONFIG] = pdev->resource[TH_PCI_CONFIG_BAR],
[TH_MMIO_SW] = pdev->resource[TH_PCI_STH_SW_BAR],
......@@ -273,11 +273,21 @@ static const struct pci_device_id intel_th_pci_id_table[] = {
PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x51a6),
.driver_data = (kernel_ulong_t)&intel_th_2x,
},
{
/* Alder Lake-M */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x54a6),
.driver_data = (kernel_ulong_t)&intel_th_2x,
},
{
/* Alder Lake CPU */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x466f),
.driver_data = (kernel_ulong_t)&intel_th_2x,
},
{
/* Rocket Lake CPU */
PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4c19),
.driver_data = (kernel_ulong_t)&intel_th_2x,
},
{ 0 },
};
......
drivers/hwtracing/intel_th/pti.c
View file @ 8e3a3249
......@@ -142,7 +142,7 @@ static struct attribute *pti_output_attrs[] = {
NULL,
};
static struct attribute_group pti_output_group = {
static const struct attribute_group pti_output_group = {
.attrs = pti_output_attrs,
};
......@@ -295,7 +295,7 @@ static struct attribute *lpp_output_attrs[] = {
NULL,
};
static struct attribute_group lpp_output_group = {
static const struct attribute_group lpp_output_group = {
.attrs = lpp_output_attrs,
};
......
drivers/hwtracing/stm/p_sys-t.c
View file @ 8e3a3249
......@@ -92,7 +92,7 @@ static void sys_t_policy_node_init(void *priv)
{
struct sys_t_policy_node *pn = priv;
generate_random_uuid(pn->uuid.b);
uuid_gen(&pn->uuid);
}
static int sys_t_output_open(void *priv, struct stm_output *output)
......@@ -292,6 +292,7 @@ static ssize_t sys_t_write(struct stm_data *data, struct stm_output *output,
unsigned int m = output->master;
const unsigned char nil = 0;
u32 header = DATA_HEADER;
u8 uuid[UUID_SIZE];
ssize_t sz;
/* We require an existing policy node to proceed */
......@@ -322,7 +323,8 @@ static ssize_t sys_t_write(struct stm_data *data, struct stm_output *output,
return sz;
/* GUID */
sz = stm_data_write(data, m, c, false, op->node.uuid.b, UUID_SIZE);
export_uuid(uuid, &op->node.uuid);
sz = stm_data_write(data, m, c, false, uuid, sizeof(op->node.uuid));
if (sz <= 0)
return sz;
......
drivers/hwtracing/stm/policy.c
View file @ 8e3a3249
......@@ -57,11 +57,6 @@ void stp_policy_node_get_ranges(struct stp_policy_node *policy_node,
*cend = policy_node->last_channel;
}
static inline char *stp_policy_node_name(struct stp_policy_node *policy_node)
{
return policy_node->group.cg_item.ci_name ? : "<none>";
}
static inline struct stp_policy *to_stp_policy(struct config_item *item)
{
return item ?
......
drivers/interconnect/qcom/Kconfig
View file @ 8e3a3249
......@@ -74,6 +74,15 @@ config INTERCONNECT_QCOM_SC7180
This is a driver for the Qualcomm Network-on-Chip on sc7180-based
platforms.
config INTERCONNECT_QCOM_SDM660
tristate "Qualcomm SDM660 interconnect driver"
depends on INTERCONNECT_QCOM
depends on QCOM_SMD_RPM
select INTERCONNECT_QCOM_SMD_RPM
help
This is a driver for the Qualcomm Network-on-Chip on sdm660-based
platforms.
config INTERCONNECT_QCOM_SDM845
tristate "Qualcomm SDM845 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
......@@ -110,5 +119,14 @@ config INTERCONNECT_QCOM_SM8250
This is a driver for the Qualcomm Network-on-Chip on sm8250-based
platforms.
config INTERCONNECT_QCOM_SM8350
tristate "Qualcomm SM8350 interconnect driver"
depends on INTERCONNECT_QCOM_RPMH_POSSIBLE
select INTERCONNECT_QCOM_RPMH
select INTERCONNECT_QCOM_BCM_VOTER
help
This is a driver for the Qualcomm Network-on-Chip on SM8350-based
platforms.
config INTERCONNECT_QCOM_SMD_RPM
tristate
drivers/interconnect/qcom/Makefile
View file @ 8e3a3249
......@@ -8,10 +8,12 @@ icc-osm-l3-objs := osm-l3.o
qnoc-qcs404-objs := qcs404.o
icc-rpmh-obj := icc-rpmh.o
qnoc-sc7180-objs := sc7180.o
qnoc-sdm660-objs := sdm660.o
qnoc-sdm845-objs := sdm845.o
qnoc-sdx55-objs := sdx55.o
qnoc-sm8150-objs := sm8150.o
qnoc-sm8250-objs := sm8250.o
qnoc-sm8350-objs := sm8350.o
icc-smd-rpm-objs := smd-rpm.o icc-rpm.o
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
......@@ -22,8 +24,10 @@ obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDM660) += qnoc-sdm660.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDX55) += qnoc-sdx55.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o
obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o
obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o
drivers/interconnect/qcom/icc-rpm.c
View file @ 8e3a3249
......@@ -59,8 +59,8 @@ static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
qn->slv_rpm_id,
sum_bw);
if (ret) {
pr_err("qcom_icc_rpm_smd_send slv error %d\n",
ret);
pr_err("qcom_icc_rpm_smd_send slv %d error %d\n",
qn->slv_rpm_id, ret);
return ret;
}
}
......
drivers/interconnect/qcom/sdm660.c 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
drivers/interconnect/qcom/sm8350.c 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
drivers/interconnect/qcom/sm8350.h 0 → 100644
View file @ 8e3a3249
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Qualcomm SM8350 interconnect IDs
*
* Copyright (c) 2021, Linaro Limited
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_SM8350_H
#define __DRIVERS_INTERCONNECT_QCOM_SM8350_H
#define SM8350_MASTER_GPU_TCU 0
#define SM8350_MASTER_SYS_TCU 1
#define SM8350_MASTER_APPSS_PROC 2
#define SM8350_MASTER_LLCC 3
#define SM8350_MASTER_CNOC_LPASS_AG_NOC 4
#define SM8350_MASTER_CDSP_NOC_CFG 5
#define SM8350_MASTER_QDSS_BAM 6
#define SM8350_MASTER_QSPI_0 7
#define SM8350_MASTER_QUP_0 8
#define SM8350_MASTER_QUP_1 9
#define SM8350_MASTER_QUP_2 10
#define SM8350_MASTER_A1NOC_CFG 11
#define SM8350_MASTER_A2NOC_CFG 12
#define SM8350_MASTER_A1NOC_SNOC 13
#define SM8350_MASTER_A2NOC_SNOC 14
#define SM8350_MASTER_CAMNOC_HF 15
#define SM8350_MASTER_CAMNOC_ICP 16
#define SM8350_MASTER_CAMNOC_SF 17
#define SM8350_MASTER_COMPUTE_NOC 18
#define SM8350_MASTER_CNOC_DC_NOC 19
#define SM8350_MASTER_GEM_NOC_CFG 20
#define SM8350_MASTER_GEM_NOC_CNOC 21
#define SM8350_MASTER_GEM_NOC_PCIE_SNOC 22
#define SM8350_MASTER_GFX3D 23
#define SM8350_MASTER_CNOC_MNOC_CFG 24
#define SM8350_MASTER_MNOC_HF_MEM_NOC 25
#define SM8350_MASTER_MNOC_SF_MEM_NOC 26
#define SM8350_MASTER_ANOC_PCIE_GEM_NOC 27
#define SM8350_MASTER_SNOC_CFG 28
#define SM8350_MASTER_SNOC_GC_MEM_NOC 29
#define SM8350_MASTER_SNOC_SF_MEM_NOC 30
#define SM8350_MASTER_VIDEO_P0 31
#define SM8350_MASTER_VIDEO_P1 32
#define SM8350_MASTER_VIDEO_PROC 33
#define SM8350_MASTER_QUP_CORE_0 34
#define SM8350_MASTER_QUP_CORE_1 35
#define SM8350_MASTER_QUP_CORE_2 36
#define SM8350_MASTER_CRYPTO 37
#define SM8350_MASTER_IPA 38
#define SM8350_MASTER_MDP0 39
#define SM8350_MASTER_MDP1 40
#define SM8350_MASTER_CDSP_PROC 41
#define SM8350_MASTER_PIMEM 42
#define SM8350_MASTER_ROTATOR 43
#define SM8350_MASTER_GIC 44
#define SM8350_MASTER_PCIE_0 45
#define SM8350_MASTER_PCIE_1 46
#define SM8350_MASTER_QDSS_DAP 47
#define SM8350_MASTER_QDSS_ETR 48
#define SM8350_MASTER_SDCC_2 49
#define SM8350_MASTER_SDCC_4 50
#define SM8350_MASTER_UFS_CARD 51
#define SM8350_MASTER_UFS_MEM 52
#define SM8350_MASTER_USB3_0 53
#define SM8350_MASTER_USB3_1 54
#define SM8350_SLAVE_EBI1 55
#define SM8350_SLAVE_AHB2PHY_SOUTH 56
#define SM8350_SLAVE_AHB2PHY_NORTH 57
#define SM8350_SLAVE_AOSS 58
#define SM8350_SLAVE_APPSS 59
#define SM8350_SLAVE_CAMERA_CFG 60
#define SM8350_SLAVE_CLK_CTL 61
#define SM8350_SLAVE_CDSP_CFG 62
#define SM8350_SLAVE_RBCPR_CX_CFG 63
#define SM8350_SLAVE_RBCPR_MMCX_CFG 64
#define SM8350_SLAVE_RBCPR_MX_CFG 65
#define SM8350_SLAVE_CRYPTO_0_CFG 66
#define SM8350_SLAVE_CX_RDPM 67
#define SM8350_SLAVE_DCC_CFG 68
#define SM8350_SLAVE_DISPLAY_CFG 69
#define SM8350_SLAVE_GFX3D_CFG 70
#define SM8350_SLAVE_HWKM 71
#define SM8350_SLAVE_IMEM_CFG 72
#define SM8350_SLAVE_IPA_CFG 73
#define SM8350_SLAVE_IPC_ROUTER_CFG 74
#define SM8350_SLAVE_LLCC_CFG 75
#define SM8350_SLAVE_LPASS 76
#define SM8350_SLAVE_LPASS_CORE_CFG 77
#define SM8350_SLAVE_LPASS_LPI_CFG 78
#define SM8350_SLAVE_LPASS_MPU_CFG 79
#define SM8350_SLAVE_LPASS_TOP_CFG 80
#define SM8350_SLAVE_MSS_PROC_MS_MPU_CFG 81
#define SM8350_SLAVE_MCDMA_MS_MPU_CFG 82
#define SM8350_SLAVE_CNOC_MSS 83
#define SM8350_SLAVE_MX_RDPM 84
#define SM8350_SLAVE_PCIE_0_CFG 85
#define SM8350_SLAVE_PCIE_1_CFG 86
#define SM8350_SLAVE_PDM 87
#define SM8350_SLAVE_PIMEM_CFG 88
#define SM8350_SLAVE_PKA_WRAPPER_CFG 89
#define SM8350_SLAVE_PMU_WRAPPER_CFG 90
#define SM8350_SLAVE_QDSS_CFG 91
#define SM8350_SLAVE_QSPI_0 92
#define SM8350_SLAVE_QUP_0 93
#define SM8350_SLAVE_QUP_1 94
#define SM8350_SLAVE_QUP_2 95
#define SM8350_SLAVE_SDCC_2 96
#define SM8350_SLAVE_SDCC_4 97
#define SM8350_SLAVE_SECURITY 98
#define SM8350_SLAVE_SPSS_CFG 99
#define SM8350_SLAVE_TCSR 100
#define SM8350_SLAVE_TLMM 101
#define SM8350_SLAVE_UFS_CARD_CFG 102
#define SM8350_SLAVE_UFS_MEM_CFG 103
#define SM8350_SLAVE_USB3_0 104
#define SM8350_SLAVE_USB3_1 105
#define SM8350_SLAVE_VENUS_CFG 106
#define SM8350_SLAVE_VSENSE_CTRL_CFG 107
#define SM8350_SLAVE_A1NOC_CFG 108
#define SM8350_SLAVE_A1NOC_SNOC 109
#define SM8350_SLAVE_A2NOC_CFG 110
#define SM8350_SLAVE_A2NOC_SNOC 111
#define SM8350_SLAVE_DDRSS_CFG 112
#define SM8350_SLAVE_GEM_NOC_CNOC 113
#define SM8350_SLAVE_GEM_NOC_CFG 114
#define SM8350_SLAVE_SNOC_GEM_NOC_GC 115
#define SM8350_SLAVE_SNOC_GEM_NOC_SF 116
#define SM8350_SLAVE_LLCC 117
#define SM8350_SLAVE_MNOC_HF_MEM_NOC 118
#define SM8350_SLAVE_MNOC_SF_MEM_NOC 119
#define SM8350_SLAVE_CNOC_MNOC_CFG 120
#define SM8350_SLAVE_CDSP_MEM_NOC 121
#define SM8350_SLAVE_MEM_NOC_PCIE_SNOC 122
#define SM8350_SLAVE_ANOC_PCIE_GEM_NOC 123
#define SM8350_SLAVE_SNOC_CFG 124
#define SM8350_SLAVE_QUP_CORE_0 125
#define SM8350_SLAVE_QUP_CORE_1 126
#define SM8350_SLAVE_QUP_CORE_2 127
#define SM8350_SLAVE_BOOT_IMEM 128
#define SM8350_SLAVE_IMEM 129
#define SM8350_SLAVE_PIMEM 130
#define SM8350_SLAVE_SERVICE_NSP_NOC 131
#define SM8350_SLAVE_SERVICE_A1NOC 132
#define SM8350_SLAVE_SERVICE_A2NOC 133
#define SM8350_SLAVE_SERVICE_CNOC 134
#define SM8350_SLAVE_SERVICE_GEM_NOC_1 135
#define SM8350_SLAVE_SERVICE_MNOC 136
#define SM8350_SLAVE_SERVICES_LPASS_AML_NOC 137
#define SM8350_SLAVE_SERVICE_LPASS_AG_NOC 138
#define SM8350_SLAVE_SERVICE_GEM_NOC_2 139
#define SM8350_SLAVE_SERVICE_SNOC 140
#define SM8350_SLAVE_SERVICE_GEM_NOC 141
#define SM8350_SLAVE_PCIE_0 142
#define SM8350_SLAVE_PCIE_1 143
#define SM8350_SLAVE_QDSS_STM 144
#define SM8350_SLAVE_TCU 145
#define SM8350_MASTER_LLCC_DISP 146
#define SM8350_MASTER_MNOC_HF_MEM_NOC_DISP 147
#define SM8350_MASTER_MNOC_SF_MEM_NOC_DISP 148
#define SM8350_MASTER_MDP0_DISP 149
#define SM8350_MASTER_MDP1_DISP 150
#define SM8350_MASTER_ROTATOR_DISP 151
#define SM8350_SLAVE_EBI1_DISP 152
#define SM8350_SLAVE_LLCC_DISP 153
#define SM8350_SLAVE_MNOC_HF_MEM_NOC_DISP 154
#define SM8350_SLAVE_MNOC_SF_MEM_NOC_DISP 155
#endif
drivers/misc/Kconfig
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/Makefile
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/ad525x_dpot.c
View file @ 8e3a3249
......@@ -139,6 +139,9 @@ static s32 dpot_read_spi(struct dpot_data *dpot, u8 reg)
value = dpot_read_r8d8(dpot,
DPOT_AD5291_READ_RDAC << 2);
if (value < 0)
return value;
if (dpot->uid == DPOT_UID(AD5291_ID))
value = value >> 2;
......
drivers/misc/cxl/context.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/cxl/fault.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/dw-xdata-pcie.c 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/genwqe/card_ddcb.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/habanalabs/common/context.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/habanalabs/common/debugfs.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/habanalabs/common/device.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/habanalabs/common/habanalabs.h
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/habanalabs/common/hw_queue.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/habanalabs/common/irq.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/habanalabs/common/memory.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/habanalabs/common/mmu/mmu.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/habanalabs/common/pci/pci.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/habanalabs/common/sysfs.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/habanalabs/gaudi/gaudi.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/habanalabs/gaudi/gaudiP.h
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/habanalabs/goya/goya.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/habanalabs/goya/goyaP.h
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/habanalabs/include/goya/goya.h
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/kgdbts.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/lis3lv02d/lis3lv02d.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/mei/hw-me-regs.h
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/mei/pci-me.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/pvpanic/Kconfig 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/pvpanic/Makefile 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/pvpanic/pvpanic-pci.c 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/pvpanic/pvpanic.c 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/pvpanic/pvpanic.h 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/sgi-xp/xp_main.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/sgi-xp/xpc_main.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/uacce/uacce.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/vmw_balloon.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/vmw_vmci/vmci_doorbell.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/vmw_vmci/vmci_guest.c
View file @ 8e3a3249
This diff is collapsed.
drivers/misc/vmw_vmci/vmci_host.c
View file @ 8e3a3249
This diff is collapsed.
drivers/most/most_cdev.c
View file @ 8e3a3249
This diff is collapsed.
drivers/mux/gpio.c
View file @ 8e3a3249
This diff is collapsed.
drivers/nvmem/Kconfig
View file @ 8e3a3249
This diff is collapsed.
drivers/nvmem/Makefile
View file @ 8e3a3249
This diff is collapsed.
drivers/nvmem/brcm_nvram.c 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
drivers/nvmem/core.c
View file @ 8e3a3249
This diff is collapsed.
drivers/nvmem/qcom-spmi-sdam.c
View file @ 8e3a3249
This diff is collapsed.
drivers/nvmem/qfprom.c
View file @ 8e3a3249
This diff is collapsed.
drivers/nvmem/snvs_lpgpr.c
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/Kconfig
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/Makefile
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/broadcom/Kconfig
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/cadence/Kconfig
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/cadence/phy-cadence-sierra.c
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/cadence/phy-cadence-torrent.c
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/hisilicon/phy-hi6220-usb.c
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/hisilicon/phy-hix5hd2-sata.c
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/ingenic/phy-ingenic-usb.c
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/intel/phy-intel-lgm-combo.c
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/marvell/Kconfig
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/marvell/Makefile
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/marvell/phy-mvebu-cp110-utmi.c 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/microchip/Kconfig 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/microchip/Makefile 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/microchip/sparx5_serdes.c 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/microchip/sparx5_serdes.h 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/microchip/sparx5_serdes_regs.h 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/phy-core.c
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/qualcomm/phy-qcom-ipq806x-usb.c
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/qualcomm/phy-qcom-qmp.c
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/qualcomm/phy-qcom-qmp.h
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/qualcomm/phy-qcom-usb-hs.c
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/ralink/phy-mt7621-pci.c
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/rockchip/phy-rockchip-typec.c
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/st/Kconfig
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/st/phy-stm32-usbphyc.c
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/ti/phy-j721e-wiz.c
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/ti/phy-tusb1210.c
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/ti/phy-twl4030-usb.c
View file @ 8e3a3249
This diff is collapsed.
drivers/phy/xilinx/phy-zynqmp.c
View file @ 8e3a3249
This diff is collapsed.
drivers/pps/clients/pps-gpio.c
View file @ 8e3a3249
This diff is collapsed.
drivers/soundwire/Makefile
View file @ 8e3a3249
This diff is collapsed.
drivers/soundwire/bus.c
View file @ 8e3a3249
This diff is collapsed.
drivers/soundwire/bus.h
View file @ 8e3a3249
This diff is collapsed.
drivers/soundwire/bus_type.c
View file @ 8e3a3249
This diff is collapsed.
drivers/soundwire/cadence_master.c
View file @ 8e3a3249
This diff is collapsed.
drivers/soundwire/dmi-quirks.c 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
drivers/soundwire/intel.c
View file @ 8e3a3249
This diff is collapsed.
drivers/soundwire/intel_init.c
View file @ 8e3a3249
This diff is collapsed.
drivers/soundwire/qcom.c
View file @ 8e3a3249
This diff is collapsed.
drivers/soundwire/slave.c
View file @ 8e3a3249
This diff is collapsed.
drivers/soundwire/stream.c
View file @ 8e3a3249
This diff is collapsed.
drivers/uio/Kconfig
View file @ 8e3a3249
This diff is collapsed.
drivers/uio/Makefile
View file @ 8e3a3249
This diff is collapsed.
drivers/uio/uio_dfl.c 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
drivers/video/fbdev/core/fbcmap.c
View file @ 8e3a3249
This diff is collapsed.
drivers/virt/acrn/vm.c
View file @ 8e3a3249
This diff is collapsed.
drivers/w1/slaves/w1_ds2780.c
View file @ 8e3a3249
This diff is collapsed.
drivers/w1/slaves/w1_ds2781.c
View file @ 8e3a3249
This diff is collapsed.
drivers/w1/slaves/w1_ds2805.c
View file @ 8e3a3249
This diff is collapsed.
drivers/w1/slaves/w1_ds28e17.c
View file @ 8e3a3249
This diff is collapsed.
drivers/w1/slaves/w1_therm.c
View file @ 8e3a3249
This diff is collapsed.
include/dt-bindings/interconnect/qcom,sdm660.h 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
include/dt-bindings/interconnect/qcom,sm8350.h 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
include/dt-bindings/mux/ti-serdes.h
View file @ 8e3a3249
This diff is collapsed.
include/dt-bindings/phy/phy-ti.h 0 → 100644
View file @ 8e3a3249
This diff is collapsed.
include/linux/mhi.h
View file @ 8e3a3249
This diff is collapsed.
include/linux/nvmem-consumer.h
View file @ 8e3a3249
This diff is collapsed.
include/linux/phy/phy.h
View file @ 8e3a3249
This diff is collapsed.
include/linux/pps-gpio.h deleted 100644 → 0
View file @ 90035c28
This diff is collapsed.
include/linux/soundwire/sdw.h
View file @ 8e3a3249
This diff is collapsed.
include/uapi/linux/android/binder.h
View file @ 8e3a3249
This diff is collapsed.
include/uapi/linux/map_to_7segment.h
View file @ 8e3a3249
This diff is collapsed.
include/uapi/misc/habanalabs.h
View file @ 8e3a3249
This diff is collapsed.
net/bluetooth/hci_request.c
View file @ 8e3a3249
This diff is collapsed.
scripts/spdxcheck.py
View file @ 8e3a3249
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7