Commit 8eb37aff authored by Andrew Jeffery's avatar Andrew Jeffery Committed by Linus Walleij

pinctrl: aspeed-g5: Fix pin association of SPI1 function

The SPI1 function was associated with the wrong pins: The functions that
those pins provide is either an SPI debug or passthrough function
coupled to SPI1. Make the SPI1 mux function configure the relevant pins
and associate new SPI1DEBUG and SPI1PASSTHRU functions with the pins
that were already defined.

The notation used in the datasheet's multi-function pin table for the SoC is
often creative: in this case the SYS* signals are enabled by a single bit,
which is nothing unusual on its own, but in this case the bit was also
participating in a multi-bit bitfield and therefore represented multiple
functions. This fact was overlooked in the original patch.

Fixes: 56e57cb6 (pinctrl: Add pinctrl-aspeed-g5 driver)
Signed-off-by: default avatarAndrew Jeffery <andrew@aj.id.au>
Reviewed-by: default avatarJoel Stanley <joel@jms.id.au>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent d3dbabe9
...@@ -43,7 +43,9 @@ aspeed,ast2500-pinctrl, aspeed,g5-pinctrl: ...@@ -43,7 +43,9 @@ aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8 GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8
I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 SPI1DEBUG SPI1PASSTHRU TIMER4 TIMER5 TIMER6
TIMER7 TIMER8 VGABIOSROM
Examples: Examples:
......
...@@ -186,24 +186,84 @@ MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT); ...@@ -186,24 +186,84 @@ MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT);
FUNC_GROUP_DECL(GPIE0, B20, C20); FUNC_GROUP_DECL(GPIE0, B20, C20);
#define SPI1_DESC SIG_DESC_SET(HW_STRAP1, 13) #define SPI1_DESC { HW_STRAP1, GENMASK(13, 12), 1, 0 }
#define SPI1DEBUG_DESC { HW_STRAP1, GENMASK(13, 12), 2, 0 }
#define SPI1PASSTHRU_DESC { HW_STRAP1, GENMASK(13, 12), 3, 0 }
#define C18 64 #define C18 64
SIG_EXPR_LIST_DECL_SINGLE(SYSCS, SPI1, COND1, SPI1_DESC); SIG_EXPR_DECL(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU);
SS_PIN_DECL(C18, GPIOI0, SYSCS); SS_PIN_DECL(C18, GPIOI0, SYSCS);
#define E15 65 #define E15 65
SIG_EXPR_LIST_DECL_SINGLE(SYSCK, SPI1, COND1, SPI1_DESC); SIG_EXPR_DECL(SYSCK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU);
SS_PIN_DECL(E15, GPIOI1, SYSCK); SS_PIN_DECL(E15, GPIOI1, SYSCK);
#define A14 66 #define B16 66
SIG_EXPR_LIST_DECL_SINGLE(SYSMOSI, SPI1, COND1, SPI1_DESC); SIG_EXPR_DECL(SYSMOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SS_PIN_DECL(A14, GPIOI2, SYSMOSI); SIG_EXPR_DECL(SYSMOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL_DUAL(SYSMOSI, SPI1DEBUG, SPI1PASSTHRU);
SS_PIN_DECL(B16, GPIOI2, SYSMOSI);
#define C16 67 #define C16 67
SIG_EXPR_LIST_DECL_SINGLE(SYSMISO, SPI1, COND1, SPI1_DESC); SIG_EXPR_DECL(SYSMISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL(SYSMISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL_DUAL(SYSMISO, SPI1DEBUG, SPI1PASSTHRU);
SS_PIN_DECL(C16, GPIOI3, SYSMISO); SS_PIN_DECL(C16, GPIOI3, SYSMISO);
FUNC_GROUP_DECL(SPI1, C18, E15, A14, C16); #define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
#define B15 68
SIG_EXPR_DECL(SPI1CS0, SPI1, COND1, SPI1_DESC);
SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1),
SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG),
SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU));
SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOSROM, COND1, VB_DESC);
MS_PIN_DECL(B15, GPIOI4, SPI1CS0, VBCS);
#define C15 69
SIG_EXPR_DECL(SPI1CK, SPI1, COND1, SPI1_DESC);
SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1),
SIG_EXPR_PTR(SPI1CK, SPI1DEBUG),
SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU));
SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOSROM, COND1, VB_DESC);
MS_PIN_DECL(C15, GPIOI5, SPI1CK, VBCK);
#define A14 70
SIG_EXPR_DECL(SPI1MOSI, SPI1, COND1, SPI1_DESC);
SIG_EXPR_DECL(SPI1MOSI, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL(SPI1MOSI, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL(SPI1MOSI, SIG_EXPR_PTR(SPI1MOSI, SPI1),
SIG_EXPR_PTR(SPI1MOSI, SPI1DEBUG),
SIG_EXPR_PTR(SPI1MOSI, SPI1PASSTHRU));
SIG_EXPR_LIST_DECL_SINGLE(VBMOSI, VGABIOSROM, COND1, VB_DESC);
MS_PIN_DECL(A14, GPIOI6, SPI1MOSI, VBMOSI);
#define A15 71
SIG_EXPR_DECL(SPI1MISO, SPI1, COND1, SPI1_DESC);
SIG_EXPR_DECL(SPI1MISO, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
SIG_EXPR_DECL(SPI1MISO, SPI1PASSTHRU, COND1, SPI1PASSTHRU_DESC);
SIG_EXPR_LIST_DECL(SPI1MISO, SIG_EXPR_PTR(SPI1MISO, SPI1),
SIG_EXPR_PTR(SPI1MISO, SPI1DEBUG),
SIG_EXPR_PTR(SPI1MISO, SPI1PASSTHRU));
SIG_EXPR_LIST_DECL_SINGLE(VBMISO, VGABIOSROM, COND1, VB_DESC);
MS_PIN_DECL(A15, GPIOI7, SPI1MISO, VBMISO);
FUNC_GROUP_DECL(SPI1, B15, C15, A14, A15);
FUNC_GROUP_DECL(SPI1DEBUG, C18, E15, B16, C16, B15, C15, A14, A15);
FUNC_GROUP_DECL(SPI1PASSTHRU, C18, E15, B16, C16, B15, C15, A14, A15);
FUNC_GROUP_DECL(VGABIOSROM, B15, C15, A14, A15);
#define R2 72
SIG_EXPR_LIST_DECL_SINGLE(SGPMCK, SGPM, SIG_DESC_SET(SCU84, 8));
SS_PIN_DECL(R2, GPIOJ0, SGPMCK);
#define L2 73 #define L2 73
SIG_EXPR_LIST_DECL_SINGLE(SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9)); SIG_EXPR_LIST_DECL_SINGLE(SGPMLD, SGPM, SIG_DESC_SET(SCU84, 9));
...@@ -580,6 +640,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { ...@@ -580,6 +640,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(A12), ASPEED_PINCTRL_PIN(A12),
ASPEED_PINCTRL_PIN(A13), ASPEED_PINCTRL_PIN(A13),
ASPEED_PINCTRL_PIN(A14), ASPEED_PINCTRL_PIN(A14),
ASPEED_PINCTRL_PIN(A15),
ASPEED_PINCTRL_PIN(A2), ASPEED_PINCTRL_PIN(A2),
ASPEED_PINCTRL_PIN(A3), ASPEED_PINCTRL_PIN(A3),
ASPEED_PINCTRL_PIN(A4), ASPEED_PINCTRL_PIN(A4),
...@@ -592,6 +653,8 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { ...@@ -592,6 +653,8 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(B12), ASPEED_PINCTRL_PIN(B12),
ASPEED_PINCTRL_PIN(B13), ASPEED_PINCTRL_PIN(B13),
ASPEED_PINCTRL_PIN(B14), ASPEED_PINCTRL_PIN(B14),
ASPEED_PINCTRL_PIN(B15),
ASPEED_PINCTRL_PIN(B16),
ASPEED_PINCTRL_PIN(B2), ASPEED_PINCTRL_PIN(B2),
ASPEED_PINCTRL_PIN(B20), ASPEED_PINCTRL_PIN(B20),
ASPEED_PINCTRL_PIN(B3), ASPEED_PINCTRL_PIN(B3),
...@@ -603,6 +666,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = { ...@@ -603,6 +666,7 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(C12), ASPEED_PINCTRL_PIN(C12),
ASPEED_PINCTRL_PIN(C13), ASPEED_PINCTRL_PIN(C13),
ASPEED_PINCTRL_PIN(C14), ASPEED_PINCTRL_PIN(C14),
ASPEED_PINCTRL_PIN(C15),
ASPEED_PINCTRL_PIN(C16), ASPEED_PINCTRL_PIN(C16),
ASPEED_PINCTRL_PIN(C18), ASPEED_PINCTRL_PIN(C18),
ASPEED_PINCTRL_PIN(C2), ASPEED_PINCTRL_PIN(C2),
...@@ -691,11 +755,14 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = { ...@@ -691,11 +755,14 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = {
ASPEED_PINCTRL_GROUP(RMII2), ASPEED_PINCTRL_GROUP(RMII2),
ASPEED_PINCTRL_GROUP(SD1), ASPEED_PINCTRL_GROUP(SD1),
ASPEED_PINCTRL_GROUP(SPI1), ASPEED_PINCTRL_GROUP(SPI1),
ASPEED_PINCTRL_GROUP(SPI1DEBUG),
ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
ASPEED_PINCTRL_GROUP(TIMER4), ASPEED_PINCTRL_GROUP(TIMER4),
ASPEED_PINCTRL_GROUP(TIMER5), ASPEED_PINCTRL_GROUP(TIMER5),
ASPEED_PINCTRL_GROUP(TIMER6), ASPEED_PINCTRL_GROUP(TIMER6),
ASPEED_PINCTRL_GROUP(TIMER7), ASPEED_PINCTRL_GROUP(TIMER7),
ASPEED_PINCTRL_GROUP(TIMER8), ASPEED_PINCTRL_GROUP(TIMER8),
ASPEED_PINCTRL_GROUP(VGABIOSROM),
}; };
static const struct aspeed_pin_function aspeed_g5_functions[] = { static const struct aspeed_pin_function aspeed_g5_functions[] = {
...@@ -733,11 +800,14 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = { ...@@ -733,11 +800,14 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = {
ASPEED_PINCTRL_FUNC(RMII2), ASPEED_PINCTRL_FUNC(RMII2),
ASPEED_PINCTRL_FUNC(SD1), ASPEED_PINCTRL_FUNC(SD1),
ASPEED_PINCTRL_FUNC(SPI1), ASPEED_PINCTRL_FUNC(SPI1),
ASPEED_PINCTRL_FUNC(SPI1DEBUG),
ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
ASPEED_PINCTRL_FUNC(TIMER4), ASPEED_PINCTRL_FUNC(TIMER4),
ASPEED_PINCTRL_FUNC(TIMER5), ASPEED_PINCTRL_FUNC(TIMER5),
ASPEED_PINCTRL_FUNC(TIMER6), ASPEED_PINCTRL_FUNC(TIMER6),
ASPEED_PINCTRL_FUNC(TIMER7), ASPEED_PINCTRL_FUNC(TIMER7),
ASPEED_PINCTRL_FUNC(TIMER8), ASPEED_PINCTRL_FUNC(TIMER8),
ASPEED_PINCTRL_FUNC(VGABIOSROM),
}; };
static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = { static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
......
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