Commit 8eeab81c authored by James Hogan's avatar James Hogan Committed by Paolo Bonzini

MIPS: KVM: Decode RDHWR more strictly

When KVM emulates the RDHWR instruction, decode the instruction more
strictly. The rs field (bits 25:21) should be zero, as should bits 10:9.
Bits 8:6 is the register select field in MIPSr6, so we aren't strict
about those bits (no other operations should use that encoding space).
Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Radim KrÄmáŠ<rkrcmar@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: kvm@vger.kernel.org
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
parent 5cc4aafc
...@@ -2357,7 +2357,9 @@ enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc, ...@@ -2357,7 +2357,9 @@ enum emulation_result kvm_mips_handle_ri(u32 cause, u32 *opc,
} }
if (inst.r_format.opcode == spec3_op && if (inst.r_format.opcode == spec3_op &&
inst.r_format.func == rdhwr_op) { inst.r_format.func == rdhwr_op &&
inst.r_format.rs == 0 &&
(inst.r_format.re >> 3) == 0) {
int usermode = !KVM_GUEST_KERNEL_MODE(vcpu); int usermode = !KVM_GUEST_KERNEL_MODE(vcpu);
int rd = inst.r_format.rd; int rd = inst.r_format.rd;
int rt = inst.r_format.rt; int rt = inst.r_format.rt;
......
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