Commit 8f2d9010 authored by Anson Huang's avatar Anson Huang Committed by Rob Herring

dt-bindings: timer: Convert i.MX TPM to json-schema

Convert the i.MX TPM binding to DT schema format using json-schema.
Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Reviewed-by: default avatarDong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent 268b7e3c
NXP Low Power Timer/Pulse Width Modulation Module (TPM)
The Timer/PWM Module (TPM) supports input capture, output compare,
and the generation of PWM signals to control electric motor and power
management applications. The counter, compare and capture registers
are clocked by an asynchronous clock that can remain enabled in low
power modes. TPM can support global counter bus where one TPM drives
the counter bus for the others, provided bit width is the same.
Required properties:
- compatible : should be "fsl,imx7ulp-tpm"
- reg : Specifies base physical address and size of the register sets
for the clock event device and clock source device.
- interrupts : Should be the clock event device interrupt.
- clocks : The clocks provided by the SoC to drive the timer, must contain
an entry for each entry in clock-names.
- clock-names : Must include the following entries: "ipg" and "per".
Example:
tpm5: tpm@40260000 {
compatible = "fsl,imx7ulp-tpm";
reg = <0x40260000 0x1000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX7ULP_CLK_NIC1_BUS_DIV>,
<&clks IMX7ULP_CLK_LPTPM5>;
clock-names = "ipg", "per";
};
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP Low Power Timer/Pulse Width Modulation Module (TPM)
maintainers:
- Dong Aisheng <aisheng.dong@nxp.com>
description: |
The Timer/PWM Module (TPM) supports input capture, output compare,
and the generation of PWM signals to control electric motor and power
management applications. The counter, compare and capture registers
are clocked by an asynchronous clock that can remain enabled in low
power modes. TPM can support global counter bus where one TPM drives
the counter bus for the others, provided bit width is the same.
properties:
compatible:
const: fsl,imx7ulp-tpm
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: SoC TPM ipg clock
- description: SoC TPM per clock
clock-names:
items:
- const: ipg
- const: per
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx7ulp-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
timer@40260000 {
compatible = "fsl,imx7ulp-tpm";
reg = <0x40260000 0x1000>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scg1 IMX7ULP_CLK_NIC1_BUS_DIV>,
<&pcc2 IMX7ULP_CLK_LPTPM5>;
clock-names = "ipg", "per";
};
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