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Commit 8f59ae06 authored by Linus Torvalds's avatar Linus Torvalds
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC fixes from Arnd Bergmann:
 "A few patches have come up since the merge window.  The largest one is
  a rewrite of the PXA lubbock/mainstone IRQ handling.  This was already
  broken in 2011 by a change to the GPIO code and only noticed now.

  The other changes contained here are:

  MAINTAINERS file updates:

   - Ray Jui and Scott Branden are now co-maintainers for some of the
     mach-bcm chips, while Christian Daudt and Marc Carino have stepped
     down.

   - Andrew Victor is no longer maintaining at91.  Instead, Alexandre
     Belloni now becomes an official maintainer, after having done a
     bulk of the work for a while.

   - Baruch Siach, who added the mach-digicolor platform in 4.1 is now
     listed as maintainer

   - The git URL for mach-socfpga has changed

  Bug fixes:

   - Three bug fixes for new rockchip rk3288 code

   - A regression fix to make SD card support work on certain ux500
     boards

   - multiple smaller dts fixes for imx, omap, mvebu, and shmobile

   - a regression fiix for omap3 power consumption

   - a fix for regression in the ARM CCI bus driver

  Configuration changes:

   - more imx platforms are now enabled in multi_v7_defconfig"

* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (39 commits)
  MAINTAINERS: add Conexant Digicolor machines entry
  MAINTAINERS: socfpga: update the git repo for SoCFPGA
  ARM: multi_v7_defconfig: Select more FSL SoCs
  MAINTAINERS: replace an AT91 maintainer
  drivers: CCI: fix used_mask init in validate_group()
  bus: omap_l3_noc: Fix master id address decoding for OMAP5
  bus: omap_l3_noc: Fix offset for DRA7 CLK1_HOST_CLK1_2 instance
  ARM: dts: dra7: Fix efuse register size for ABB
  ARM: dts: am57xx-beagle-x15: Switch GPIO fan number
  ARM: dts: am57xx-beagle-x15: Switch UART mux pins
  ARM: dts: am437x-sk: reduce col-scan-delay-us
  ARM: dts: am437x-sk: fix for new newhaven display module revision
  ARM: dts: am57xx-beagle-x15: Fix RTC aliases
  ARM: dts: am57xx-beagle-x15: Fix IRQ type for mcp7941x
  ARM: dts: omap3: Add #iommu-cells to isp and iva iommu
  ARM: omap2plus_defconfig: Enable EXTCON_USB_GPIO
  ARM: dts: OMAP3-N900: Add microphone bias voltages
  ARM: OMAP2+: Fix omap off idle power consumption creeping up
  MAINTAINERS: Update brcmstb entry
  MAINTAINERS: Remove Christian Daudt for mach-bcm
  ...
parents 51dfcb07 c9d862c4
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CREDITS
View file @ 8f59ae06
......@@ -3709,6 +3709,13 @@ N: Dirk Verworner
D: Co-author of German book ``Linux-Kernel-Programmierung''
D: Co-founder of Berlin Linux User Group
N: Andrew Victor
E: linux@maxim.org.za
W: http://maxim.org.za/at91_26.html
D: First maintainer of Atmel ARM-based SoC, aka AT91
D: Introduced support for at91rm9200, the first chip of AT91 family
S: South Africa
N: Riku Voipio
E: riku.voipio@iki.fi
D: Author of PCA9532 LED and Fintek f75375s hwmon driver
......
Documentation/devicetree/bindings/arm/omap/l3-noc.txt
View file @ 8f59ae06
......@@ -6,6 +6,7 @@ provided by Arteris.
Required properties:
- compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
Should be "ti,omap4-l3-noc" for OMAP4 family
Should be "ti,omap5-l3-noc" for OMAP5 family
Should be "ti,dra7-l3-noc" for DRA7 family
Should be "ti,am4372-l3-noc" for AM43 family
- reg: Contains L3 register address range for each noc domain.
......
Documentation/devicetree/bindings/dma/fsl-mxs-dma.txt
View file @ 8f59ae06
......@@ -38,7 +38,7 @@ dma_apbx: dma-apbx@80024000 {
80 81 68 69
70 71 72 73
74 75 76 77>;
interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
"saif0", "saif1", "i2c0", "i2c1",
"auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
"auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
......
MAINTAINERS
View file @ 8f59ae06
......@@ -892,11 +892,10 @@ S: Maintained
F: arch/arm/mach-alpine/
ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES
M: Andrew Victor <linux@maxim.org.za>
M: Nicolas Ferre <nicolas.ferre@atmel.com>
M: Alexandre Belloni <alexandre.belloni@free-electrons.com>
M: Jean-Christophe Plagniol-Villard <plagnioj@jcrosoft.com>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
W: http://maxim.org.za/at91_26.html
W: http://www.linux4sam.org
S: Supported
F: arch/arm/mach-at91/
......@@ -990,6 +989,12 @@ F: drivers/clocksource/timer-prima2.c
F: drivers/clocksource/timer-atlas7.c
N: [^a-z]sirf
ARM/CONEXANT DIGICOLOR MACHINE SUPPORT
M: Baruch Siach <baruch@tkos.co.il>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
N: digicolor
ARM/EBSA110 MACHINE SUPPORT
M: Russell King <linux@arm.linux.org.uk>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
......@@ -1439,9 +1444,10 @@ ARM/SOCFPGA ARCHITECTURE
M: Dinh Nguyen <dinguyen@opensource.altera.com>
S: Maintained
F: arch/arm/mach-socfpga/
F: arch/arm/boot/dts/socfpga*
F: arch/arm/configs/socfpga_defconfig
W: http://www.rocketboards.org
T: git://git.rocketboards.org/linux-socfpga.git
T: git://git.rocketboards.org/linux-socfpga-next.git
T: git git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git
ARM/SOCFPGA CLOCK FRAMEWORK SUPPORT
M: Dinh Nguyen <dinguyen@opensource.altera.com>
......@@ -2116,8 +2122,9 @@ S: Supported
F: drivers/net/ethernet/broadcom/bnx2x/
BROADCOM BCM281XX/BCM11XXX/BCM216XX ARM ARCHITECTURE
M: Christian Daudt <bcm@fixthebug.org>
M: Florian Fainelli <f.fainelli@gmail.com>
M: Ray Jui <rjui@broadcom.com>
M: Scott Branden <sbranden@broadcom.com>
L: bcm-kernel-feedback-list@broadcom.com
T: git git://github.com/broadcom/mach-bcm
S: Maintained
......@@ -2168,7 +2175,6 @@ S: Maintained
F: drivers/usb/gadget/udc/bcm63xx_udc.*
BROADCOM BCM7XXX ARM ARCHITECTURE
M: Marc Carino <marc.ceeeee@gmail.com>
M: Brian Norris <computersforpeace@gmail.com>
M: Gregory Fong <gregory.0xf0@gmail.com>
M: Florian Fainelli <f.fainelli@gmail.com>
......
arch/arm/boot/dts/am437x-sk-evm.dts
View file @ 8f59ae06
......@@ -49,7 +49,7 @@ matrix_keypad: matrix_keypad@0 {
pinctrl-0 = <&matrix_keypad_pins>;
debounce-delay-ms = <5>;
col-scan-delay-us = <1500>;
col-scan-delay-us = <5>;
row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */
&gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */
......@@ -473,7 +473,7 @@ edt-ft5306@38 {
interrupt-parent = <&gpio0>;
interrupts = <31 0>;
wake-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
touchscreen-size-x = <480>;
touchscreen-size-y = <272>;
......
arch/arm/boot/dts/am57xx-beagle-x15.dts
View file @ 8f59ae06
......@@ -18,6 +18,7 @@ / {
aliases {
rtc0 = &mcp_rtc;
rtc1 = &tps659038_rtc;
rtc2 = &rtc;
};
memory {
......@@ -83,7 +84,7 @@ led@3 {
gpio_fan: gpio_fan {
/* Based on 5v 500mA AFB02505HHB */
compatible = "gpio-fan";
gpios = <&tps659038_gpio 1 GPIO_ACTIVE_HIGH>;
gpios = <&tps659038_gpio 2 GPIO_ACTIVE_HIGH>;
gpio-fan,speed-map = <0 0>,
<13000 1>;
#cooling-cells = <2>;
......@@ -130,8 +131,8 @@ i2c3_pins_default: i2c3_pins_default {
uart3_pins_default: uart3_pins_default {
pinctrl-single,pins = <
0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd.rxd */
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd.txd */
0x3f8 (PIN_INPUT_SLEW | MUX_MODE2) /* uart2_ctsn.uart3_rxd */
0x3fc (PIN_INPUT_SLEW | MUX_MODE1) /* uart2_rtsn.uart3_txd */
>;
};
......@@ -455,7 +456,7 @@ &i2c3 {
mcp_rtc: rtc@6f {
compatible = "microchip,mcp7941x";
reg = <0x6f>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>; /* IRQ_SYS_1N */
interrupts = <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>; /* IRQ_SYS_1N */
pinctrl-names = "default";
pinctrl-0 = <&mcp79410_pins_default>;
......@@ -478,7 +479,7 @@ &cpu0 {
&uart3 {
status = "okay";
interrupts-extended = <&crossbar_mpu GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<&dra7_pmx_core 0x248>;
<&dra7_pmx_core 0x3f8>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins_default>;
......
arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
View file @ 8f59ae06
......@@ -105,6 +105,10 @@ pcie@1,0 {
};
internal-regs {
rtc@10300 {
/* No crystal connected to the internal RTC */
status = "disabled";
};
serial@12000 {
status = "okay";
};
......
arch/arm/boot/dts/dra7.dtsi
View file @ 8f59ae06
......@@ -911,7 +911,7 @@ abb_mpu: regulator-abb-mpu {
ti,clock-cycles = <16>;
reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
<0x4ae06014 0x4>, <0x4a003b20 0x8>,
<0x4ae06014 0x4>, <0x4a003b20 0xc>,
<0x4ae0c158 0x4>;
reg-names = "setup-address", "control-address",
"int-address", "efuse-address",
......@@ -944,7 +944,7 @@ abb_ivahd: regulator-abb-ivahd {
ti,clock-cycles = <16>;
reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
<0x4ae06010 0x4>, <0x4a0025cc 0x8>,
<0x4ae06010 0x4>, <0x4a0025cc 0xc>,
<0x4a002470 0x4>;
reg-names = "setup-address", "control-address",
"int-address", "efuse-address",
......@@ -977,7 +977,7 @@ abb_dspeve: regulator-abb-dspeve {
ti,clock-cycles = <16>;
reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
<0x4ae06010 0x4>, <0x4a0025e0 0x8>,
<0x4ae06010 0x4>, <0x4a0025e0 0xc>,
<0x4a00246c 0x4>;
reg-names = "setup-address", "control-address",
"int-address", "efuse-address",
......@@ -1010,7 +1010,7 @@ abb_gpu: regulator-abb-gpu {
ti,clock-cycles = <16>;
reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
<0x4ae06010 0x4>, <0x4a003b08 0x8>,
<0x4ae06010 0x4>, <0x4a003b08 0xc>,
<0x4ae0c154 0x4>;
reg-names = "setup-address", "control-address",
"int-address", "efuse-address",
......@@ -1203,7 +1203,7 @@ omap_control_pcie2phy: control-pcie@0x4a003c44 {
status = "disabled";
};
rtc@48838000 {
rtc: rtc@48838000 {
compatible = "ti,am3352-rtc";
reg = <0x48838000 0x100>;
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
......
arch/arm/boot/dts/imx23-olinuxino.dts
View file @ 8f59ae06
......@@ -12,6 +12,7 @@
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx23.dtsi"
/ {
......@@ -93,6 +94,7 @@ usbphy0: usbphy@8007c000 {
ahb@80080000 {
usb0: usb@80080000 {
dr_mode = "host";
vbus-supply = <&reg_usb0_vbus>;
status = "okay";
};
......@@ -122,7 +124,7 @@ leds {
user {
label = "green";
gpios = <&gpio2 1 1>;
gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
};
};
};
arch/arm/boot/dts/imx25.dtsi
View file @ 8f59ae06
......@@ -428,6 +428,7 @@ slcdc@53fc0000 {
pwm4: pwm@53fc8000 {
compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
#pwm-cells = <2>;
reg = <0x53fc8000 0x4000>;
clocks = <&clks 108>, <&clks 52>;
clock-names = "ipg", "per";
......
arch/arm/boot/dts/imx28.dtsi
View file @ 8f59ae06
......@@ -913,7 +913,7 @@ dma_apbx: dma-apbx@80024000 {
80 81 68 69
70 71 72 73
74 75 76 77>;
interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty",
"saif0", "saif1", "i2c0", "i2c1",
"auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
"auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
......
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
View file @ 8f59ae06
......@@ -31,6 +31,7 @@ reg_usb_otg_vbus: regulator@0 {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 15 0>;
enable-active-high;
};
reg_usb_h1_vbus: regulator@1 {
......@@ -40,6 +41,7 @@ reg_usb_h1_vbus: regulator@1 {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 0 0>;
enable-active-high;
};
};
......
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
View file @ 8f59ae06
......@@ -185,7 +185,6 @@ vgen6_reg: vgen6 {
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
status = "okay";
max7310_a: gpio@30 {
......
arch/arm/boot/dts/omap3-n900.dts
View file @ 8f59ae06
......@@ -498,6 +498,8 @@ tlv320aic3x: tlv320aic3x@18 {
DRVDD-supply = <&vmmc2>;
IOVDD-supply = <&vio>;
DVDD-supply = <&vio>;
ai3x-micbias-vg = <1>;
};
tlv320aic3x_aux: tlv320aic3x@19 {
......@@ -509,6 +511,8 @@ tlv320aic3x_aux: tlv320aic3x@19 {
DRVDD-supply = <&vmmc2>;
IOVDD-supply = <&vio>;
DVDD-supply = <&vio>;
ai3x-micbias-vg = <2>;
};
tsl2563: tsl2563@29 {
......
arch/arm/boot/dts/omap3.dtsi
View file @ 8f59ae06
......@@ -456,6 +456,7 @@ mmc3: mmc@480ad000 {
};
mmu_isp: mmu@480bd400 {
#iommu-cells = <0>;
compatible = "ti,omap2-iommu";
reg = <0x480bd400 0x80>;
interrupts = <24>;
......@@ -464,6 +465,7 @@ mmu_isp: mmu@480bd400 {
};
mmu_iva: mmu@5d000000 {
#iommu-cells = <0>;
compatible = "ti,omap2-iommu";
reg = <0x5d000000 0x80>;
interrupts = <28>;
......
arch/arm/boot/dts/omap5.dtsi
View file @ 8f59ae06
......@@ -128,7 +128,7 @@ mpu {
* hierarchy.
*/
ocp {
compatible = "ti,omap4-l3-noc", "simple-bus";
compatible = "ti,omap5-l3-noc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
......
arch/arm/boot/dts/r8a7791-koelsch.dts
View file @ 8f59ae06
......@@ -545,7 +545,7 @@ hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio3>;
interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
......
arch/arm/boot/dts/ste-dbx5x0.dtsi
View file @ 8f59ae06
......@@ -1017,23 +1017,6 @@ cpufreq-cooling {
status = "disabled";
};
vmmci: regulator-gpio {
compatible = "regulator-gpio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2900000>;
regulator-name = "mmci-reg";
regulator-type = "voltage";
startup-delay-us = <100>;
enable-active-high;
states = <1800000 0x1
2900000 0x0>;
status = "disabled";
};
mcde@a0350000 {
compatible = "stericsson,mcde";
reg = <0xa0350000 0x1000>, /* MCDE */
......
arch/arm/boot/dts/ste-href.dtsi
View file @ 8f59ae06
......@@ -111,6 +111,21 @@ i2c@80110000 {
pinctrl-1 = <&i2c3_sleep_mode>;
};
vmmci: regulator-gpio {
compatible = "regulator-gpio";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2900000>;
regulator-name = "mmci-reg";
regulator-type = "voltage";
startup-delay-us = <100>;
enable-active-high;
states = <1800000 0x1
2900000 0x0>;
};
// External Micro SD slot
sdi0_per1@80126000 {
arm,primecell-periphid = <0x10480180>;
......
arch/arm/boot/dts/ste-snowball.dts
View file @ 8f59ae06
......@@ -146,8 +146,21 @@ ethernet@0 {
};
vmmci: regulator-gpio {
compatible = "regulator-gpio";
gpios = <&gpio7 4 0x4>;
enable-gpio = <&gpio6 25 0x4>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2900000>;
regulator-name = "mmci-reg";
regulator-type = "voltage";
startup-delay-us = <100>;
enable-active-high;
states = <1800000 0x1
2900000 0x0>;
};
// External Micro SD slot
......
arch/arm/configs/multi_v7_defconfig
View file @ 8f59ae06
......@@ -39,11 +39,14 @@ CONFIG_ARCH_HIP04=y
CONFIG_ARCH_KEYSTONE=y
CONFIG_ARCH_MESON=y
CONFIG_ARCH_MXC=y
CONFIG_SOC_IMX50=y
CONFIG_SOC_IMX51=y
CONFIG_SOC_IMX53=y
CONFIG_SOC_IMX6Q=y
CONFIG_SOC_IMX6SL=y
CONFIG_SOC_IMX6SX=y
CONFIG_SOC_VF610=y
CONFIG_SOC_LS1021A=y
CONFIG_ARCH_OMAP3=y
CONFIG_ARCH_OMAP4=y
CONFIG_SOC_OMAP5=y
......
arch/arm/configs/omap2plus_defconfig
View file @ 8f59ae06
......@@ -393,7 +393,7 @@ CONFIG_TI_EDMA=y
CONFIG_DMA_OMAP=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_EXTCON=m
CONFIG_EXTCON_GPIO=m
CONFIG_EXTCON_USB_GPIO=m
CONFIG_EXTCON_PALMAS=m
CONFIG_TI_EMIF=m
CONFIG_PWM=y
......
arch/arm/mach-imx/devices/platform-sdhci-esdhc-imx.c
View file @ 8f59ae06
/*
* Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de>
* Copyright (C) 2010 Pengutronix, Wolfram Sang <kernel@pengutronix.de>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
......
arch/arm/mach-omap2/prm-regbits-34xx.h
View file @ 8f59ae06
......@@ -112,6 +112,7 @@
#define OMAP3430_VC_CMD_ONLP_SHIFT 16
#define OMAP3430_VC_CMD_RET_SHIFT 8
#define OMAP3430_VC_CMD_OFF_SHIFT 0
#define OMAP3430_SREN_MASK (1 << 4)
#define OMAP3430_HSEN_MASK (1 << 3)
#define OMAP3430_MCODE_MASK (0x7 << 0)
#define OMAP3430_VALID_MASK (1 << 24)
......
arch/arm/mach-omap2/prm-regbits-44xx.h
View file @ 8f59ae06
......@@ -35,6 +35,7 @@
#define OMAP4430_GLOBAL_WARM_SW_RST_SHIFT 1
#define OMAP4430_GLOBAL_WUEN_MASK (1 << 16)
#define OMAP4430_HSMCODE_MASK (0x7 << 0)
#define OMAP4430_SRMODEEN_MASK (1 << 4)
#define OMAP4430_HSMODEEN_MASK (1 << 3)
#define OMAP4430_HSSCLL_SHIFT 24
#define OMAP4430_ICEPICK_RST_SHIFT 9
......
arch/arm/mach-omap2/vc.c
View file @ 8f59ae06
......@@ -316,7 +316,8 @@ static void __init omap3_vc_init_pmic_signaling(struct voltagedomain *voltdm)
* idle. And we can also scale voltages to zero for off-idle.
* Note that no actual voltage scaling during off-idle will
* happen unless the board specific twl4030 PMIC scripts are
* loaded.
* loaded. See also omap_vc_i2c_init for comments regarding
* erratum i531.
*/
val = voltdm->read(OMAP3_PRM_VOLTCTRL_OFFSET);
if (!(val & OMAP3430_PRM_VOLTCTRL_SEL_OFF)) {
......@@ -704,9 +705,16 @@ static void __init omap_vc_i2c_init(struct voltagedomain *voltdm)
return;
}
/*
* Note that for omap3 OMAP3430_SREN_MASK clears SREN to work around
* erratum i531 "Extra Power Consumed When Repeated Start Operation
* Mode Is Enabled on I2C Interface Dedicated for Smart Reflex (I2C4)".
* Otherwise I2C4 eventually leads into about 23mW extra power being
* consumed even during off idle using VMODE.
*/
i2c_high_speed = voltdm->pmic->i2c_high_speed;
if (i2c_high_speed)
voltdm->rmw(vc->common->i2c_cfg_hsen_mask,
voltdm->rmw(vc->common->i2c_cfg_clear_mask,
vc->common->i2c_cfg_hsen_mask,
vc->common->i2c_cfg_reg);
......
arch/arm/mach-omap2/vc.h
View file @ 8f59ae06
......@@ -34,6 +34,7 @@ struct voltagedomain;
* @cmd_ret_shift: RET field shift in PRM_VC_CMD_VAL_* register
* @cmd_off_shift: OFF field shift in PRM_VC_CMD_VAL_* register
* @i2c_cfg_reg: I2C configuration register offset
* @i2c_cfg_clear_mask: high-speed mode bit clear mask in I2C config register
* @i2c_cfg_hsen_mask: high-speed mode bit field mask in I2C config register
* @i2c_mcode_mask: MCODE field mask for I2C config register
*
......@@ -52,6 +53,7 @@ struct omap_vc_common {
u8 cmd_ret_shift;
u8 cmd_off_shift;
u8 i2c_cfg_reg;
u8 i2c_cfg_clear_mask;
u8 i2c_cfg_hsen_mask;
u8 i2c_mcode_mask;
};
......
arch/arm/mach-omap2/vc3xxx_data.c
View file @ 8f59ae06
......@@ -40,6 +40,7 @@ static struct omap_vc_common omap3_vc_common = {
.cmd_onlp_shift = OMAP3430_VC_CMD_ONLP_SHIFT,
.cmd_ret_shift = OMAP3430_VC_CMD_RET_SHIFT,
.cmd_off_shift = OMAP3430_VC_CMD_OFF_SHIFT,
.i2c_cfg_clear_mask = OMAP3430_SREN_MASK | OMAP3430_HSEN_MASK,
.i2c_cfg_hsen_mask = OMAP3430_HSEN_MASK,
.i2c_cfg_reg = OMAP3_PRM_VC_I2C_CFG_OFFSET,
.i2c_mcode_mask = OMAP3430_MCODE_MASK,
......
arch/arm/mach-omap2/vc44xx_data.c
View file @ 8f59ae06
......@@ -42,6 +42,7 @@ static const struct omap_vc_common omap4_vc_common = {
.cmd_ret_shift = OMAP4430_RET_SHIFT,
.cmd_off_shift = OMAP4430_OFF_SHIFT,
.i2c_cfg_reg = OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET,
.i2c_cfg_clear_mask = OMAP4430_SRMODEEN_MASK | OMAP4430_HSMODEEN_MASK,
.i2c_cfg_hsen_mask = OMAP4430_HSMODEEN_MASK,
.i2c_mcode_mask = OMAP4430_HSMCODE_MASK,
};
......
arch/arm/mach-pxa/Kconfig
View file @ 8f59ae06
......@@ -691,4 +691,13 @@ config SHARPSL_PM_MAX1111
config PXA310_ULPI
bool
config PXA_SYSTEMS_CPLDS
tristate "Motherboard cplds"
default ARCH_LUBBOCK || MACH_MAINSTONE
help
This driver supports the Lubbock and Mainstone multifunction chip
found on the pxa25x development platform system (Lubbock) and pxa27x
development platform system (Mainstone). This IO board supports the
interrupts handling, ethernet controller, flash chips, etc ...
endif
arch/arm/mach-pxa/Makefile
View file @ 8f59ae06
......@@ -90,4 +90,5 @@ obj-$(CONFIG_MACH_RAUMFELD_CONNECTOR) += raumfeld.o
obj-$(CONFIG_MACH_RAUMFELD_SPEAKER) += raumfeld.o
obj-$(CONFIG_MACH_ZIPIT2) += z2.o
obj-$(CONFIG_PXA_SYSTEMS_CPLDS) += pxa_cplds_irqs.o
obj-$(CONFIG_TOSA_BT) += tosa-bt.o
arch/arm/mach-pxa/include/mach/lubbock.h
View file @ 8f59ae06
......@@ -37,7 +37,9 @@
#define LUB_GP __LUB_REG(LUBBOCK_FPGA_PHYS + 0x100)
/* Board specific IRQs */
#define LUBBOCK_IRQ(x) (IRQ_BOARD_START + (x))
#define LUBBOCK_NR_IRQS IRQ_BOARD_START
#define LUBBOCK_IRQ(x) (LUBBOCK_NR_IRQS + (x))
#define LUBBOCK_SD_IRQ LUBBOCK_IRQ(0)
#define LUBBOCK_SA1111_IRQ LUBBOCK_IRQ(1)
#define LUBBOCK_USB_IRQ LUBBOCK_IRQ(2) /* usb connect */
......@@ -47,8 +49,7 @@
#define LUBBOCK_USB_DISC_IRQ LUBBOCK_IRQ(6) /* usb disconnect */
#define LUBBOCK_LAST_IRQ LUBBOCK_IRQ(6)
#define LUBBOCK_SA1111_IRQ_BASE (IRQ_BOARD_START + 16)
#define LUBBOCK_NR_IRQS (IRQ_BOARD_START + 16 + 55)
#define LUBBOCK_SA1111_IRQ_BASE (LUBBOCK_NR_IRQS + 32)
#ifndef __ASSEMBLY__
extern void lubbock_set_misc_wr(unsigned int mask, unsigned int set);
......
arch/arm/mach-pxa/include/mach/mainstone.h
View file @ 8f59ae06
......@@ -120,7 +120,9 @@
#define MST_PCMCIA_PWR_VCC_50 0x4 /* voltage VCC = 5.0V */
/* board specific IRQs */
#define MAINSTONE_IRQ(x) (IRQ_BOARD_START + (x))
#define MAINSTONE_NR_IRQS IRQ_BOARD_START
#define MAINSTONE_IRQ(x) (MAINSTONE_NR_IRQS + (x))
#define MAINSTONE_MMC_IRQ MAINSTONE_IRQ(0)
#define MAINSTONE_USIM_IRQ MAINSTONE_IRQ(1)
#define MAINSTONE_USBC_IRQ MAINSTONE_IRQ(2)
......@@ -136,6 +138,4 @@
#define MAINSTONE_S1_STSCHG_IRQ MAINSTONE_IRQ(14)
#define MAINSTONE_S1_IRQ MAINSTONE_IRQ(15)
#define MAINSTONE_NR_IRQS (IRQ_BOARD_START + 16)
#endif
arch/arm/mach-pxa/lubbock.c
View file @ 8f59ae06
......@@ -12,6 +12,7 @@
* published by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
......@@ -123,84 +124,6 @@ void lubbock_set_misc_wr(unsigned int mask, unsigned int set)
}
EXPORT_SYMBOL(lubbock_set_misc_wr);
static unsigned long lubbock_irq_enabled;
static void lubbock_mask_irq(struct irq_data *d)
{
int lubbock_irq = (d->irq - LUBBOCK_IRQ(0));
LUB_IRQ_MASK_EN = (lubbock_irq_enabled &= ~(1 << lubbock_irq));
}
static void lubbock_unmask_irq(struct irq_data *d)
{
int lubbock_irq = (d->irq - LUBBOCK_IRQ(0));
/* the irq can be acknowledged only if deasserted, so it's done here */
LUB_IRQ_SET_CLR &= ~(1 << lubbock_irq);
LUB_IRQ_MASK_EN = (lubbock_irq_enabled |= (1 << lubbock_irq));
}
static struct irq_chip lubbock_irq_chip = {
.name = "FPGA",
.irq_ack = lubbock_mask_irq,
.irq_mask = lubbock_mask_irq,
.irq_unmask = lubbock_unmask_irq,
};
static void lubbock_irq_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned long pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
do {
/* clear our parent irq */
desc->irq_data.chip->irq_ack(&desc->irq_data);
if (likely(pending)) {
irq = LUBBOCK_IRQ(0) + __ffs(pending);
generic_handle_irq(irq);
}
pending = LUB_IRQ_SET_CLR & lubbock_irq_enabled;
} while (pending);
}
static void __init lubbock_init_irq(void)
{
int irq;
pxa25x_init_irq();
/* setup extra lubbock irqs */
for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) {
irq_set_chip_and_handler(irq, &lubbock_irq_chip,
handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), lubbock_irq_handler);
irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
}
#ifdef CONFIG_PM
static void lubbock_irq_resume(void)
{
LUB_IRQ_MASK_EN = lubbock_irq_enabled;
}
static struct syscore_ops lubbock_irq_syscore_ops = {
.resume = lubbock_irq_resume,
};
static int __init lubbock_irq_device_init(void)
{
if (machine_is_lubbock()) {
register_syscore_ops(&lubbock_irq_syscore_ops);
return 0;
}
return -ENODEV;
}
device_initcall(lubbock_irq_device_init);
#endif
static int lubbock_udc_is_connected(void)
{
return (LUB_MISC_RD & (1 << 9)) == 0;
......@@ -383,11 +306,38 @@ static struct platform_device lubbock_flash_device[2] = {
},
};
static struct resource lubbock_cplds_resources[] = {
[0] = {
.start = LUBBOCK_FPGA_PHYS + 0xc0,
.end = LUBBOCK_FPGA_PHYS + 0xe0 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = PXA_GPIO_TO_IRQ(0),
.end = PXA_GPIO_TO_IRQ(0),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
[2] = {
.start = LUBBOCK_IRQ(0),
.end = LUBBOCK_IRQ(6),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device lubbock_cplds_device = {
.name = "pxa_cplds_irqs",
.id = -1,
.resource = &lubbock_cplds_resources[0],
.num_resources = 3,
};
static struct platform_device *devices[] __initdata = {
&sa1111_device,
&smc91x_device,
&lubbock_flash_device[0],
&lubbock_flash_device[1],
&lubbock_cplds_device,
};
static struct pxafb_mode_info sharp_lm8v31_mode = {
......@@ -648,7 +598,7 @@ MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)")
/* Maintainer: MontaVista Software Inc. */
.map_io = lubbock_map_io,
.nr_irqs = LUBBOCK_NR_IRQS,
.init_irq = lubbock_init_irq,
.init_irq = pxa25x_init_irq,
.handle_irq = pxa25x_handle_irq,
.init_time = pxa_timer_init,
.init_machine = lubbock_init,
......
arch/arm/mach-pxa/mainstone.c
View file @ 8f59ae06
......@@ -13,6 +13,7 @@
* published by the Free Software Foundation.
*/
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
......@@ -122,92 +123,6 @@ static unsigned long mainstone_pin_config[] = {
GPIO1_GPIO | WAKEUP_ON_EDGE_BOTH,
};
static unsigned long mainstone_irq_enabled;
static void mainstone_mask_irq(struct irq_data *d)
{
int mainstone_irq = (d->irq - MAINSTONE_IRQ(0));
MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq));
}
static void mainstone_unmask_irq(struct irq_data *d)
{
int mainstone_irq = (d->irq - MAINSTONE_IRQ(0));
/* the irq can be acknowledged only if deasserted, so it's done here */
MST_INTSETCLR &= ~(1 << mainstone_irq);
MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq));
}
static struct irq_chip mainstone_irq_chip = {
.name = "FPGA",
.irq_ack = mainstone_mask_irq,
.irq_mask = mainstone_mask_irq,
.irq_unmask = mainstone_unmask_irq,
};
static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc)
{
unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
do {
/* clear useless edge notification */
desc->irq_data.chip->irq_ack(&desc->irq_data);
if (likely(pending)) {
irq = MAINSTONE_IRQ(0) + __ffs(pending);
generic_handle_irq(irq);
}
pending = MST_INTSETCLR & mainstone_irq_enabled;
} while (pending);
}
static void __init mainstone_init_irq(void)
{
int irq;
pxa27x_init_irq();
/* setup extra Mainstone irqs */
for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
irq_set_chip_and_handler(irq, &mainstone_irq_chip,
handle_level_irq);
if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
else
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
}
set_irq_flags(MAINSTONE_IRQ(8), 0);
set_irq_flags(MAINSTONE_IRQ(12), 0);
MST_INTMSKENA = 0;
MST_INTSETCLR = 0;
irq_set_chained_handler(PXA_GPIO_TO_IRQ(0), mainstone_irq_handler);
irq_set_irq_type(PXA_GPIO_TO_IRQ(0), IRQ_TYPE_EDGE_FALLING);
}
#ifdef CONFIG_PM
static void mainstone_irq_resume(void)
{
MST_INTMSKENA = mainstone_irq_enabled;
}
static struct syscore_ops mainstone_irq_syscore_ops = {
.resume = mainstone_irq_resume,
};
static int __init mainstone_irq_device_init(void)
{
if (machine_is_mainstone())
register_syscore_ops(&mainstone_irq_syscore_ops);
return 0;
}
device_initcall(mainstone_irq_device_init);
#endif
static struct resource smc91x_resources[] = {
[0] = {
.start = (MST_ETH_PHYS + 0x300),
......@@ -487,11 +402,37 @@ static struct platform_device mst_gpio_keys_device = {
},
};
static struct resource mst_cplds_resources[] = {
[0] = {
.start = MST_FPGA_PHYS + 0xc0,
.end = MST_FPGA_PHYS + 0xe0 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = PXA_GPIO_TO_IRQ(0),
.end = PXA_GPIO_TO_IRQ(0),
.flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
},
[2] = {
.start = MAINSTONE_IRQ(0),
.end = MAINSTONE_IRQ(15),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device mst_cplds_device = {
.name = "pxa_cplds_irqs",
.id = -1,
.resource = &mst_cplds_resources[0],
.num_resources = 3,
};
static struct platform_device *platform_devices[] __initdata = {
&smc91x_device,
&mst_flash_device[0],
&mst_flash_device[1],
&mst_gpio_keys_device,
&mst_cplds_device,
};
static struct pxaohci_platform_data mainstone_ohci_platform_data = {
......@@ -718,7 +659,7 @@ MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
.atag_offset = 0x100, /* BLOB boot parameter setting */
.map_io = mainstone_map_io,
.nr_irqs = MAINSTONE_NR_IRQS,
.init_irq = mainstone_init_irq,
.init_irq = pxa27x_init_irq,
.handle_irq = pxa27x_handle_irq,
.init_time = pxa_timer_init,
.init_machine = mainstone_init,
......
arch/arm/mach-pxa/pxa_cplds_irqs.c 0 → 100644
View file @ 8f59ae06
/*
* Intel Reference Systems cplds
*
* Copyright (C) 2014 Robert Jarzmik
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* Cplds motherboard driver, supporting lubbock and mainstone SoC board.
*/
#include <linux/bitops.h>
#include <linux/gpio.h>
#include <linux/gpio/consumer.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/mfd/core.h>
#include <linux/module.h>
#include <linux/of_platform.h>
#define FPGA_IRQ_MASK_EN 0x0
#define FPGA_IRQ_SET_CLR 0x10
#define CPLDS_NB_IRQ 32
struct cplds {
void __iomem *base;
int irq;
unsigned int irq_mask;
struct gpio_desc *gpio0;
struct irq_domain *irqdomain;
};
static irqreturn_t cplds_irq_handler(int in_irq, void *d)
{
struct cplds *fpga = d;
unsigned long pending;
unsigned int bit;
pending = readl(fpga->base + FPGA_IRQ_SET_CLR) & fpga->irq_mask;
for_each_set_bit(bit, &pending, CPLDS_NB_IRQ)
generic_handle_irq(irq_find_mapping(fpga->irqdomain, bit));
return IRQ_HANDLED;
}
static void cplds_irq_mask_ack(struct irq_data *d)
{
struct cplds *fpga = irq_data_get_irq_chip_data(d);
unsigned int cplds_irq = irqd_to_hwirq(d);
unsigned int set, bit = BIT(cplds_irq);
fpga->irq_mask &= ~bit;
writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
set = readl(fpga->base + FPGA_IRQ_SET_CLR);
writel(set & ~bit, fpga->base + FPGA_IRQ_SET_CLR);
}
static void cplds_irq_unmask(struct irq_data *d)
{
struct cplds *fpga = irq_data_get_irq_chip_data(d);
unsigned int cplds_irq = irqd_to_hwirq(d);
unsigned int bit = BIT(cplds_irq);
fpga->irq_mask |= bit;
writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
}
static struct irq_chip cplds_irq_chip = {
.name = "pxa_cplds",
.irq_mask_ack = cplds_irq_mask_ack,
.irq_unmask = cplds_irq_unmask,
.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
};
static int cplds_irq_domain_map(struct irq_domain *d, unsigned int irq,
irq_hw_number_t hwirq)
{
struct cplds *fpga = d->host_data;
irq_set_chip_and_handler(irq, &cplds_irq_chip, handle_level_irq);
irq_set_chip_data(irq, fpga);
return 0;
}
static const struct irq_domain_ops cplds_irq_domain_ops = {
.xlate = irq_domain_xlate_twocell,
.map = cplds_irq_domain_map,
};
static int cplds_resume(struct platform_device *pdev)
{
struct cplds *fpga = platform_get_drvdata(pdev);
writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
return 0;
}
static int cplds_probe(struct platform_device *pdev)
{
struct resource *res;
struct cplds *fpga;
int ret;
unsigned int base_irq = 0;
unsigned long irqflags = 0;
fpga = devm_kzalloc(&pdev->dev, sizeof(*fpga), GFP_KERNEL);
if (!fpga)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (res) {
fpga->irq = (unsigned int)res->start;
irqflags = res->flags;
}
if (!fpga->irq)
return -ENODEV;
base_irq = platform_get_irq(pdev, 1);
if (base_irq < 0)
base_irq = 0;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
fpga->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(fpga->base))
return PTR_ERR(fpga->base);
platform_set_drvdata(pdev, fpga);
writel(fpga->irq_mask, fpga->base + FPGA_IRQ_MASK_EN);
writel(0, fpga->base + FPGA_IRQ_SET_CLR);
ret = devm_request_irq(&pdev->dev, fpga->irq, cplds_irq_handler,
irqflags, dev_name(&pdev->dev), fpga);
if (ret == -ENOSYS)
return -EPROBE_DEFER;
if (ret) {
dev_err(&pdev->dev, "couldn't request main irq%d: %d\n",
fpga->irq, ret);
return ret;
}
irq_set_irq_wake(fpga->irq, 1);
fpga->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
CPLDS_NB_IRQ,
&cplds_irq_domain_ops, fpga);
if (!fpga->irqdomain)
return -ENODEV;
if (base_irq) {
ret = irq_create_strict_mappings(fpga->irqdomain, base_irq, 0,
CPLDS_NB_IRQ);
if (ret) {
dev_err(&pdev->dev, "couldn't create the irq mapping %d..%d\n",
base_irq, base_irq + CPLDS_NB_IRQ);
return ret;
}
}
return 0;
}
static int cplds_remove(struct platform_device *pdev)
{
struct cplds *fpga = platform_get_drvdata(pdev);
irq_set_chip_and_handler(fpga->irq, NULL, NULL);
return 0;
}
static const struct of_device_id cplds_id_table[] = {
{ .compatible = "intel,lubbock-cplds-irqs", },
{ .compatible = "intel,mainstone-cplds-irqs", },
{ }
};
MODULE_DEVICE_TABLE(of, cplds_id_table);
static struct platform_driver cplds_driver = {
.driver = {
.name = "pxa_cplds_irqs",
.of_match_table = of_match_ptr(cplds_id_table),
},
.probe = cplds_probe,
.remove = cplds_remove,
.resume = cplds_resume,
};
module_platform_driver(cplds_driver);
MODULE_DESCRIPTION("PXA Cplds interrupts driver");
MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
MODULE_LICENSE("GPL");
arch/arm/mach-rockchip/pm.c
View file @ 8f59ae06
......@@ -44,9 +44,11 @@ static void __iomem *rk3288_bootram_base;
static phys_addr_t rk3288_bootram_phy;
static struct regmap *pmu_regmap;
static struct regmap *grf_regmap;
static struct regmap *sgrf_regmap;
static u32 rk3288_pmu_pwr_mode_con;
static u32 rk3288_grf_soc_con0;
static u32 rk3288_sgrf_soc_con0;
static inline u32 rk3288_l2_config(void)
......@@ -70,11 +72,25 @@ static void rk3288_slp_mode_set(int level)
{
u32 mode_set, mode_set1;
regmap_read(grf_regmap, RK3288_GRF_SOC_CON0, &rk3288_grf_soc_con0);
regmap_read(sgrf_regmap, RK3288_SGRF_SOC_CON0, &rk3288_sgrf_soc_con0);
regmap_read(pmu_regmap, RK3288_PMU_PWRMODE_CON,
&rk3288_pmu_pwr_mode_con);
/*
* We need set this bit GRF_FORCE_JTAG here, for the debug module,
* otherwise, it may become inaccessible after resume.
* This creates a potential security issue, as the sdmmc pins may
* accept jtag data for a short time during resume if no card is
* inserted.
* But this is of course also true for the regular boot, before we
* turn of the jtag/sdmmc autodetect.
*/
regmap_write(grf_regmap, RK3288_GRF_SOC_CON0, GRF_FORCE_JTAG |
GRF_FORCE_JTAG_WRITE);
/*
* SGRF_FAST_BOOT_EN - system to boot from FAST_BOOT_ADDR
* PCLK_WDT_GATE - disable WDT during suspend.
......@@ -83,6 +99,13 @@ static void rk3288_slp_mode_set(int level)
SGRF_PCLK_WDT_GATE | SGRF_FAST_BOOT_EN
| SGRF_PCLK_WDT_GATE_WRITE | SGRF_FAST_BOOT_EN_WRITE);
/*
* The dapswjdp can not auto reset before resume, that cause it may
* access some illegal address during resume. Let's disable it before
* suspend, and the MASKROM will enable it back.
*/
regmap_write(sgrf_regmap, RK3288_SGRF_CPU_CON0, SGRF_DAPDEVICEEN_WRITE);
/* booting address of resuming system is from this register value */
regmap_write(sgrf_regmap, RK3288_SGRF_FAST_BOOT_ADDR,
rk3288_bootram_phy);
......@@ -128,6 +151,9 @@ static void rk3288_slp_mode_set_resume(void)
regmap_write(sgrf_regmap, RK3288_SGRF_SOC_CON0,
rk3288_sgrf_soc_con0 | SGRF_PCLK_WDT_GATE_WRITE
| SGRF_FAST_BOOT_EN_WRITE);
regmap_write(grf_regmap, RK3288_GRF_SOC_CON0, rk3288_grf_soc_con0 |
GRF_FORCE_JTAG_WRITE);
}
static int rockchip_lpmode_enter(unsigned long arg)
......@@ -186,6 +212,13 @@ static int rk3288_suspend_init(struct device_node *np)
return PTR_ERR(pmu_regmap);
}
grf_regmap = syscon_regmap_lookup_by_compatible(
"rockchip,rk3288-grf");
if (IS_ERR(grf_regmap)) {
pr_err("%s: could not find grf regmap\n", __func__);
return PTR_ERR(pmu_regmap);
}
sram_np = of_find_compatible_node(NULL, NULL,
"rockchip,rk3288-pmu-sram");
if (!sram_np) {
......
arch/arm/mach-rockchip/pm.h
View file @ 8f59ae06
......@@ -48,6 +48,10 @@ static inline void rockchip_suspend_init(void)
#define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44
#define RK3288_PMU_PWRMODE_CON1 0x90
#define RK3288_GRF_SOC_CON0 0x244
#define GRF_FORCE_JTAG BIT(12)
#define GRF_FORCE_JTAG_WRITE BIT(28)
#define RK3288_SGRF_SOC_CON0 (0x0000)
#define RK3288_SGRF_FAST_BOOT_ADDR (0x0120)
#define SGRF_PCLK_WDT_GATE BIT(6)
......@@ -55,6 +59,10 @@ static inline void rockchip_suspend_init(void)
#define SGRF_FAST_BOOT_EN BIT(8)
#define SGRF_FAST_BOOT_EN_WRITE BIT(24)
#define RK3288_SGRF_CPU_CON0 (0x40)
#define SGRF_DAPDEVICEEN BIT(0)
#define SGRF_DAPDEVICEEN_WRITE BIT(16)
#define RK3288_CRU_MODE_CON 0x50
#define RK3288_CRU_SEL0_CON 0x60
#define RK3288_CRU_SEL1_CON 0x64
......
arch/arm/mach-rockchip/rockchip.c
View file @ 8f59ae06
......@@ -30,11 +30,30 @@
#include "pm.h"
#define RK3288_GRF_SOC_CON0 0x244
#define RK3288_TIMER6_7_PHYS 0xff810000
static void __init rockchip_timer_init(void)
{
if (of_machine_is_compatible("rockchip,rk3288")) {
struct regmap *grf;
void __iomem *reg_base;
/*
* Most/all uboot versions for rk3288 don't enable timer7
* which is needed for the architected timer to work.
* So make sure it is running during early boot.
*/
reg_base = ioremap(RK3288_TIMER6_7_PHYS, SZ_16K);
if (reg_base) {
writel(0, reg_base + 0x30);
writel(0xffffffff, reg_base + 0x20);
writel(0xffffffff, reg_base + 0x24);
writel(1, reg_base + 0x30);
dsb();
iounmap(reg_base);
} else {
pr_err("rockchip: could not map timer7 registers\n");
}
/*
* Disable auto jtag/sdmmc switching that causes issues
......
drivers/bus/arm-cci.c
View file @ 8f59ae06
......@@ -660,7 +660,7 @@ validate_group(struct perf_event *event)
* Initialise the fake PMU. We only need to populate the
* used_mask for the purposes of validation.
*/
.used_mask = CPU_BITS_NONE,
.used_mask = { 0 },
};
if (!validate_event(event->pmu, &fake_pmu, leader))
......
drivers/bus/omap_l3_noc.c
View file @ 8f59ae06
/*
* OMAP L3 Interconnect error handling driver
*
* Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* Sricharan <r.sricharan@ti.com>
*
......@@ -233,7 +233,8 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3)
}
static const struct of_device_id l3_noc_match[] = {
{.compatible = "ti,omap4-l3-noc", .data = &omap_l3_data},
{.compatible = "ti,omap4-l3-noc", .data = &omap4_l3_data},
{.compatible = "ti,omap5-l3-noc", .data = &omap5_l3_data},
{.compatible = "ti,dra7-l3-noc", .data = &dra_l3_data},
{.compatible = "ti,am4372-l3-noc", .data = &am4372_l3_data},
{},
......
drivers/bus/omap_l3_noc.h
View file @ 8f59ae06
/*
* OMAP L3 Interconnect error handling driver header
*
* Copyright (C) 2011-2014 Texas Instruments Incorporated - http://www.ti.com/
* Copyright (C) 2011-2015 Texas Instruments Incorporated - http://www.ti.com/
* Santosh Shilimkar <santosh.shilimkar@ti.com>
* sricharan <r.sricharan@ti.com>
*
......@@ -175,16 +175,14 @@ static struct l3_flagmux_data omap_l3_flagmux_clk2 = {
};
static struct l3_target_data omap_l3_target_data_clk3[] = {
{0x0100, "EMUSS",},
{0x0300, "DEBUG SOURCE",},
{0x0, "HOST CLK3",},
static struct l3_target_data omap4_l3_target_data_clk3[] = {
{0x0100, "DEBUGSS",},
};
static struct l3_flagmux_data omap_l3_flagmux_clk3 = {
static struct l3_flagmux_data omap4_l3_flagmux_clk3 = {
.offset = 0x0200,
.l3_targ = omap_l3_target_data_clk3,
.num_targ_data = ARRAY_SIZE(omap_l3_target_data_clk3),
.l3_targ = omap4_l3_target_data_clk3,
.num_targ_data = ARRAY_SIZE(omap4_l3_target_data_clk3),
};
static struct l3_masters_data omap_l3_masters[] = {
......@@ -215,21 +213,49 @@ static struct l3_masters_data omap_l3_masters[] = {
{ 0x32, "USBHOSTFS"}
};
static struct l3_flagmux_data *omap_l3_flagmux[] = {
static struct l3_flagmux_data *omap4_l3_flagmux[] = {
&omap_l3_flagmux_clk1,
&omap_l3_flagmux_clk2,
&omap_l3_flagmux_clk3,
&omap4_l3_flagmux_clk3,
};
static const struct omap_l3 omap_l3_data = {
.l3_flagmux = omap_l3_flagmux,
.num_modules = ARRAY_SIZE(omap_l3_flagmux),
static const struct omap_l3 omap4_l3_data = {
.l3_flagmux = omap4_l3_flagmux,
.num_modules = ARRAY_SIZE(omap4_l3_flagmux),
.l3_masters = omap_l3_masters,
.num_masters = ARRAY_SIZE(omap_l3_masters),
/* The 6 MSBs of register field used to distinguish initiator */
.mst_addr_mask = 0xFC,
};
/* OMAP5 data */
static struct l3_target_data omap5_l3_target_data_clk3[] = {
{0x0100, "L3INSTR",},
{0x0300, "DEBUGSS",},
{0x0, "HOSTCLK3",},
};
static struct l3_flagmux_data omap5_l3_flagmux_clk3 = {
.offset = 0x0200,
.l3_targ = omap5_l3_target_data_clk3,
.num_targ_data = ARRAY_SIZE(omap5_l3_target_data_clk3),
};
static struct l3_flagmux_data *omap5_l3_flagmux[] = {
&omap_l3_flagmux_clk1,
&omap_l3_flagmux_clk2,
&omap5_l3_flagmux_clk3,
};
static const struct omap_l3 omap5_l3_data = {
.l3_flagmux = omap5_l3_flagmux,
.num_modules = ARRAY_SIZE(omap5_l3_flagmux),
.l3_masters = omap_l3_masters,
.num_masters = ARRAY_SIZE(omap_l3_masters),
/* The 6 MSBs of register field used to distinguish initiator */
.mst_addr_mask = 0x7E0,
};
/* DRA7 data */
static struct l3_target_data dra_l3_target_data_clk1[] = {
{0x2a00, "AES1",},
......@@ -274,7 +300,7 @@ static struct l3_flagmux_data dra_l3_flagmux_clk1 = {
static struct l3_target_data dra_l3_target_data_clk2[] = {
{0x0, "HOST CLK1",},
{0x0, "HOST CLK2",},
{0x800000, "HOST CLK2",},
{0xdead, L3_TARGET_NOT_SUPPORTED,},
{0x3400, "SHA2_2",},
{0x0900, "BB2D",},
......
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