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Commit 8fa894ae authored by Kai Germaschewski's avatar Kai Germaschewski
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ISDN/HiSax: Add B-Channel FIFO ops 

Preparing for un-inlining hscx_irq.c, we add operations needed
to access the B-Channel FIFO's, similar to what we already have
for the D-Channel.
parent 32610705
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Showing with 441 additions and 267 deletions
drivers/isdn/hisax/asuscom.c
View file @ 8fa894ae
......@@ -153,20 +153,34 @@ static struct dc_hw_ops ipac_dc_ops = {
};
static u8
ReadHSCX(struct IsdnCardState *cs, int hscx, u8 offset)
hscx_read(struct IsdnCardState *cs, int hscx, u8 offset)
{
return readreg(cs, cs->hw.asus.hscx, offset + (hscx ? 0x40 : 0));
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
hscx_write(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
{
writereg(cs, cs->hw.asus.hscx, offset + (hscx ? 0x40 : 0), value);
}
static void
hscx_read_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
readfifo(cs, cs->hw.asus.hscx, hscx ? 0x40 : 0, data, size);
}
static void
hscx_write_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
writefifo(cs, cs->hw.asus.hscx, hscx ? 0x40 : 0, data, size);
}
static struct bc_hw_ops hscx_ops = {
.read_reg = ReadHSCX,
.write_reg = WriteHSCX,
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
/*
......
drivers/isdn/hisax/avm_a1.c
View file @ 8fa894ae
......@@ -51,54 +51,66 @@ write_fifo(unsigned int adr, u8 * data, int size)
outsb(adr, data, size);
}
/* Interface functions */
static u8
ReadISAC(struct IsdnCardState *cs, u8 offset)
isac_read(struct IsdnCardState *cs, u8 offset)
{
return (readreg(cs->hw.avm.isac, offset));
return readreg(cs->hw.avm.isac, offset);
}
static void
WriteISAC(struct IsdnCardState *cs, u8 offset, u8 value)
isac_write(struct IsdnCardState *cs, u8 offset, u8 value)
{
writereg(cs->hw.avm.isac, offset, value);
}
static void
ReadISACfifo(struct IsdnCardState *cs, u8 * data, int size)
isac_read_fifo(struct IsdnCardState *cs, u8 * data, int size)
{
read_fifo(cs->hw.avm.isacfifo, data, size);
}
static void
WriteISACfifo(struct IsdnCardState *cs, u8 * data, int size)
isac_write_fifo(struct IsdnCardState *cs, u8 * data, int size)
{
write_fifo(cs->hw.avm.isacfifo, data, size);
}
static struct dc_hw_ops isac_ops = {
.read_reg = ReadISAC,
.write_reg = WriteISAC,
.read_fifo = ReadISACfifo,
.write_fifo = WriteISACfifo,
.read_reg = isac_read,
.write_reg = isac_write,
.read_fifo = isac_read_fifo,
.write_fifo = isac_write_fifo,
};
static u8
ReadHSCX(struct IsdnCardState *cs, int hscx, u8 offset)
hscx_read(struct IsdnCardState *cs, int hscx, u8 offset)
{
return (readreg(cs->hw.avm.hscx[hscx], offset));
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
hscx_write(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
{
writereg(cs->hw.avm.hscx[hscx], offset, value);
}
static void
hscx_read_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
read_fifo(cs->hw.avm.hscxfifo[hscx], data, size);
}
static void
hscx_write_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
write_fifo(cs->hw.avm.hscxfifo[hscx], data, size);
}
static struct bc_hw_ops hscx_ops = {
.read_reg = ReadHSCX,
.write_reg = WriteHSCX,
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
/*
......
drivers/isdn/hisax/avm_a1p.c
View file @ 8fa894ae
......@@ -137,43 +137,45 @@ static struct dc_hw_ops isac_ops = {
.write_fifo = isac_write_fifo,
};
static inline u8
ReadHSCX(struct IsdnCardState *cs, int hscx, u8 adr)
static u8
hscx_read(struct IsdnCardState *cs, int hscx, u8 adr)
{
return readreg(cs, HSCX_REG_OFFSET + hscx*HSCX_CH_DIFF, adr);
}
static inline void
WriteHSCX(struct IsdnCardState *cs, int hscx, u8 adr, u8 value)
static void
hscx_write(struct IsdnCardState *cs, int hscx, u8 adr, u8 value)
{
writereg(cs, HSCX_REG_OFFSET + hscx*HSCX_CH_DIFF, adr, value);
}
static inline void
ReadHSCXfifo(struct IsdnCardState *cs, int hscx, u8 * data, int size)
static void
hscx_read_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
return readfifo(cs, HSCX_FIFO_OFFSET + hscx*HSCX_CH_DIFF, data, size);
}
static inline void
WriteHSCXfifo(struct IsdnCardState *cs, int hscx, u8 * data, int size)
static void
hscx_write_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
writefifo(cs, HSCX_FIFO_OFFSET + hscx*HSCX_CH_DIFF, data, size);
}
static struct bc_hw_ops hscx_ops = {
.read_reg = ReadHSCX,
.write_reg = WriteHSCX,
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) ReadHSCX(cs, nr, reg)
#define WRITEHSCX(cs, nr, reg, data) WriteHSCX(cs, nr, reg, data)
#define READHSCXFIFO(cs, nr, ptr, cnt) ReadHSCXfifo(cs, nr, ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) WriteHSCXfifo(cs, nr, ptr, cnt)
#define READHSCX(cs, nr, reg) hscx_read(cs, nr, reg)
#define WRITEHSCX(cs, nr, reg, data) hscx_write(cs, nr, reg, data)
#define READHSCXFIFO(cs, nr, ptr, cnt) hscx_read_fifo(cs, nr, ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) hscx_write_fifo(cs, nr, ptr, cnt)
#include "hscx_irq.c"
......@@ -188,7 +190,7 @@ avm_a1p_interrupt(int intno, void *dev_id, struct pt_regs *regs)
if (cs->debug & L1_DEB_INTSTAT)
debugl1(cs, "avm IntStatus %x", sval);
if (sval & ASL0_R_HSCX) {
val = ReadHSCX(cs, 1, HSCX_ISTA);
val = hscx_read(cs, 1, HSCX_ISTA);
if (val)
hscx_int_main(cs, val);
}
......@@ -198,12 +200,12 @@ avm_a1p_interrupt(int intno, void *dev_id, struct pt_regs *regs)
isac_interrupt(cs, val);
}
}
WriteHSCX(cs, 0, HSCX_MASK, 0xff);
WriteHSCX(cs, 1, HSCX_MASK, 0xff);
isac_write(cs, ISAC_MASK, 0xff);
isac_write(cs, ISAC_MASK, 0x00);
WriteHSCX(cs, 0, HSCX_MASK, 0x00);
WriteHSCX(cs, 1, HSCX_MASK, 0x00);
hscx_write(cs, 0, HSCX_MASK, 0xFF);
hscx_write(cs, 1, HSCX_MASK, 0xFF);
isac_write(cs, ISAC_MASK, 0xFF);
isac_write(cs, ISAC_MASK, 0x0);
hscx_write(cs, 0, HSCX_MASK, 0x0);
hscx_write(cs, 1, HSCX_MASK, 0x0);
spin_unlock(&cs->lock);
}
......
drivers/isdn/hisax/bkm_a8.c
View file @ 8fa894ae
......@@ -122,20 +122,34 @@ static struct dc_hw_ops ipac_dc_ops = {
};
static u8
ReadHSCX(struct IsdnCardState *cs, int hscx, u8 offset)
hscx_read(struct IsdnCardState *cs, int hscx, u8 offset)
{
return readreg(cs, offset + (hscx ? 0x40 : 0));
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
hscx_write(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
{
writereg(cs, offset + (hscx ? 0x40 : 0), value);
}
static void
hscx_read_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
readfifo(cs, hscx ? 0x40 : 0, data, size);
}
static void
hscx_write_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
writefifo(cs, hscx ? 0x40 : 0, data, size);
}
static struct bc_hw_ops hscx_ops = {
.read_reg = ReadHSCX,
.write_reg = WriteHSCX,
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
/* Set the specific ipac to active */
......
drivers/isdn/hisax/diva.c
View file @ 8fa894ae
......@@ -204,22 +204,36 @@ static struct dc_hw_ops ipac_dc_ops = {
};
static u8
ReadHSCX(struct IsdnCardState *cs, int hscx, u8 offset)
hscx_read(struct IsdnCardState *cs, int hscx, u8 offset)
{
return(readreg(cs->hw.diva.hscx_adr,
cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0)));
return readreg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx,
offset + (hscx ? 0x40 : 0));
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
hscx_write(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
{
writereg(cs->hw.diva.hscx_adr,
cs->hw.diva.hscx, offset + (hscx ? 0x40 : 0), value);
writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx,
offset + (hscx ? 0x40 : 0), value);
}
static void
hscx_read_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
readfifo(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, hscx ? 0x40 : 0, data, size);
}
static void
hscx_write_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
writefifo(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, hscx ? 0x40 : 0, data, size);
}
static struct bc_hw_ops hscx_ops = {
.read_reg = ReadHSCX,
.write_reg = WriteHSCX,
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
static u8
......@@ -256,20 +270,20 @@ static struct dc_hw_ops mem_ipac_dc_ops = {
};
static u8
MemReadHSCX(struct IsdnCardState *cs, int hscx, u8 offset)
mem_hscx_read(struct IsdnCardState *cs, int hscx, u8 offset)
{
return(memreadreg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0)));
return memreadreg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0));
}
static void
MemWriteHSCX(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
mem_hscx_write(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
{
memwritereg(cs->hw.diva.cfg_reg, offset + (hscx ? 0x40 : 0), value);
}
static struct bc_hw_ops mem_hscx_ops = {
.read_reg = MemReadHSCX,
.write_reg = MemWriteHSCX,
.read_reg = mem_hscx_read,
.write_reg = mem_hscx_write,
};
/* IO-Functions for IPACX type cards */
......@@ -307,22 +321,22 @@ static struct dc_hw_ops ipacx_dc_ops = {
};
static u8
MemReadHSCX_IPACX(struct IsdnCardState *cs, int hscx, u8 offset)
ipacx_bc_read(struct IsdnCardState *cs, int hscx, u8 offset)
{
return(memreadreg(cs->hw.diva.cfg_reg, offset +
(hscx ? IPACX_OFF_B2 : IPACX_OFF_B1)));
return memreadreg(cs->hw.diva.cfg_reg, offset +
(hscx ? IPACX_OFF_B2 : IPACX_OFF_B1));
}
static void
MemWriteHSCX_IPACX(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
ipacx_bc_write(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
{
memwritereg(cs->hw.diva.cfg_reg, offset +
(hscx ? IPACX_OFF_B2 : IPACX_OFF_B1), value);
}
static struct bc_hw_ops mem_ipacx_bc_ops = {
.read_reg = MemReadHSCX_IPACX,
.write_reg = MemWriteHSCX_IPACX,
static struct bc_hw_ops ipacx_bc_ops = {
.read_reg = ipacx_bc_read,
.write_reg = ipacx_bc_write,
};
/*
......@@ -422,7 +436,7 @@ MemwaitforCEC(struct IsdnCardState *cs, int hscx)
{
int to = 50;
while ((MemReadHSCX(cs, hscx, HSCX_STAR) & 0x04) && to) {
while ((mem_hscx_read(cs, hscx, HSCX_STAR) & 0x04) && to) {
udelay(1);
to--;
}
......@@ -436,7 +450,7 @@ MemwaitforXFW(struct IsdnCardState *cs, int hscx)
{
int to = 50;
while ((!(MemReadHSCX(cs, hscx, HSCX_STAR) & 0x44) == 0x40) && to) {
while ((!(mem_hscx_read(cs, hscx, HSCX_STAR) & 0x44) == 0x40) && to) {
udelay(1);
to--;
}
......@@ -451,7 +465,7 @@ MemWriteHSCXCMDR(struct IsdnCardState *cs, int hscx, u8 data)
spin_lock_irqsave(&diva_lock, flags);
MemwaitforCEC(cs, hscx);
MemWriteHSCX(cs, hscx, HSCX_CMDR, data);
mem_hscx_write(cs, hscx, HSCX_CMDR, data);
spin_unlock_irqrestore(&diva_lock, flags);
}
......@@ -524,7 +538,7 @@ Memhscx_interrupt(struct IsdnCardState *cs, u8 val, u8 hscx)
return;
if (val & 0x80) { /* RME */
r = MemReadHSCX(cs, hscx, HSCX_RSTA);
r = mem_hscx_read(cs, hscx, HSCX_RSTA);
if ((r & 0xf0) != 0xa0) {
if (!(r & 0x80))
if (cs->debug & L1_DEB_WARN)
......@@ -538,7 +552,7 @@ Memhscx_interrupt(struct IsdnCardState *cs, u8 val, u8 hscx)
debugl1(cs, "HSCX CRC error");
MemWriteHSCXCMDR(cs, hscx, 0x80);
} else {
count = MemReadHSCX(cs, hscx, HSCX_RBCL) & (
count = mem_hscx_read(cs, hscx, HSCX_RBCL) & (
test_bit(HW_IPAC, &cs->HW_Flags)? 0x3f: 0x1f);
if (count == 0)
count = fifo_size;
......@@ -591,7 +605,7 @@ Memhscx_int_main(struct IsdnCardState *cs, u8 val)
if (val & 0x01) { // EXB
bcs = cs->bcs + 1;
exval = MemReadHSCX(cs, 1, HSCX_EXIR);
exval = mem_hscx_read(cs, 1, HSCX_EXIR);
if (exval & 0x40) {
if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "HSCX B EXIR %x", exval);
......@@ -605,7 +619,7 @@ Memhscx_int_main(struct IsdnCardState *cs, u8 val)
}
if (val & 0x02) { // EXA
bcs = cs->bcs;
exval = MemReadHSCX(cs, 0, HSCX_EXIR);
exval = mem_hscx_read(cs, 0, HSCX_EXIR);
if (exval & 0x40) {
if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "HSCX A EXIR %x", exval);
......@@ -613,7 +627,7 @@ Memhscx_int_main(struct IsdnCardState *cs, u8 val)
}
}
if (val & 0x04) { // ICA
exval = MemReadHSCX(cs, 0, HSCX_ISTA);
exval = mem_hscx_read(cs, 0, HSCX_ISTA);
if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "HSCX A interrupt %x", exval);
Memhscx_interrupt(cs, exval, 0);
......@@ -1123,7 +1137,7 @@ setup_diva(struct IsdnCard *card)
printk(KERN_INFO "Diva: IPAC version %x\n", val);
} else if (cs->subtyp == DIVA_IPACX_PCI) {
cs->dc_hw_ops = &ipacx_dc_ops;
cs->bc_hw_ops = &mem_ipacx_bc_ops;
cs->bc_hw_ops = &ipacx_bc_ops;
cs->BC_Send_Data = &ipacx_fill_fifo;
cs->irq_func = &diva_irq_ipacx_pci;
printk(KERN_INFO "Diva: IPACX Design Id: %x\n",
......
drivers/isdn/hisax/elsa.c
View file @ 8fa894ae
......@@ -251,33 +251,47 @@ static struct dc_hw_ops ipac_dc_ops = {
};
static u8
ReadHSCX(struct IsdnCardState *cs, int hscx, u8 offset)
hscx_read(struct IsdnCardState *cs, int hscx, u8 offset)
{
return readreg(cs, cs->hw.elsa.hscx, offset + (hscx ? 0x40 : 0));
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
hscx_write(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
{
writereg(cs, cs->hw.elsa.hscx, offset + (hscx ? 0x40 : 0), value);
}
static void
hscx_read_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
writefifo(cs, cs->hw.elsa.hscx, hscx ? 0x40 : 0, data, size);
}
static void
hscx_write_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
writefifo(cs, cs->hw.elsa.hscx, hscx ? 0x40 : 0, data, size);
}
static struct bc_hw_ops hscx_ops = {
.read_reg = ReadHSCX,
.write_reg = WriteHSCX,
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
static inline u8
readitac(struct IsdnCardState *cs, u8 off)
{
register u8 ret;
u8 ret;
unsigned long flags;
spin_lock_irqsave(&elsa_lock, flags);
byteout(cs->hw.elsa.ale, off);
ret = bytein(cs->hw.elsa.itac);
spin_unlock_irqrestore(&elsa_lock, flags);
return (ret);
return ret;
}
static inline void
......
drivers/isdn/hisax/gazel.c
View file @ 8fa894ae
......@@ -180,84 +180,86 @@ static struct dc_hw_ops isac_ops = {
.write_fifo = isac_write_fifo,
};
static void
ReadHSCXfifo(struct IsdnCardState *cs, int hscx, u8 * data, int size)
static u8
hscx_read(struct IsdnCardState *cs, int hscx, u8 offset)
{
u_short off2 = offset;
switch (cs->subtyp) {
case R647:
off2 = ((off2 << 8 & 0xf000) | (off2 & 0xf));
case R685:
read_fifo(cs->hw.gazel.hscxfifo[hscx], data, size);
break;
return readreg(cs->hw.gazel.hscx[hscx], off2);
case R753:
case R742:
read_fifo_ipac(cs, hscx * 0x40, data, size);
break;
return readreg_ipac(cs, hscx * 0x40 + off2);
}
return 0;
}
static void
WriteHSCXfifo(struct IsdnCardState *cs, int hscx, u8 * data, int size)
hscx_write(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
{
u_short off2 = offset;
switch (cs->subtyp) {
case R647:
off2 = ((off2 << 8 & 0xf000) | (off2 & 0xf));
case R685:
write_fifo(cs->hw.gazel.hscxfifo[hscx], data, size);
writereg(cs->hw.gazel.hscx[hscx], off2, value);
break;
case R753:
case R742:
write_fifo_ipac(cs, hscx * 0x40, data, size);
writereg_ipac(cs, hscx * 0x40 + off2, value);
break;
}
}
static u8
ReadHSCX(struct IsdnCardState *cs, int hscx, u8 offset)
static void
hscx_read_fifo(struct IsdnCardState *cs, int hscx, u8 * data, int size)
{
u_short off2 = offset;
switch (cs->subtyp) {
case R647:
off2 = ((off2 << 8 & 0xf000) | (off2 & 0xf));
case R685:
return readreg(cs->hw.gazel.hscx[hscx], off2);
read_fifo(cs->hw.gazel.hscxfifo[hscx], data, size);
break;
case R753:
case R742:
return readreg_ipac(cs, hscx * 0x40 + off2);
read_fifo_ipac(cs, hscx * 0x40, data, size);
break;
}
return 0;
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
hscx_write_fifo(struct IsdnCardState *cs, int hscx, u8 * data, int size)
{
u_short off2 = offset;
switch (cs->subtyp) {
case R647:
off2 = ((off2 << 8 & 0xf000) | (off2 & 0xf));
case R685:
writereg(cs->hw.gazel.hscx[hscx], off2, value);
write_fifo(cs->hw.gazel.hscxfifo[hscx], data, size);
break;
case R753:
case R742:
writereg_ipac(cs, hscx * 0x40 + off2, value);
write_fifo_ipac(cs, hscx * 0x40, data, size);
break;
}
}
static struct bc_hw_ops hscx_ops = {
.read_reg = ReadHSCX,
.write_reg = WriteHSCX,
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) ReadHSCX(cs, nr, reg)
#define WRITEHSCX(cs, nr, reg, data) WriteHSCX(cs, nr, reg, data)
#define READHSCXFIFO(cs, nr, ptr, cnt) ReadHSCXfifo(cs, nr, ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) WriteHSCXfifo(cs, nr, ptr, cnt)
#define READHSCX(cs, nr, reg) hscx_read(cs, nr, reg)
#define WRITEHSCX(cs, nr, reg, data) hscx_write(cs, nr, reg, data)
#define READHSCXFIFO(cs, nr, ptr, cnt) hscx_read_fifo(cs, nr, ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) hscx_write_fifo(cs, nr, ptr, cnt)
#include "hscx_irq.c"
......@@ -271,7 +273,7 @@ gazel_interrupt(int intno, void *dev_id, struct pt_regs *regs)
spin_lock(&cs->lock);
do {
valhscx = ReadHSCX(cs, 1, HSCX_ISTA);
valhscx = hscx_read(cs, 1, HSCX_ISTA);
if (valhscx)
hscx_int_main(cs, valhscx);
valisac = isac_read(cs, ISAC_ISTA);
......@@ -280,12 +282,12 @@ gazel_interrupt(int intno, void *dev_id, struct pt_regs *regs)
count++;
} while ((valhscx || valisac) && (count < MAXCOUNT));
WriteHSCX(cs, 0, HSCX_MASK, 0xFF);
WriteHSCX(cs, 1, HSCX_MASK, 0xFF);
hscx_write(cs, 0, HSCX_MASK, 0xFF);
hscx_write(cs, 1, HSCX_MASK, 0xFF);
isac_write(cs, ISAC_MASK, 0xFF);
isac_write(cs, ISAC_MASK, 0x0);
WriteHSCX(cs, 0, HSCX_MASK, 0x0);
WriteHSCX(cs, 1, HSCX_MASK, 0x0);
hscx_write(cs, 0, HSCX_MASK, 0x0);
hscx_write(cs, 1, HSCX_MASK, 0x0);
spin_unlock(&cs->lock);
}
......@@ -304,7 +306,7 @@ gazel_interrupt_ipac(int intno, void *dev_id, struct pt_regs *regs)
ista = readreg_ipac(cs, IPAC_ISTA);
do {
if (ista & 0x0f) {
val = ReadHSCX(cs, 1, HSCX_ISTA);
val = hscx_read(cs, 1, HSCX_ISTA);
if (ista & 0x01)
val |= 0x01;
if (ista & 0x04)
......
drivers/isdn/hisax/hisax.h
View file @ 8fa894ae
......@@ -351,8 +351,10 @@ struct l3_process {
struct IsdnCardState;
struct bc_hw_ops {
u8 (*read_reg) (struct IsdnCardState *, int, u8);
void (*write_reg) (struct IsdnCardState *, int, u8, u8);
u8 (*read_reg) (struct IsdnCardState *, int, u8);
void (*write_reg) (struct IsdnCardState *, int, u8, u8);
void (*read_fifo) (struct IsdnCardState *, int, u8 *, int);
void (*write_fifo) (struct IsdnCardState *, int, u8 *, int);
};
struct hscx_hw {
......
drivers/isdn/hisax/hscx_irq.c
View file @ 8fa894ae
......@@ -41,7 +41,7 @@ waitforXFW(struct IsdnCardState *cs, int hscx)
}
static inline void
WriteHSCXCMDR(struct IsdnCardState *cs, int hscx, u8 data)
hscx_writeCMDR(struct IsdnCardState *cs, int hscx, u8 data)
{
waitforCEC(cs, hscx);
WRITEHSCX(cs, hscx, HSCX_CMDR, data);
......@@ -60,14 +60,14 @@ hscx_empty_fifo(struct BCState *bcs, int count)
if (bcs->hw.hscx.rcvidx + count > HSCX_BUFMAX) {
if (cs->debug & L1_DEB_WARN)
debugl1(cs, "hscx_empty_fifo: incoming packet too large");
WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80);
hscx_writeCMDR(cs, bcs->hw.hscx.hscx, 0x80);
bcs->hw.hscx.rcvidx = 0;
return;
}
ptr = bcs->hw.hscx.rcvbuf + bcs->hw.hscx.rcvidx;
bcs->hw.hscx.rcvidx += count;
READHSCXFIFO(cs, bcs->hw.hscx.hscx, ptr, count);
WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, 0x80);
hscx_writeCMDR(cs, bcs->hw.hscx.hscx, 0x80);
if (cs->debug & L1_DEB_HSCX_FIFO) {
char *t = bcs->blog;
......@@ -107,7 +107,7 @@ hscx_fill_fifo(struct BCState *bcs)
bcs->tx_cnt -= count;
bcs->count += count;
WRITEHSCXFIFO(cs, bcs->hw.hscx.hscx, ptr, count);
WriteHSCXCMDR(cs, bcs->hw.hscx.hscx, more ? 0x8 : 0xa);
hscx_writeCMDR(cs, bcs->hw.hscx.hscx, more ? 0x8 : 0xa);
if (cs->debug & L1_DEB_HSCX_FIFO) {
char *t = bcs->blog;
......@@ -155,7 +155,7 @@ hscx_interrupt(struct IsdnCardState *cs, u8 val, u8 hscx)
bcs->err_crc++;
#endif
}
WriteHSCXCMDR(cs, hscx, 0x80);
hscx_writeCMDR(cs, hscx, 0x80);
} else {
count = READHSCX(cs, hscx, HSCX_RBCL) & (
test_bit(HW_IPAC, &cs->HW_Flags)? 0x3f: 0x1f);
......@@ -198,7 +198,7 @@ hscx_interrupt(struct IsdnCardState *cs, u8 val, u8 hscx)
static void
reset_xmit(struct BCState *bcs)
{
WriteHSCXCMDR(bcs->cs, bcs->hw.hscx.hscx, 0x01);
hscx_writeCMDR(bcs->cs, bcs->hw.hscx.hscx, 0x01);
}
static inline void
......
drivers/isdn/hisax/ix1_micro.c
View file @ 8fa894ae
......@@ -119,20 +119,34 @@ static struct dc_hw_ops isac_ops = {
};
static u8
ReadHSCX(struct IsdnCardState *cs, int hscx, u8 offset)
hscx_read(struct IsdnCardState *cs, int hscx, u8 offset)
{
return readreg(cs, cs->hw.ix1.hscx, offset + (hscx ? 0x40 : 0));
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
hscx_write(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
{
writereg(cs, cs->hw.ix1.hscx, offset + (hscx ? 0x40 : 0), value);
}
static void
hscx_read_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
readfifo(cs, cs->hw.ix1.hscx, hscx ? 0x40 : 0, data, size);
}
static void
hscx_write_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
writefifo(cs, cs->hw.ix1.hscx, hscx ? 0x40 : 0, data, size);
}
static struct bc_hw_ops hscx_ops = {
.read_reg = ReadHSCX,
.write_reg = WriteHSCX,
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
#define READHSCX(cs, nr, reg) readreg(cs, \
......
drivers/isdn/hisax/mic.c
View file @ 8fa894ae
......@@ -110,22 +110,36 @@ static struct dc_hw_ops isac_ops = {
};
static u8
ReadHSCX(struct IsdnCardState *cs, int hscx, u8 offset)
hscx_read(struct IsdnCardState *cs, int hscx, u8 offset)
{
return readreg(cs, cs->hw.mic.hscx, offset + (hscx ? 0x40 : 0));
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
hscx_write(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
{
writereg(cs, cs->hw.mic.hscx, offset + (hscx ? 0x40 : 0), value);
}
static void
hscx_read_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
readfifo(cs, cs->hw.mic.hscx, hscx ? 0x40 : 0, data, size);
}
static void
hscx_write_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
writefifo(cs, cs->hw.mic.hscx, hscx ? 0x40 : 0, data, size);
}
static struct bc_hw_ops hscx_ops = {
.read_reg = ReadHSCX,
.write_reg = WriteHSCX,
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
/*
* fast interrupt HSCX stuff goes here
*/
......
drivers/isdn/hisax/niccy.c
View file @ 8fa894ae
......@@ -125,24 +125,40 @@ static struct dc_hw_ops isac_ops = {
};
static u8
ReadHSCX(struct IsdnCardState *cs, int hscx, u8 offset)
hscx_read(struct IsdnCardState *cs, int hscx, u8 offset)
{
return (readreg(cs->hw.niccy.hscx_ale,
cs->hw.niccy.hscx, offset + (hscx ? 0x40 : 0)));
return readreg(cs->hw.niccy.hscx_ale,
cs->hw.niccy.hscx, offset + (hscx ? 0x40 : 0));
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
hscx_write(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
{
writereg(cs->hw.niccy.hscx_ale,
cs->hw.niccy.hscx, offset + (hscx ? 0x40 : 0), value);
}
static void
hscx_read_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
readfifo(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx,
hscx ? 0x40 : 0, data, size);
}
static void
hscx_write_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
writefifo(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx,
hscx ? 0x40 : 0, data, size);
}
static struct bc_hw_ops hscx_ops = {
.read_reg = ReadHSCX,
.write_reg = WriteHSCX,
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
#define READHSCX(cs, nr, reg) readreg(cs->hw.niccy.hscx_ale, \
cs->hw.niccy.hscx, reg + (nr ? 0x40 : 0))
#define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.niccy.hscx_ale, \
......
drivers/isdn/hisax/s0box.c
View file @ 8fa894ae
......@@ -136,22 +136,36 @@ static struct dc_hw_ops isac_ops = {
};
static u8
ReadHSCX(struct IsdnCardState *cs, int hscx, u8 offset)
hscx_read(struct IsdnCardState *cs, int hscx, u8 offset)
{
return readreg(cs, cs->hw.teles3.hscx[hscx], offset);
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
hscx_write(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
{
writereg(cs, cs->hw.teles3.hscx[hscx], offset, value);
}
static void
hscx_read_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
read_fifo(cs, cs->hw.teles3.hscxfifo[hscx], data, size);
}
static void
hscx_write_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
write_fifo(cs, cs->hw.teles3.hscxfifo[hscx], data, size);
}
static struct bc_hw_ops hscx_ops = {
.read_reg = ReadHSCX,
.write_reg = WriteHSCX,
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
/*
* fast interrupt HSCX stuff goes here
*/
......
drivers/isdn/hisax/saphir.c
View file @ 8fa894ae
......@@ -110,22 +110,36 @@ static struct dc_hw_ops isac_ops = {
};
static u8
ReadHSCX(struct IsdnCardState *cs, int hscx, u8 offset)
hscx_read(struct IsdnCardState *cs, int hscx, u8 offset)
{
return readreg(cs, cs->hw.saphir.hscx, offset + (hscx ? 0x40 : 0));
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
hscx_write(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
{
writereg(cs, cs->hw.saphir.hscx, offset + (hscx ? 0x40 : 0), value);
}
static void
hscx_read_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
readfifo(cs, cs->hw.saphir.hscx, hscx ? 0x40 : 0, data, size);
}
static void
hscx_write_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
writefifo(cs, cs->hw.saphir.hscx, hscx ? 0x40 : 0, data, size);
}
static struct bc_hw_ops hscx_ops = {
.read_reg = ReadHSCX,
.write_reg = WriteHSCX,
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
#define READHSCX(cs, nr, reg) readreg(cs, \
cs->hw.saphir.hscx, reg + (nr ? 0x40 : 0))
#define WRITEHSCX(cs, nr, reg, data) writereg(cs, \
......
drivers/isdn/hisax/sedlbauer.c
View file @ 8fa894ae
......@@ -228,20 +228,34 @@ static struct dc_hw_ops ipac_dc_ops = {
};
static u8
ReadHSCX(struct IsdnCardState *cs, int hscx, u8 offset)
hscx_read(struct IsdnCardState *cs, int hscx, u8 offset)
{
return readreg(cs, cs->hw.sedl.hscx, offset + (hscx ? 0x40 : 0));
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
hscx_write(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
{
writereg(cs, cs->hw.sedl.hscx, offset + (hscx ? 0x40 : 0), value);
}
static void
hscx_read_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
readfifo(cs, cs->hw.sedl.hscx, hscx ? 0x40 : 0, data, size);
}
static void
hscx_write_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
writefifo(cs, cs->hw.sedl.hscx, hscx ? 0x40 : 0, data, size);
}
static struct bc_hw_ops hscx_ops = {
.read_reg = ReadHSCX,
.write_reg = WriteHSCX,
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
/* ISAR access routines
......@@ -251,30 +265,32 @@ static struct bc_hw_ops hscx_ops = {
*/
static u8
ReadISAR(struct IsdnCardState *cs, int mode, u8 offset)
isar_read(struct IsdnCardState *cs, int mode, u8 offset)
{
if (mode == 0)
return readreg(cs, cs->hw.sedl.hscx, offset);
else if (mode == 1)
if (mode == 1)
byteout(cs->hw.sedl.adr, offset);
return(bytein(cs->hw.sedl.hscx));
return bytein(cs->hw.sedl.hscx);
}
static void
WriteISAR(struct IsdnCardState *cs, int mode, u8 offset, u8 value)
isar_write(struct IsdnCardState *cs, int mode, u8 offset, u8 value)
{
if (mode == 0)
writereg(cs, cs->hw.sedl.hscx, offset, value);
else {
if (mode == 1)
byteout(cs->hw.sedl.adr, offset);
byteout(cs->hw.sedl.hscx, value);
}
return writereg(cs, cs->hw.sedl.hscx, offset, value);
if (mode == 1)
byteout(cs->hw.sedl.adr, offset);
byteout(cs->hw.sedl.hscx, value);
}
static struct bc_hw_ops isar_ops = {
.read_reg = ReadISAR,
.write_reg = WriteISAR,
.read_reg = isar_read,
.write_reg = isar_write,
};
/*
......
drivers/isdn/hisax/sportster.c
View file @ 8fa894ae
......@@ -81,20 +81,34 @@ static struct dc_hw_ops isac_ops = {
};
static u8
ReadHSCX(struct IsdnCardState *cs, int hscx, u8 offset)
hscx_read(struct IsdnCardState *cs, int hscx, u8 offset)
{
return (bytein(calc_off(cs->hw.spt.hscx[hscx], offset)));
return bytein(calc_off(cs->hw.spt.hscx[hscx], offset));
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
hscx_write(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
{
byteout(calc_off(cs->hw.spt.hscx[hscx], offset), value);
}
static void
hscx_read_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
read_fifo(cs->hw.spt.hscx[hscx], data, size);
}
static void
hscx_write_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
write_fifo(cs->hw.spt.hscx[hscx], data, size);
}
static struct bc_hw_ops hscx_ops = {
.read_reg = ReadHSCX,
.write_reg = WriteHSCX,
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
/*
......
drivers/isdn/hisax/teles0.c
View file @ 8fa894ae
......@@ -70,64 +70,54 @@ static struct dc_hw_ops isac_ops = {
.write_fifo = isac_write_fifo,
};
static inline u8
readhscx(unsigned long adr, int hscx, u8 off)
static u8
hscx_read(struct IsdnCardState *cs, int hscx, u8 off)
{
return readb(adr + (hscx ? 0x1c0 : 0x180) +
return readb(cs->hw.teles0.membase + (hscx ? 0x1c0 : 0x180) +
((off & 1) ? 0x1ff : 0) + off);
}
static inline void
writehscx(unsigned long adr, int hscx, u8 off, u8 data)
static void
hscx_write(struct IsdnCardState *cs, int hscx, u8 off, u8 data)
{
writeb(data, adr + (hscx ? 0x1c0 : 0x180) +
writeb(data, cs->hw.teles0.membase + (hscx ? 0x1c0 : 0x180) +
((off & 1) ? 0x1ff : 0) + off); mb();
}
static inline void
read_fifo_hscx(unsigned long adr, int hscx, u8 * data, int size)
static void
hscx_read_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
register int i;
register u8 *ad = (u8 *) (adr + (hscx ? 0x1c0 : 0x180));
int i;
unsigned long ad = cs->hw.teles0.membase + (hscx ? 0x1c0 : 0x180);
for (i = 0; i < size; i++)
data[i] = readb(ad);
}
static inline void
write_fifo_hscx(unsigned long adr, int hscx, u8 * data, int size)
static void
hscx_write_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
int i;
register u8 *ad = (u8 *) (adr + (hscx ? 0x1c0 : 0x180));
unsigned long ad = cs->hw.teles0.membase + (hscx ? 0x1c0 : 0x180);
for (i = 0; i < size; i++) {
writeb(data[i], ad); mb();
writeb(data[i], ad);
}
}
static u8
ReadHSCX(struct IsdnCardState *cs, int hscx, u8 offset)
{
return (readhscx(cs->hw.teles0.membase, hscx, offset));
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
{
writehscx(cs->hw.teles0.membase, hscx, offset, value);
}
static struct bc_hw_ops hscx_ops = {
.read_reg = ReadHSCX,
.write_reg = WriteHSCX,
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg)
#define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data)
#define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
#define READHSCX(cs, nr, reg) hscx_read(cs, nr, reg)
#define WRITEHSCX(cs, nr, reg, data) hscx_write(cs, nr, reg, data)
#define READHSCXFIFO(cs, nr, ptr, cnt) hscx_read_fifo(cs, nr, ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) hscx_write_fifo(cs, nr, ptr, cnt)
#include "hscx_irq.c"
......@@ -139,7 +129,7 @@ teles0_interrupt(int intno, void *dev_id, struct pt_regs *regs)
int count = 0;
spin_lock(&cs->lock);
val = readhscx(cs->hw.teles0.membase, 1, HSCX_ISTA);
val = hscx_read(cs, 1, HSCX_ISTA);
Start_HSCX:
if (val)
hscx_int_main(cs, val);
......@@ -148,7 +138,7 @@ teles0_interrupt(int intno, void *dev_id, struct pt_regs *regs)
if (val)
isac_interrupt(cs, val);
count++;
val = readhscx(cs->hw.teles0.membase, 1, HSCX_ISTA);
val = hscx_read(cs, 1, HSCX_ISTA);
if (val && count < 5) {
if (cs->debug & L1_DEB_HSCX)
debugl1(cs, "HSCX IntStat after IntRoutine");
......@@ -160,12 +150,12 @@ teles0_interrupt(int intno, void *dev_id, struct pt_regs *regs)
debugl1(cs, "ISAC IntStat after IntRoutine");
goto Start_ISAC;
}
writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0xFF);
writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0xFF);
hscx_write(cs, 0, HSCX_MASK, 0xFF);
hscx_write(cs, 1, HSCX_MASK, 0xFF);
isac_write(cs, ISAC_MASK, 0xFF);
isac_write(cs, ISAC_MASK, 0x0);
writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0x0);
writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0x0);
hscx_write(cs, 0, HSCX_MASK, 0x0);
hscx_write(cs, 1, HSCX_MASK, 0x0);
spin_unlock(&cs->lock);
}
......
drivers/isdn/hisax/teles3.c
View file @ 8fa894ae
......@@ -83,20 +83,34 @@ static struct dc_hw_ops isac_ops = {
};
static u8
ReadHSCX(struct IsdnCardState *cs, int hscx, u8 offset)
hscx_read(struct IsdnCardState *cs, int hscx, u8 offset)
{
return (readreg(cs->hw.teles3.hscx[hscx], offset));
return readreg(cs->hw.teles3.hscx[hscx], offset);
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
hscx_write(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
{
writereg(cs->hw.teles3.hscx[hscx], offset, value);
}
static void
hscx_read_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
read_fifo(cs->hw.teles3.hscxfifo[hscx], data, size);
}
static void
hscx_write_fifo(struct IsdnCardState *cs, int hscx, u8 *data, int size)
{
write_fifo(cs->hw.teles3.hscxfifo[hscx], data, size);
}
static struct bc_hw_ops hscx_ops = {
.read_reg = ReadHSCX,
.write_reg = WriteHSCX,
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
/*
......
drivers/isdn/hisax/telespci.c
View file @ 8fa894ae
......@@ -39,23 +39,23 @@ const char *telespci_revision = "$Revision: 2.16.6.5 $";
#define WRITE_DATA_HSCX (ZORAN_PO_WR | ZORAN_PO_GID1 | ZORAN_PO_GREG1)
#define ZORAN_WAIT_NOBUSY do { \
portdata = readl(adr + 0x200); \
portdata = readl(adr); \
} while (portdata & ZORAN_PO_RQ_PEN)
static u8
isac_read(struct IsdnCardState *cs, u8 off)
{
unsigned long adr = cs->hw.teles0.membase;
unsigned long adr = cs->hw.teles0.membase + 0x200;
unsigned int portdata;
ZORAN_WAIT_NOBUSY;
/* set address for ISAC */
writel(WRITE_ADDR_ISAC | off, adr + 0x200);
writel(WRITE_ADDR_ISAC | off, adr);
ZORAN_WAIT_NOBUSY;
/* read data from ISAC */
writel(READ_DATA_ISAC, adr + 0x200);
writel(READ_DATA_ISAC, adr);
ZORAN_WAIT_NOBUSY;
return((u8)(portdata & ZORAN_PO_DMASK));
}
......@@ -63,24 +63,24 @@ isac_read(struct IsdnCardState *cs, u8 off)
static void
isac_write(struct IsdnCardState *cs, u8 off, u8 data)
{
unsigned long adr = cs->hw.teles0.membase;
unsigned long adr = cs->hw.teles0.membase + 0x200;
unsigned int portdata;
ZORAN_WAIT_NOBUSY;
/* set address for ISAC */
writel(WRITE_ADDR_ISAC | off, adr + 0x200);
writel(WRITE_ADDR_ISAC | off, adr);
ZORAN_WAIT_NOBUSY;
/* write data to ISAC */
writel(WRITE_DATA_ISAC | data, adr + 0x200);
writel(WRITE_DATA_ISAC | data, adr);
ZORAN_WAIT_NOBUSY;
}
static void
isac_read_fifo(struct IsdnCardState *cs, u8 *data, int size)
{
unsigned long adr = cs->hw.teles0.membase;
unsigned long adr = cs->hw.teles0.membase + 0x200;
unsigned int portdata;
int i;
......@@ -90,7 +90,7 @@ isac_read_fifo(struct IsdnCardState *cs, u8 *data, int size)
/* set address for ISAC fifo */
writel(WRITE_ADDR_ISAC | 0x1E, adr);
ZORAN_WAIT_NOBUSY;
writel(READ_DATA_ISAC, adr + 0x200);
writel(READ_DATA_ISAC, adr);
ZORAN_WAIT_NOBUSY;
data[i] = (u8)(portdata & ZORAN_PO_DMASK);
}
......@@ -99,7 +99,7 @@ isac_read_fifo(struct IsdnCardState *cs, u8 *data, int size)
static void
isac_write_fifo(struct IsdnCardState *cs, u8 *data, int size)
{
unsigned long adr = cs->hw.teles0.membase;
unsigned long adr = cs->hw.teles0.membase + 0x200;
unsigned int portdata;
int i;
......@@ -109,7 +109,7 @@ isac_write_fifo(struct IsdnCardState *cs, u8 *data, int size)
/* set address for ISAC fifo */
writel(WRITE_ADDR_ISAC | 0x1E, adr);
ZORAN_WAIT_NOBUSY;
writel(WRITE_DATA_ISAC | data[i], adr + 0x200);
writel(WRITE_DATA_ISAC | data[i], adr);
ZORAN_WAIT_NOBUSY;
}
}
......@@ -121,98 +121,92 @@ static struct dc_hw_ops isac_ops = {
.write_fifo = isac_write_fifo,
};
static inline u8
readhscx(unsigned long adr, int hscx, u8 off)
static u8
hscx_read(struct IsdnCardState *cs, int hscx, u8 off)
{
register unsigned int portdata;
unsigned long adr = cs->hw.teles0.membase + 0x200;
unsigned int portdata;
ZORAN_WAIT_NOBUSY;
/* set address for HSCX */
writel(WRITE_ADDR_HSCX | ((hscx ? 0x40:0) + off), adr + 0x200);
writel(WRITE_ADDR_HSCX | ((hscx ? 0x40:0) + off), adr);
ZORAN_WAIT_NOBUSY;
/* read data from HSCX */
writel(READ_DATA_HSCX, adr + 0x200);
writel(READ_DATA_HSCX, adr);
ZORAN_WAIT_NOBUSY;
return ((u8)(portdata & ZORAN_PO_DMASK));
}
static inline void
writehscx(unsigned long adr, int hscx, u8 off, u8 data)
static void
hscx_write(struct IsdnCardState *cs, int hscx, u8 off, u8 data)
{
register unsigned int portdata;
unsigned long adr = cs->hw.teles0.membase + 0x200;
unsigned int portdata;
ZORAN_WAIT_NOBUSY;
/* set address for HSCX */
writel(WRITE_ADDR_HSCX | ((hscx ? 0x40:0) + off), adr + 0x200);
writel(WRITE_ADDR_HSCX | ((hscx ? 0x40:0) + off), adr);
ZORAN_WAIT_NOBUSY;
/* write data to HSCX */
writel(WRITE_DATA_HSCX | data, adr + 0x200);
writel(WRITE_DATA_HSCX | data, adr);
ZORAN_WAIT_NOBUSY;
}
static inline void
read_fifo_hscx(unsigned long adr, int hscx, u8 * data, int size)
static void
hscx_read_fifo(struct IsdnCardState *cs, int hscx, u8 * data, int size)
{
register unsigned int portdata;
register int i;
unsigned long adr = cs->hw.teles0.membase + 0x200;
unsigned int portdata;
int i;
ZORAN_WAIT_NOBUSY;
/* read data from HSCX */
for (i = 0; i < size; i++) {
/* set address for HSCX fifo */
writel(WRITE_ADDR_HSCX |(hscx ? 0x5F:0x1F), adr + 0x200);
writel(WRITE_ADDR_HSCX |(hscx ? 0x5F:0x1F), adr);
ZORAN_WAIT_NOBUSY;
writel(READ_DATA_HSCX, adr + 0x200);
writel(READ_DATA_HSCX, adr);
ZORAN_WAIT_NOBUSY;
data[i] = (u8) (portdata & ZORAN_PO_DMASK);
}
}
static inline void
write_fifo_hscx(unsigned long adr, int hscx, u8 * data, int size)
static void
hscx_write_fifo(struct IsdnCardState *cs, int hscx, u8 * data, int size)
{
unsigned long adr = cs->hw.teles0.membase + 0x200;
unsigned int portdata;
register int i;
int i;
ZORAN_WAIT_NOBUSY;
/* write data to HSCX */
for (i = 0; i < size; i++) {
/* set address for HSCX fifo */
writel(WRITE_ADDR_HSCX |(hscx ? 0x5F:0x1F), adr + 0x200);
writel(WRITE_ADDR_HSCX |(hscx ? 0x5F:0x1F), adr);
ZORAN_WAIT_NOBUSY;
writel(WRITE_DATA_HSCX | data[i], adr + 0x200);
writel(WRITE_DATA_HSCX | data[i], adr);
ZORAN_WAIT_NOBUSY;
udelay(10);
}
}
static u8
ReadHSCX(struct IsdnCardState *cs, int hscx, u8 offset)
{
return (readhscx(cs->hw.teles0.membase, hscx, offset));
}
static void
WriteHSCX(struct IsdnCardState *cs, int hscx, u8 offset, u8 value)
{
writehscx(cs->hw.teles0.membase, hscx, offset, value);
}
static struct bc_hw_ops hscx_ops = {
.read_reg = ReadHSCX,
.write_reg = WriteHSCX,
.read_reg = hscx_read,
.write_reg = hscx_write,
.read_fifo = hscx_read_fifo,
.write_fifo = hscx_write_fifo,
};
/*
* fast interrupt HSCX stuff goes here
*/
#define READHSCX(cs, nr, reg) readhscx(cs->hw.teles0.membase, nr, reg)
#define WRITEHSCX(cs, nr, reg, data) writehscx(cs->hw.teles0.membase, nr, reg, data)
#define READHSCXFIFO(cs, nr, ptr, cnt) read_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) write_fifo_hscx(cs->hw.teles0.membase, nr, ptr, cnt)
#define READHSCX(cs, nr, reg) hscx_read(cs, nr, reg)
#define WRITEHSCX(cs, nr, reg, data) hscx_write(cs, nr, reg, data)
#define READHSCXFIFO(cs, nr, ptr, cnt) hscx_read_fifo(cs, nr, ptr, cnt)
#define WRITEHSCXFIFO(cs, nr, ptr, cnt) hscx_write_fifo(cs, nr, ptr, cnt)
#include "hscx_irq.c"
......@@ -224,7 +218,7 @@ telespci_interrupt(int intno, void *dev_id, struct pt_regs *regs)
u8 val;
spin_lock(&cs->lock);
val = readhscx(cs->hw.teles0.membase, 1, HSCX_ISTA);
val = hscx_read(cs, 1, HSCX_ISTA);
if (val)
hscx_int_main(cs, val);
val = isac_read(cs, ISAC_ISTA);
......@@ -233,12 +227,12 @@ telespci_interrupt(int intno, void *dev_id, struct pt_regs *regs)
/* Clear interrupt register for Zoran PCI controller */
writel(0x70000000, cs->hw.teles0.membase + 0x3C);
writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0xFF);
writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0xFF);
hscx_write(cs, 0, HSCX_MASK, 0xFF);
hscx_write(cs, 1, HSCX_MASK, 0xFF);
isac_write(cs, ISAC_MASK, 0xFF);
isac_write(cs, ISAC_MASK, 0x0);
writehscx(cs->hw.teles0.membase, 0, HSCX_MASK, 0x0);
writehscx(cs->hw.teles0.membase, 1, HSCX_MASK, 0x0);
hscx_write(cs, 0, HSCX_MASK, 0x0);
hscx_write(cs, 1, HSCX_MASK, 0x0);
spin_unlock(&cs->lock);
}
......
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