Commit 903bfeac authored by Andy Walls's avatar Andy Walls Committed by Mauro Carvalho Chehab

V4L/DVB (10274): cx18: Fix a PLL divisor update for the I2S master clock

A redundant PLL divisior update for the I2S master clock after AV core
firmware load was missed in earlier PLL parameter changes.  This one really
doesn't matter because it's redundant and gets overwritten, but the driver
should be self consistent in the values used.
Signed-off-by: default avatarAndy Walls <awalls@radix.net>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent f97d2074
...@@ -115,9 +115,9 @@ int cx18_av_loadfw(struct cx18 *cx) ...@@ -115,9 +115,9 @@ int cx18_av_loadfw(struct cx18 *cx)
are generated) */ are generated) */
cx18_av_write4(cx, CXADEC_I2S_OUT_CTL, 0x000001A0); cx18_av_write4(cx, CXADEC_I2S_OUT_CTL, 0x000001A0);
/* set alt I2s master clock to /16 and enable alt divider i2s /* set alt I2s master clock to /0x16 and enable alt divider i2s
passthrough */ passthrough */
cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5000B687); cx18_av_write4(cx, CXADEC_PIN_CFG3, 0x5600B687);
cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, 0x000000F6, 0x000000F6, cx18_av_write4_expect(cx, CXADEC_STD_DET_CTL, 0x000000F6, 0x000000F6,
0x3F00FFFF); 0x3F00FFFF);
......
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