Commit 911779e3 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher

drm/amd/pm: add Raven2 watermark WmType setting

Which tells it's a normal pstate change or memory retraining.
Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Tested-by: default avatarChangfeng Zhu <Changfeng.Zhu@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ce2c0006
...@@ -54,7 +54,8 @@ typedef struct { ...@@ -54,7 +54,8 @@ typedef struct {
uint16_t MaxMclk; uint16_t MaxMclk;
uint8_t WmSetting; uint8_t WmSetting;
uint8_t Padding[3]; uint8_t WmType;
uint8_t Padding[2];
} WatermarkRowGeneric_t; } WatermarkRowGeneric_t;
#define NUM_WM_RANGES 4 #define NUM_WM_RANGES 4
......
...@@ -1181,8 +1181,19 @@ static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr, ...@@ -1181,8 +1181,19 @@ static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
struct smu10_hwmgr *data = hwmgr->backend; struct smu10_hwmgr *data = hwmgr->backend;
struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges; struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
Watermarks_t *table = &(data->water_marks_table); Watermarks_t *table = &(data->water_marks_table);
struct amdgpu_device *adev = hwmgr->adev;
int i;
smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges); smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges);
if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
for (i = 0; i < NUM_WM_RANGES; i++)
table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0;
for (i = 0; i < NUM_WM_RANGES; i++)
table->WatermarkRow[WM_SOCCLK][i].WmType = (uint8_t)0;
}
smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false); smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);
data->water_marks_exist = true; data->water_marks_exist = true;
return 0; return 0;
......
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