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Commit 912c9fbe authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'imx-drivers-4.12' of... 

Merge tag 'imx-drivers-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/drivers

i.MX drivers updates for 4.12:
 - A series from Lucas Stach which partly rewrites the imx gpc driver
   to support multiple power domains, and moves the related code from
   imx platform into drivers folder.
 - A series from Dong Aisheng which fixes the issues with Lucas' code
   changes and improves things.
 - Add workaround for i.MX6QP hardware erratum ERR009619 that is PRE
   clocks may be stalled during the power up sequencing of the PU power
   domain.
 - Add imx-gpcv2 driver to support power domains managed by GPCv2 IP
   block found on i.MX7 series of SoCs.

* tag 'imx-drivers-4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver
  dt-bindings: imx-gpc: add i.MX6 QuadPlus compatible
  soc: imx: gpc: add defines for domain index
  soc: imx: Add GPCv2 power gating driver
  dt-bindings: Add GPCv2 power gating driver
  soc: imx: gpc: remove unnecessary readable_reg callback
  dt-bindings: imx-gpc: correct the DOMAIN_INDEX using
  soc: imx: gpc: keep PGC_X_CTRL name align with reference manual
  soc: imx: gpc: fix comment when power up domain
  soc: imx: gpc: fix imx6sl gpc power domain regression
  soc: imx: gpc: fix domain_index sanity check issue
  soc: imx: gpc: fix the wrong using of regmap cache
  soc: imx: gpc: fix gpc clk get error handling
  soc: imx: move PGC handling to a new GPC driver
  dt-bindings: add multidomain support to i.MX GPC DT binding
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 7b020654 44c43c98
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Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
View file @ 912c9fbe
Freescale i.MX General Power Controller Freescale i.MX General Power Controller
======================================= =======================================
The i.MX6Q General Power Control (GPC) block contains DVFS load tracking The i.MX6 General Power Control (GPC) block contains DVFS load tracking
counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power counters and Power Gating Control (PGC).
domains.
Required properties: Required properties:
- compatible: Should be "fsl,imx6q-gpc" or "fsl,imx6sl-gpc" - compatible: Should be one of the following:
- fsl,imx6q-gpc
- fsl,imx6qp-gpc
- fsl,imx6sl-gpc
- reg: should be register base and length as documented in the - reg: should be register base and length as documented in the
datasheet datasheet
- interrupts: Should contain GPC interrupt request 1 - interrupts: Should contain one interrupt specifier for the GPC interrupt
- pu-supply: Link to the LDO regulator powering the PU power domain - clocks: Must contain an entry for each entry in clock-names.
- clocks: Clock phandles to devices in the PU power domain that need See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
to be enabled during domain power-up for reset propagation. - clock-names: Must include the following entries:
- #power-domain-cells: Should be 1, see below: - ipg
The gpc node is a power-controller as documented by the generic power domain The power domains are generic power domain providers as documented in
bindings in Documentation/devicetree/bindings/power/power_domain.txt. Documentation/devicetree/bindings/power/power_domain.txt. They are described as
subnodes of the power gating controller 'pgc' node of the GPC and should
contain the following:
Required properties:
- reg: Must contain the DOMAIN_INDEX of this power domain
The following DOMAIN_INDEX values are valid for i.MX6Q:
ARM_DOMAIN 0
PU_DOMAIN 1
The following additional DOMAIN_INDEX value is valid for i.MX6SL:
DISPLAY_DOMAIN 2
- #power-domain-cells: Should be 0
Optional properties:
- clocks: a number of phandles to clocks that need to be enabled during domain
power-up sequencing to ensure reset propagation into devices located inside
this power domain
- power-supply: a phandle to the regulator powering this domain
Example: Example:
...@@ -25,14 +45,30 @@ Example: ...@@ -25,14 +45,30 @@ Example:
reg = <0x020dc000 0x4000>; reg = <0x020dc000 0x4000>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
<0 90 IRQ_TYPE_LEVEL_HIGH>; <0 90 IRQ_TYPE_LEVEL_HIGH>;
pu-supply = <&reg_pu>; clocks = <&clks IMX6QDL_CLK_IPG>;
clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, clock-names = "ipg";
<&clks IMX6QDL_CLK_GPU3D_SHADER>,
<&clks IMX6QDL_CLK_GPU2D_CORE>, pgc {
<&clks IMX6QDL_CLK_GPU2D_AXI>, #address-cells = <1>;
<&clks IMX6QDL_CLK_OPENVG_AXI>, #size-cells = <0>;
<&clks IMX6QDL_CLK_VPU_AXI>;
#power-domain-cells = <1>; power-domain@0 {
reg = <0>;
#power-domain-cells = <0>;
};
pd_pu: power-domain@1 {
reg = <1>;
#power-domain-cells = <0>;
power-supply = <&reg_pu>;
clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
<&clks IMX6QDL_CLK_GPU3D_SHADER>,
<&clks IMX6QDL_CLK_GPU2D_CORE>,
<&clks IMX6QDL_CLK_GPU2D_AXI>,
<&clks IMX6QDL_CLK_OPENVG_AXI>,
<&clks IMX6QDL_CLK_VPU_AXI>;
};
};
}; };
...@@ -40,20 +76,13 @@ Specifying power domain for IP modules ...@@ -40,20 +76,13 @@ Specifying power domain for IP modules
====================================== ======================================
IP cores belonging to a power domain should contain a 'power-domains' property IP cores belonging to a power domain should contain a 'power-domains' property
that is a phandle pointing to the gpc device node and a DOMAIN_INDEX specifying that is a phandle pointing to the power domain the device belongs to.
the power domain the device belongs to.
Example of a device that is part of the PU power domain: Example of a device that is part of the PU power domain:
vpu: vpu@02040000 { vpu: vpu@02040000 {
reg = <0x02040000 0x3c000>; reg = <0x02040000 0x3c000>;
/* ... */ /* ... */
power-domains = <&gpc 1>; power-domains = <&pd_pu>;
/* ... */ /* ... */
}; };
The following DOMAIN_INDEX values are valid for i.MX6Q:
ARM_DOMAIN 0
PU_DOMAIN 1
The following additional DOMAIN_INDEX value is valid for i.MX6SL:
DISPLAY_DOMAIN 2
Documentation/devicetree/bindings/power/fsl,imx-gpcv2.txt 0 → 100644
View file @ 912c9fbe
Freescale i.MX General Power Controller v2
==========================================
The i.MX7S/D General Power Control (GPC) block contains Power Gating
Control (PGC) for various power domains.
Required properties:
- compatible: Should be "fsl,imx7d-gpc"
- reg: should be register base and length as documented in the
datasheet
- interrupts: Should contain GPC interrupt request 1
Power domains contained within GPC node are generic power domain
providers, documented in
Documentation/devicetree/bindings/power/power_domain.txt, which are
described as subnodes of the power gating controller 'pgc' node,
which, in turn, is expected to contain the following:
Required properties:
- reg: Power domain index. Valid values are defined in
include/dt-bindings/power/imx7-power.h
- #power-domain-cells: Should be 0
Optional properties:
- power-supply: Power supply used to power the domain
Example:
gpc: gpc@303a0000 {
compatible = "fsl,imx7d-gpc";
reg = <0x303a0000 0x1000>;
interrupt-controller;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <3>;
interrupt-parent = <&intc>;
pgc {
#address-cells = <1>;
#size-cells = <0>;
pgc_pcie_phy: power-domain@3 {
#power-domain-cells = <0>;
reg = <IMX7_POWER_DOMAIN_PCIE_PHY>;
power-supply = <&reg_1p0d>;
};
};
};
Specifying power domain for IP modules
======================================
IP cores belonging to a power domain should contain a 'power-domains'
property that is a phandle for PGC node representing the domain.
Example of a device that is part of the PCIE_PHY power domain:
pcie: pcie@33800000 {
reg = <0x33800000 0x4000>,
<0x4ff00000 0x80000>;
/* ... */
power-domains = <&pgc_pcie_phy>;
/* ... */
};
MAINTAINERS
View file @ 912c9fbe
...@@ -1268,6 +1268,7 @@ F: arch/arm/mach-mxs/ ...@@ -1268,6 +1268,7 @@ F: arch/arm/mach-mxs/
F: arch/arm/boot/dts/imx* F: arch/arm/boot/dts/imx*
F: arch/arm/configs/imx*_defconfig F: arch/arm/configs/imx*_defconfig
F: drivers/clk/imx/ F: drivers/clk/imx/
F: drivers/soc/imx/
F: include/soc/imx/ F: include/soc/imx/
ARM/FREESCALE VYBRID ARM ARCHITECTURE ARM/FREESCALE VYBRID ARM ARCHITECTURE
......
arch/arm/mach-imx/gpc.c
View file @ 912c9fbe
...@@ -10,26 +10,17 @@ ...@@ -10,26 +10,17 @@
* http://www.gnu.org/copyleft/gpl.html * http://www.gnu.org/copyleft/gpl.html
*/ */
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/irq.h> #include <linux/irq.h>
#include <linux/irqchip.h> #include <linux/irqchip.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/of_irq.h> #include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/regulator/consumer.h>
#include <linux/irqchip/arm-gic.h> #include <linux/irqchip/arm-gic.h>
#include "common.h" #include "common.h"
#include "hardware.h" #include "hardware.h"
#define GPC_CNTR 0x000
#define GPC_IMR1 0x008 #define GPC_IMR1 0x008
#define GPC_PGC_GPU_PDN 0x260
#define GPC_PGC_GPU_PUPSCR 0x264
#define GPC_PGC_GPU_PDNSCR 0x268
#define GPC_PGC_CPU_PDN 0x2a0 #define GPC_PGC_CPU_PDN 0x2a0
#define GPC_PGC_CPU_PUPSCR 0x2a4 #define GPC_PGC_CPU_PUPSCR 0x2a4
#define GPC_PGC_CPU_PDNSCR 0x2a8 #define GPC_PGC_CPU_PDNSCR 0x2a8
...@@ -39,18 +30,6 @@ ...@@ -39,18 +30,6 @@
#define IMR_NUM 4 #define IMR_NUM 4
#define GPC_MAX_IRQS (IMR_NUM * 32) #define GPC_MAX_IRQS (IMR_NUM * 32)
#define GPU_VPU_PUP_REQ BIT(1)
#define GPU_VPU_PDN_REQ BIT(0)
#define GPC_CLK_MAX 6
struct pu_domain {
struct generic_pm_domain base;
struct regulator *reg;
struct clk *clk[GPC_CLK_MAX];
int num_clks;
};
static void __iomem *gpc_base; static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM]; static u32 gpc_wake_irqs[IMR_NUM];
static u32 gpc_saved_imrs[IMR_NUM]; static u32 gpc_saved_imrs[IMR_NUM];
...@@ -296,199 +275,3 @@ void __init imx_gpc_check_dt(void) ...@@ -296,199 +275,3 @@ void __init imx_gpc_check_dt(void)
gpc_base = of_iomap(np, 0); gpc_base = of_iomap(np, 0);
} }
} }
static void _imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
{
int iso, iso2sw;
u32 val;
/* Read ISO and ISO2SW power down delays */
val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
iso = val & 0x3f;
iso2sw = (val >> 8) & 0x3f;
/* Gate off PU domain when GPU/VPU when powered down */
writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
/* Request GPC to power down GPU/VPU */
val = readl_relaxed(gpc_base + GPC_CNTR);
val |= GPU_VPU_PDN_REQ;
writel_relaxed(val, gpc_base + GPC_CNTR);
/* Wait ISO + ISO2SW IPG clock cycles */
ndelay((iso + iso2sw) * 1000 / 66);
}
static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
{
struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
_imx6q_pm_pu_power_off(genpd);
if (pu->reg)
regulator_disable(pu->reg);
return 0;
}
static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
{
struct pu_domain *pu = container_of(genpd, struct pu_domain, base);
int i, ret, sw, sw2iso;
u32 val;
if (pu->reg)
ret = regulator_enable(pu->reg);
if (pu->reg && ret) {
pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
return ret;
}
/* Enable reset clocks for all devices in the PU domain */
for (i = 0; i < pu->num_clks; i++)
clk_prepare_enable(pu->clk[i]);
/* Gate off PU domain when GPU/VPU when powered down */
writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
/* Read ISO and ISO2SW power down delays */
val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
sw = val & 0x3f;
sw2iso = (val >> 8) & 0x3f;
/* Request GPC to power up GPU/VPU */
val = readl_relaxed(gpc_base + GPC_CNTR);
val |= GPU_VPU_PUP_REQ;
writel_relaxed(val, gpc_base + GPC_CNTR);
/* Wait ISO + ISO2SW IPG clock cycles */
ndelay((sw + sw2iso) * 1000 / 66);
/* Disable reset clocks for all devices in the PU domain */
for (i = 0; i < pu->num_clks; i++)
clk_disable_unprepare(pu->clk[i]);
return 0;
}
static struct generic_pm_domain imx6q_arm_domain = {
.name = "ARM",
};
static struct pu_domain imx6q_pu_domain = {
.base = {
.name = "PU",
.power_off = imx6q_pm_pu_power_off,
.power_on = imx6q_pm_pu_power_on,
},
};
static struct generic_pm_domain imx6sl_display_domain = {
.name = "DISPLAY",
};
static struct generic_pm_domain *imx_gpc_domains[] = {
&imx6q_arm_domain,
&imx6q_pu_domain.base,
&imx6sl_display_domain,
};
static struct genpd_onecell_data imx_gpc_onecell_data = {
.domains = imx_gpc_domains,
.num_domains = ARRAY_SIZE(imx_gpc_domains),
};
static int imx_gpc_genpd_init(struct device *dev, struct regulator *pu_reg)
{
struct clk *clk;
int i, ret;
imx6q_pu_domain.reg = pu_reg;
for (i = 0; ; i++) {
clk = of_clk_get(dev->of_node, i);
if (IS_ERR(clk))
break;
if (i >= GPC_CLK_MAX) {
dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
goto clk_err;
}
imx6q_pu_domain.clk[i] = clk;
}
imx6q_pu_domain.num_clks = i;
/* Enable power always in case bootloader disabled it. */
imx6q_pm_pu_power_on(&imx6q_pu_domain.base);
if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS))
return 0;
imx6q_pu_domain.base.states = devm_kzalloc(dev,
sizeof(*imx6q_pu_domain.base.states),
GFP_KERNEL);
if (!imx6q_pu_domain.base.states)
return -ENOMEM;
imx6q_pu_domain.base.states[0].power_off_latency_ns = 25000;
imx6q_pu_domain.base.states[0].power_on_latency_ns = 2000000;
imx6q_pu_domain.base.state_count = 1;
for (i = 0; i < ARRAY_SIZE(imx_gpc_domains); i++)
pm_genpd_init(imx_gpc_domains[i], NULL, false);
ret = of_genpd_add_provider_onecell(dev->of_node,
&imx_gpc_onecell_data);
if (ret)
goto power_off;
return 0;
power_off:
imx6q_pm_pu_power_off(&imx6q_pu_domain.base);
clk_err:
while (i--)
clk_put(imx6q_pu_domain.clk[i]);
imx6q_pu_domain.reg = NULL;
return -EINVAL;
}
static int imx_gpc_probe(struct platform_device *pdev)
{
struct regulator *pu_reg;
int ret;
/* bail out if DT too old and doesn't provide the necessary info */
if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells"))
return 0;
pu_reg = devm_regulator_get_optional(&pdev->dev, "pu");
if (PTR_ERR(pu_reg) == -ENODEV)
pu_reg = NULL;
if (IS_ERR(pu_reg)) {
ret = PTR_ERR(pu_reg);
dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
return ret;
}
return imx_gpc_genpd_init(&pdev->dev, pu_reg);
}
static const struct of_device_id imx_gpc_dt_ids[] = {
{ .compatible = "fsl,imx6q-gpc" },
{ .compatible = "fsl,imx6sl-gpc" },
{ }
};
static struct platform_driver imx_gpc_driver = {
.driver = {
.name = "imx-gpc",
.of_match_table = imx_gpc_dt_ids,
},
.probe = imx_gpc_probe,
};
static int __init imx_pgc_init(void)
{
return platform_driver_register(&imx_gpc_driver);
}
subsys_initcall(imx_pgc_init);
drivers/soc/Kconfig
View file @ 912c9fbe
...@@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers" ...@@ -2,6 +2,7 @@ menu "SOC (System On Chip) specific Drivers"
source "drivers/soc/bcm/Kconfig" source "drivers/soc/bcm/Kconfig"
source "drivers/soc/fsl/Kconfig" source "drivers/soc/fsl/Kconfig"
source "drivers/soc/imx/Kconfig"
source "drivers/soc/mediatek/Kconfig" source "drivers/soc/mediatek/Kconfig"
source "drivers/soc/qcom/Kconfig" source "drivers/soc/qcom/Kconfig"
source "drivers/soc/rockchip/Kconfig" source "drivers/soc/rockchip/Kconfig"
......
drivers/soc/Makefile
View file @ 912c9fbe
...@@ -6,6 +6,7 @@ obj-y += bcm/ ...@@ -6,6 +6,7 @@ obj-y += bcm/
obj-$(CONFIG_ARCH_DOVE) += dove/ obj-$(CONFIG_ARCH_DOVE) += dove/
obj-$(CONFIG_MACH_DOVE) += dove/ obj-$(CONFIG_MACH_DOVE) += dove/
obj-y += fsl/ obj-y += fsl/
obj-$(CONFIG_ARCH_MXC) += imx/
obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/
obj-$(CONFIG_ARCH_QCOM) += qcom/ obj-$(CONFIG_ARCH_QCOM) += qcom/
obj-$(CONFIG_ARCH_RENESAS) += renesas/ obj-$(CONFIG_ARCH_RENESAS) += renesas/
......
drivers/soc/imx/Kconfig 0 → 100644
View file @ 912c9fbe
menu "i.MX SoC drivers"
config IMX7_PM_DOMAINS
bool "i.MX7 PM domains"
select PM_GENERIC_DOMAINS
depends on SOC_IMX7D || (COMPILE_TEST && OF)
default y if SOC_IMX7D
endmenu
drivers/soc/imx/Makefile 0 → 100644
View file @ 912c9fbe
obj-y += gpc.o
obj-$(CONFIG_IMX7_PM_DOMAINS) += gpcv2.o
drivers/soc/imx/gpc.c 0 → 100644
View file @ 912c9fbe
This diff is collapsed.
drivers/soc/imx/gpcv2.c 0 → 100644
View file @ 912c9fbe
/*
* Copyright 2017 Impinj, Inc
* Author: Andrey Smirnov <andrew.smirnov@gmail.com>
*
* Based on the code of analogus driver:
*
* Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
*
* The code contained herein is licensed under the GNU General Public
* License. You may obtain a copy of the GNU General Public License
* Version 2 or later at the following locations:
*
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <dt-bindings/power/imx7-power.h>
#define GPC_LPCR_A7_BSC 0x000
#define GPC_PGC_CPU_MAPPING 0x0ec
#define USB_HSIC_PHY_A7_DOMAIN BIT(6)
#define USB_OTG2_PHY_A7_DOMAIN BIT(5)
#define USB_OTG1_PHY_A7_DOMAIN BIT(4)
#define PCIE_PHY_A7_DOMAIN BIT(3)
#define MIPI_PHY_A7_DOMAIN BIT(2)
#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
#define GPC_PU_PGC_SW_PDN_REQ 0x104
#define USB_HSIC_PHY_SW_Pxx_REQ BIT(4)
#define USB_OTG2_PHY_SW_Pxx_REQ BIT(3)
#define USB_OTG1_PHY_SW_Pxx_REQ BIT(2)
#define PCIE_PHY_SW_Pxx_REQ BIT(1)
#define MIPI_PHY_SW_Pxx_REQ BIT(0)
#define GPC_M4_PU_PDN_FLG 0x1bc
#define PGC_MIPI 4
#define PGC_PCIE 5
#define PGC_USB_HSIC 8
#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
#define GPC_PGC_CTRL_PCR BIT(0)
struct imx7_pgc_domain {
struct generic_pm_domain genpd;
struct regmap *regmap;
struct regulator *regulator;
unsigned int pgc;
const struct {
u32 pxx;
u32 map;
} bits;
const int voltage;
struct device *dev;
};
static int imx7_gpc_pu_pgc_sw_pxx_req(struct generic_pm_domain *genpd,
bool on)
{
struct imx7_pgc_domain *domain = container_of(genpd,
struct imx7_pgc_domain,
genpd);
unsigned int offset = on ?
GPC_PU_PGC_SW_PUP_REQ : GPC_PU_PGC_SW_PDN_REQ;
const bool enable_power_control = !on;
const bool has_regulator = !IS_ERR(domain->regulator);
unsigned long deadline;
int ret = 0;
regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
domain->bits.map, domain->bits.map);
if (has_regulator && on) {
ret = regulator_enable(domain->regulator);
if (ret) {
dev_err(domain->dev, "failed to enable regulator\n");
goto unmap;
}
}
if (enable_power_control)
regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
GPC_PGC_CTRL_PCR, GPC_PGC_CTRL_PCR);
regmap_update_bits(domain->regmap, offset,
domain->bits.pxx, domain->bits.pxx);
/*
* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
* for PUP_REQ/PDN_REQ bit to be cleared
*/
deadline = jiffies + msecs_to_jiffies(1);
while (true) {
u32 pxx_req;
regmap_read(domain->regmap, offset, &pxx_req);
if (!(pxx_req & domain->bits.pxx))
break;
if (time_after(jiffies, deadline)) {
dev_err(domain->dev, "falied to command PGC\n");
ret = -ETIMEDOUT;
/*
* If we were in a process of enabling a
* domain and failed we might as well disable
* the regulator we just enabled. And if it
* was the opposite situation and we failed to
* power down -- keep the regulator on
*/
on = !on;
break;
}
cpu_relax();
}
if (enable_power_control)
regmap_update_bits(domain->regmap, GPC_PGC_CTRL(domain->pgc),
GPC_PGC_CTRL_PCR, 0);
if (has_regulator && !on) {
int err;
err = regulator_disable(domain->regulator);
if (err)
dev_err(domain->dev,
"failed to disable regulator: %d\n", ret);
/* Preserve earlier error code */
ret = ret ?: err;
}
unmap:
regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
domain->bits.map, 0);
return ret;
}
static int imx7_gpc_pu_pgc_sw_pup_req(struct generic_pm_domain *genpd)
{
return imx7_gpc_pu_pgc_sw_pxx_req(genpd, true);
}
static int imx7_gpc_pu_pgc_sw_pdn_req(struct generic_pm_domain *genpd)
{
return imx7_gpc_pu_pgc_sw_pxx_req(genpd, false);
}
static struct imx7_pgc_domain imx7_pgc_domains[] = {
[IMX7_POWER_DOMAIN_MIPI_PHY] = {
.genpd = {
.name = "mipi-phy",
},
.bits = {
.pxx = MIPI_PHY_SW_Pxx_REQ,
.map = MIPI_PHY_A7_DOMAIN,
},
.voltage = 1000000,
.pgc = PGC_MIPI,
},
[IMX7_POWER_DOMAIN_PCIE_PHY] = {
.genpd = {
.name = "pcie-phy",
},
.bits = {
.pxx = PCIE_PHY_SW_Pxx_REQ,
.map = PCIE_PHY_A7_DOMAIN,
},
.voltage = 1000000,
.pgc = PGC_PCIE,
},
[IMX7_POWER_DOMAIN_USB_HSIC_PHY] = {
.genpd = {
.name = "usb-hsic-phy",
},
.bits = {
.pxx = USB_HSIC_PHY_SW_Pxx_REQ,
.map = USB_HSIC_PHY_A7_DOMAIN,
},
.voltage = 1200000,
.pgc = PGC_USB_HSIC,
},
};
static int imx7_pgc_domain_probe(struct platform_device *pdev)
{
struct imx7_pgc_domain *domain = pdev->dev.platform_data;
int ret;
domain->dev = &pdev->dev;
ret = pm_genpd_init(&domain->genpd, NULL, true);
if (ret) {
dev_err(domain->dev, "Failed to init power domain\n");
return ret;
}
domain->regulator = devm_regulator_get_optional(domain->dev, "power");
if (IS_ERR(domain->regulator)) {
if (PTR_ERR(domain->regulator) != -ENODEV) {
dev_err(domain->dev, "Failed to get domain's regulator\n");
return PTR_ERR(domain->regulator);
}
} else {
regulator_set_voltage(domain->regulator,
domain->voltage, domain->voltage);
}
ret = of_genpd_add_provider_simple(domain->dev->of_node,
&domain->genpd);
if (ret) {
dev_err(domain->dev, "Failed to add genpd provider\n");
pm_genpd_remove(&domain->genpd);
}
return ret;
}
static int imx7_pgc_domain_remove(struct platform_device *pdev)
{
struct imx7_pgc_domain *domain = pdev->dev.platform_data;
of_genpd_del_provider(domain->dev->of_node);
pm_genpd_remove(&domain->genpd);
return 0;
}
static const struct platform_device_id imx7_pgc_domain_id[] = {
{ "imx7-pgc-domain", },
{ },
};
static struct platform_driver imx7_pgc_domain_driver = {
.driver = {
.name = "imx7-pgc",
},
.probe = imx7_pgc_domain_probe,
.remove = imx7_pgc_domain_remove,
.id_table = imx7_pgc_domain_id,
};
builtin_platform_driver(imx7_pgc_domain_driver)
static int imx_gpcv2_probe(struct platform_device *pdev)
{
static const struct regmap_range yes_ranges[] = {
regmap_reg_range(GPC_LPCR_A7_BSC,
GPC_M4_PU_PDN_FLG),
regmap_reg_range(GPC_PGC_CTRL(PGC_MIPI),
GPC_PGC_SR(PGC_MIPI)),
regmap_reg_range(GPC_PGC_CTRL(PGC_PCIE),
GPC_PGC_SR(PGC_PCIE)),
regmap_reg_range(GPC_PGC_CTRL(PGC_USB_HSIC),
GPC_PGC_SR(PGC_USB_HSIC)),
};
static const struct regmap_access_table access_table = {
.yes_ranges = yes_ranges,
.n_yes_ranges = ARRAY_SIZE(yes_ranges),
};
static const struct regmap_config regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.rd_table = &access_table,
.wr_table = &access_table,
.max_register = SZ_4K,
};
struct device *dev = &pdev->dev;
struct device_node *pgc_np, *np;
struct regmap *regmap;
struct resource *res;
void __iomem *base;
int ret;
pgc_np = of_get_child_by_name(dev->of_node, "pgc");
if (!pgc_np) {
dev_err(dev, "No power domains specified in DT\n");
return -EINVAL;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(dev, res);
if (IS_ERR(base))
return PTR_ERR(base);
regmap = devm_regmap_init_mmio(dev, base, &regmap_config);
if (IS_ERR(regmap)) {
ret = PTR_ERR(regmap);
dev_err(dev, "failed to init regmap (%d)\n", ret);
return ret;
}
for_each_child_of_node(pgc_np, np) {
struct platform_device *pd_pdev;
struct imx7_pgc_domain *domain;
u32 domain_index;
ret = of_property_read_u32(np, "reg", &domain_index);
if (ret) {
dev_err(dev, "Failed to read 'reg' property\n");
of_node_put(np);
return ret;
}
if (domain_index >= ARRAY_SIZE(imx7_pgc_domains)) {
dev_warn(dev,
"Domain index %d is out of bounds\n",
domain_index);
continue;
}
domain = &imx7_pgc_domains[domain_index];
domain->regmap = regmap;
domain->genpd.power_on = imx7_gpc_pu_pgc_sw_pup_req;
domain->genpd.power_off = imx7_gpc_pu_pgc_sw_pdn_req;
pd_pdev = platform_device_alloc("imx7-pgc-domain",
domain_index);
if (!pd_pdev) {
dev_err(dev, "Failed to allocate platform device\n");
of_node_put(np);
return -ENOMEM;
}
pd_pdev->dev.platform_data = domain;
pd_pdev->dev.parent = dev;
pd_pdev->dev.of_node = np;
ret = platform_device_add(pd_pdev);
if (ret) {
platform_device_put(pd_pdev);
of_node_put(np);
return ret;
}
}
return 0;
}
static const struct of_device_id imx_gpcv2_dt_ids[] = {
{ .compatible = "fsl,imx7d-gpc" },
{ }
};
static struct platform_driver imx_gpc_driver = {
.driver = {
.name = "imx-gpcv2",
.of_match_table = imx_gpcv2_dt_ids,
},
.probe = imx_gpcv2_probe,
};
builtin_platform_driver(imx_gpc_driver)
include/dt-bindings/power/imx7-power.h 0 → 100644
View file @ 912c9fbe
/*
* Copyright (C) 2017 Impinj
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __DT_BINDINGS_IMX7_POWER_H__
#define __DT_BINDINGS_IMX7_POWER_H__
#define IMX7_POWER_DOMAIN_MIPI_PHY 0
#define IMX7_POWER_DOMAIN_PCIE_PHY 1
#define IMX7_POWER_DOMAIN_USB_HSIC_PHY 2
#endif
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