Commit 913a4a7d authored by Chunfeng Yun's avatar Chunfeng Yun Committed by Greg Kroah-Hartman

usb: gadget: bdc: avoid precedence issues

Add () around macro argument to avoid precedence issues

Cc: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Acked-by: default avatarFelipe Balbi <balbi@kernel.org>
Signed-off-by: default avatarChunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/1610505748-30616-7-git-send-email-chunfeng.yun@mediatek.comSigned-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 5ae5f76a
...@@ -86,20 +86,20 @@ ...@@ -86,20 +86,20 @@
#define BDC_EPSTS5 0x74 #define BDC_EPSTS5 0x74
#define BDC_EPSTS6 0x78 #define BDC_EPSTS6 0x78
#define BDC_EPSTS7 0x7c #define BDC_EPSTS7 0x7c
#define BDC_SRRBAL(n) (0x200 + (n * 0x10)) #define BDC_SRRBAL(n) (0x200 + ((n) * 0x10))
#define BDC_SRRBAH(n) (0x204 + (n * 0x10)) #define BDC_SRRBAH(n) (0x204 + ((n) * 0x10))
#define BDC_SRRINT(n) (0x208 + (n * 0x10)) #define BDC_SRRINT(n) (0x208 + ((n) * 0x10))
#define BDC_INTCTLS(n) (0x20c + (n * 0x10)) #define BDC_INTCTLS(n) (0x20c + ((n) * 0x10))
/* Extended capability regs */ /* Extended capability regs */
#define BDC_FSCNOC 0xcd4 #define BDC_FSCNOC 0xcd4
#define BDC_FSCNIC 0xce4 #define BDC_FSCNIC 0xce4
#define NUM_NCS(p) (p >> 28) #define NUM_NCS(p) ((p) >> 28)
/* Register bit fields and Masks */ /* Register bit fields and Masks */
/* BDC Configuration 0 */ /* BDC Configuration 0 */
#define BDC_PGS(p) (((p) & (0x7 << 8)) >> 8) #define BDC_PGS(p) (((p) & (0x7 << 8)) >> 8)
#define BDC_SPB(p) (p & 0x7) #define BDC_SPB(p) ((p) & 0x7)
/* BDC Capability1 */ /* BDC Capability1 */
#define BDC_P64 (1 << 0) #define BDC_P64 (1 << 0)
...@@ -113,7 +113,7 @@ ...@@ -113,7 +113,7 @@
#define BDC_CMD_DVC 0x1 #define BDC_CMD_DVC 0x1
#define BDC_CMD_CWS (0x1 << 5) #define BDC_CMD_CWS (0x1 << 5)
#define BDC_CMD_CST(p) (((p) & (0xf << 6))>>6) #define BDC_CMD_CST(p) (((p) & (0xf << 6))>>6)
#define BDC_CMD_EPN(p) ((p & 0x1f) << 10) #define BDC_CMD_EPN(p) (((p) & 0x1f) << 10)
#define BDC_SUB_CMD_ADD (0x1 << 17) #define BDC_SUB_CMD_ADD (0x1 << 17)
#define BDC_SUB_CMD_FWK (0x4 << 17) #define BDC_SUB_CMD_FWK (0x4 << 17)
/* Reset sequence number */ /* Reset sequence number */
...@@ -163,7 +163,7 @@ ...@@ -163,7 +163,7 @@
#define BDC_SPEED_HS 0x3 #define BDC_SPEED_HS 0x3
#define BDC_SPEED_SS 0x4 #define BDC_SPEED_SS 0x4
#define BDC_PST(p) (p & 0xf) #define BDC_PST(p) ((p) & 0xf)
#define BDC_PST_MASK 0xf #define BDC_PST_MASK 0xf
/* USPPMS */ /* USPPMS */
...@@ -228,7 +228,7 @@ ...@@ -228,7 +228,7 @@
/* status report defines */ /* status report defines */
#define SR_XSF 0 #define SR_XSF 0
#define SR_USPC 4 #define SR_USPC 4
#define SR_BD_LEN(p) (p & 0xffffff) #define SR_BD_LEN(p) ((p) & 0xffffff)
#define XSF_SUCC 0x1 #define XSF_SUCC 0x1
#define XSF_SHORT 0x3 #define XSF_SHORT 0x3
......
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