Commit 91ec7792 authored by Chen Yu's avatar Chen Yu Committed by Jakub Kicinski

e1000e: Print PHY register address when MDI read/write fails

There is occasional suspend error from e1000e which blocks the
system from further suspending. And the issue was found on
a WhiskeyLake-U platform with I219-V:

[   20.078957] PM: pci_pm_suspend(): e1000e_pm_suspend+0x0/0x780 [e1000e] returns -2
[   20.078970] PM: dpm_run_callback(): pci_pm_suspend+0x0/0x170 returns -2
[   20.078974] e1000e 0000:00:1f.6: PM: pci_pm_suspend+0x0/0x170 returned -2 after 371012 usecs
[   20.078978] e1000e 0000:00:1f.6: PM: failed to suspend async: error -2

According to the code flow, this might be caused by broken MDI read/write
to PHY registers. However currently the code does not tell us which
register is broken. Thus enhance the debug information to print the
offender PHY register. So the next the issue is reproduced, this
information could be used for narrow down.
Acked-by: default avatarPaul Menzel <pmenzel@molgen.mpg.de>
Reported-by: default avatarTodd Brandt <todd.e.brandt@intel.com>
Signed-off-by: default avatarChen Yu <yu.c.chen@intel.com>
Tested-by: default avatarNaama Meir <naamax.meir@linux.intel.com>
Signed-off-by: default avatarTony Nguyen <anthony.l.nguyen@intel.com>
Link: https://lore.kernel.org/r/20220308172030.451566-1-anthony.l.nguyen@intel.comSigned-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 013a3e7c
...@@ -146,11 +146,11 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) ...@@ -146,11 +146,11 @@ s32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
break; break;
} }
if (!(mdic & E1000_MDIC_READY)) { if (!(mdic & E1000_MDIC_READY)) {
e_dbg("MDI Read did not complete\n"); e_dbg("MDI Read PHY Reg Address %d did not complete\n", offset);
return -E1000_ERR_PHY; return -E1000_ERR_PHY;
} }
if (mdic & E1000_MDIC_ERROR) { if (mdic & E1000_MDIC_ERROR) {
e_dbg("MDI Error\n"); e_dbg("MDI Read PHY Reg Address %d Error\n", offset);
return -E1000_ERR_PHY; return -E1000_ERR_PHY;
} }
if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
...@@ -210,11 +210,11 @@ s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) ...@@ -210,11 +210,11 @@ s32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
break; break;
} }
if (!(mdic & E1000_MDIC_READY)) { if (!(mdic & E1000_MDIC_READY)) {
e_dbg("MDI Write did not complete\n"); e_dbg("MDI Write PHY Reg Address %d did not complete\n", offset);
return -E1000_ERR_PHY; return -E1000_ERR_PHY;
} }
if (mdic & E1000_MDIC_ERROR) { if (mdic & E1000_MDIC_ERROR) {
e_dbg("MDI Error\n"); e_dbg("MDI Write PHY Red Address %d Error\n", offset);
return -E1000_ERR_PHY; return -E1000_ERR_PHY;
} }
if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) { if (((mdic & E1000_MDIC_REG_MASK) >> E1000_MDIC_REG_SHIFT) != offset) {
......
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