drm/i915/skl: Implement WaSetGAPSunitClckGateDisable

Let's also take the opportunity the remove the comment telling it's a
pre-prod W/A, it should be obvious from the stepping test.
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Nick Hoath <nicholas.hoath@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

drivers/gpu/drm/i915/i915_reg.h

@@ -6018,6 +6018,7 @@ enum skl_disp_power_wells {
 #define GEN6_RSTCTL				0x9420
 
 #define GEN8_UCGCTL6				0x9430
+#define   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE	(1<<24)
 #define   GEN8_SDEUNIT_CLOCK_GATE_DISABLE	(1<<14)
 
 #define GEN6_GFXPAUSE				0xA000

drivers/gpu/drm/i915/intel_pm.c

@@ -59,9 +59,10 @@ static void skl_init_clock_gating(struct drm_device *dev)
 	if (INTEL_REVID(dev) == SKL_REVID_A0) {
 		/*
 		 * WaDisableSDEUnitClockGating:skl
-		 * This seems to be a pre-production w/a.
+		 * WaSetGAPSunitClckGateDisable:skl
 		 */
 		I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
+			   GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
 			   GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
 	}
 }