Commit 92966a37 authored by Ville Syrjälä's avatar Ville Syrjälä

drm/i915: Disable FDI after the CRT port on LPT-H

Bspec modeset sequence tells us to disable the PCH transcoder and
FDI after the CRT port on LPT-H, so let's do that. And the CRT port
should be disabled after the pipe, as we do on other PCH platforms
too since
commit 1ea56e26 ("drm/i915: Disable CRT port after pipe on PCH platforms")

commit 00490c22 ("drm/i915: Consider SPLL as another shared pll, v2.")
moved the SPLL disable from the .post_disable() hook to some upper
level code, so we can just move the CRT port disabling into the
.post_disable() hook. If we still had the non-shared SPLL, it would have
needed to be moved into the .post_pll_disable() hook.

v2: Actually move the CRT port disable to the .post_disable() hook,
    and amend the commit message with more details (Paulo)
v3: Fix typos in commit message (Paulo)

Cc: Paulo Zanoni <przanoni@gmail.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1449583548-11896-1-git-send-email-ville.syrjala@linux.intel.com
parent a2572f5c
...@@ -844,7 +844,7 @@ void intel_crt_init(struct drm_device *dev) ...@@ -844,7 +844,7 @@ void intel_crt_init(struct drm_device *dev)
crt->adpa_reg = adpa_reg; crt->adpa_reg = adpa_reg;
crt->base.compute_config = intel_crt_compute_config; crt->base.compute_config = intel_crt_compute_config;
if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev)) { if (HAS_PCH_SPLIT(dev)) {
crt->base.disable = pch_disable_crt; crt->base.disable = pch_disable_crt;
crt->base.post_disable = pch_post_disable_crt; crt->base.post_disable = pch_post_disable_crt;
} else { } else {
......
...@@ -5164,18 +5164,17 @@ static void haswell_crtc_disable(struct drm_crtc *crtc) ...@@ -5164,18 +5164,17 @@ static void haswell_crtc_disable(struct drm_crtc *crtc)
if (!intel_crtc->config->has_dsi_encoder) if (!intel_crtc->config->has_dsi_encoder)
intel_ddi_disable_pipe_clock(intel_crtc); intel_ddi_disable_pipe_clock(intel_crtc);
if (intel_crtc->config->has_pch_encoder) {
lpt_disable_pch_transcoder(dev_priv);
intel_ddi_fdi_disable(crtc);
}
for_each_encoder_on_crtc(dev, crtc, encoder) for_each_encoder_on_crtc(dev, crtc, encoder)
if (encoder->post_disable) if (encoder->post_disable)
encoder->post_disable(encoder); encoder->post_disable(encoder);
if (intel_crtc->config->has_pch_encoder) if (intel_crtc->config->has_pch_encoder) {
lpt_disable_pch_transcoder(dev_priv);
intel_ddi_fdi_disable(crtc);
intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
true); true);
}
intel_fbc_disable_crtc(intel_crtc); intel_fbc_disable_crtc(intel_crtc);
} }
......
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